JP2515987Y2 - Field matching circuit - Google Patents

Description

[Detailed description of the device]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video switching device for a camera which switches a plurality of surveillance cameras and outputs a video signal to a monitor or the like. More specifically, the field of video signals from the cameras is matched by a vertical synchronizing signal. Regarding the circuit to make.

[0002]

2. Description of the Related Art In a conventional video switching apparatus, a method for synchronizing the fields in both horizontal and vertical synchronizations so that the image displayed on the monitor is not disturbed when switching the cameras and for matching the fields, and the video signal are temporarily stored. The method of synchronizing the synchronization by storing it in was adopted.

Some recent cameras have a field discriminating circuit built-in. For example, in the NTSC system, if the external vertical synchronizing signal is 30 Hz, the frame can be synchronized.

[0004]

However, in the above-mentioned conventional matching method by horizontal synchronization and vertical synchronization, since the pulse width of the horizontal synchronization pulse is narrow, it is attenuated in the case of a long distance and synchronization is lost. was there. Further, in the matching method using the memory, there is a problem that a frame memory is required and the cost becomes high. Further, in the case of using the field discriminating circuit, the field discriminating circuit is built in the camera, so that the number of parts of the camera is increased and the miniaturization of the camera is affected.

An object of the present invention is to provide a field discrimination circuit on the side of a video switching device, and further to match fields only with a vertical synchronizing signal, so that an image is disturbed when a plurality of remotely operated surveillance cameras are switched. Another object of the present invention is to provide a field matching circuit that does not generate a noise and to downsize the camera.

[0006]

A field matching circuit of the present invention is a video switching device for switching video signals of a plurality of cameras and outputting the video signals to a monitor or the like, in a vertical synchronizing signal generator and the vertical synchronizing signal. A frequency divider that divides the sync signal from the generator, a multiplexer that connects to the selected camera in response to the camera selection signal that selects the camera, and a video signal from the selected camera through this multiplexer. Field discrimination circuit that outputs the discrimination signal by discriminating whether the field of the video signal is an odd field or an even field in response to the pulse from the frequency divider and a single pulse is generated in response to the discrimination signal. A single pulse generating circuit for outputting a synchronization signal to the plurality of cameras and a single pulse superimposed on the synchronization signal and output to the selected camera. Characterized by providing a circuit.

[0007]

In the field coincidence circuit of the present invention, the field discrimination circuit discriminates the field of the video signal from the camera selected by the multiplexer in response to the camera selection signal. As a result, when it is determined that the field is an even (or odd) field, the determination signal is applied from the field determination circuit to the single pulse generation circuit, and in response thereto, a single pulse is output. This single pulse is superimposed on the sync signal via the gate circuit and applied to the camera, which forces the camera field to shift to an odd (or even) field, By performing such a matching operation, the fields of all cameras can be matched.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the structure of a field matching circuit according to an embodiment of the present invention. Reference numeral 6 denotes a vertical sync signal generator for outputting a vertical sync signal, which is normally set to output a vertical sync signal of 60 Hz or 30 Hz in the NTSC system. Since it is not included, the vertical synchronizing signal A of 60 Hz is set to be output so as to correspond to the odd or even field.

Reference numeral 8 is a matching circuit, which is a quarter frequency divider 10,
The multiplexer 12 includes a field discriminating circuit 14, a single pulse generating circuit 16, and a gate circuit 18.
The 1/4 frequency divider 10 divides the vertical synchronizing signal A by 1/4.

The multiplexer 12 switches the video signals from the cameras 1 and 2 to the field discriminating circuit 14 in response to the camera selection signal, and the single switching circuit 16 in response to the camera selection signal. And a second switching circuit 22 for switching and outputting to the gate circuit 18 to apply the single pulse from (1) to the selected camera. The camera selection signal is a signal that is output when the video signal from the camera is switched by the operation of the external operation member in the video switching device, or a signal that is output when the video signal is switched at regular intervals. It is composed of code signals corresponding to the respective cameras.

The field discriminating circuit 14 inputs the video signal of the camera selected by the first switching circuit 20 of the multiplexer 12 and outputs the output signal B of the 1/4 frequency divider 10.
Is input, the even field of the input video signal is detected in synchronization with the rising edge of the signal B, and the discrimination signal C is set to the single pulse generation circuit 16. The field discriminating circuit 14 also inputs the single pulse from the single pulse generating circuit 16 to its clear input CL. In this embodiment, in order to match the field of the camera with the odd field, the even field is set to be discriminated.

The single pulse generation circuit 16 includes a D flip-flop (hereinafter abbreviated as "FF") 24, first and second.
It is composed of one-shot circuits 26 and 28 and a buffer 30. In the FF 24, the D input terminal is fixed to the H level, the discrimination signal C is input to the clock input CK,
The signal D from the output Q is applied to the first one-shot circuit 26. The first one-shot circuit 26 inputs the signal D to the clock input CK, and in the present embodiment, it is 7 ms.
A pulse having a pulse width of ec is generated in the signal E. The second one-shot circuit 28 inputs the signal E to the clock input CK and responds to the fall of the signal E to generate a single pulse having a pulse width of 20 μsec in the signal F in this embodiment. This signal F is the buffer 30
It is applied to the clear input CL of the FF 24 and the field discrimination circuit 14 and the second switching circuit 22 of the multiplexer 12 via the.

The gate circuit 18 receives the vertical synchronizing signal A at one input end thereof and the signal from the second switching circuit 22 of the multiplexer 12 at the other input end thereof, respectively.
It is composed of OR gates 32 and 34 for applying vertical synchronization signals to the cameras 1 and 2, respectively.

Next, the operation of the field matching circuit having the above structure will be described with reference to the time chart shown in FIG. First, when the power is turned on, the fields of the cameras 1 and 2 at this time are not necessarily synchronized. Now, if the camera selection signal is the code signal corresponding to the camera 1, the first and second
The switching circuits 20 and 22 are both in a state of connecting the camera 1 to the field discrimination circuit 14 and the single pulse generation circuit 16, respectively.

Here, the field discrimination circuit 14 is 1 /
In synchronization with the rising edge of the signal B from the divide-by-four frequency divider 10, the first
It is determined whether or not the field of the video signal input from the camera 1 via the switching circuit 20 is an even field. When the field discrimination circuit 14 detects an even field, the output signal C thereof rises to H level.

Therefore, the output signal Q of the FF 24 which inputs the signal C also becomes H level, and in synchronization with the rising of this signal D, the one-shot circuit 26 generates a predetermined pulse in its output signal E. The pulse width of this pulse is the pulse interval of the vertical synchronizing signal A in this embodiment.
It is set to 7 msec, which is almost half of 6.7 msec. The one-shot circuit 28 generates a predetermined pulse in its output signal F in synchronization with the trailing edge of the pulse of the signal E. The pulse width of this pulse in this embodiment is set to be the same as the pulse generated in the vertical synchronizing signal A.

The pulse generated in the signal F is applied to the OR gate 32 via the second switching circuit 22. This pulse is set so as to be generated during the pulse generated in the vertical synchronizing signal A. Therefore, the signal G synthesized by the OR gate 32 is a single signal of the signal F between the pulses of the vertical synchronizing signal A. It becomes a signal that a pulse is generated. As a result, in the camera 1 to which the signal G is input, the field is forcibly shifted between the pulses of the vertical synchronizing signal. When the field of the camera 1 is thus shifted, the field of the camera 1 is always an odd field at the rising edge of the output signal B of the 1/4 frequency divider 10.

At this time, the field discrimination circuit 14
, And FF26 are cleared by the pulse generated in the signal F, and even if the discrimination is newly started in synchronization with the rising of the signal B, the field of the camera 1 is an odd field, and therefore the output signal C thereof is It is kept at L level. That is, once the fields are combined, the rising edge of the signal (signal B) obtained by dividing the vertical synchronizing signal by the power of 2 is:
It is always an odd field and no even field is detected.

Next, the camera selection signal is switched so that the first and second switching circuits 20 and 22 are connected to the camera 2 so that the field becomes an odd field when the signal B rises, as in the above operation. By setting to, the fields of the cameras 1 and 2 can be matched.

When the fields are matched, the field of the camera 2 is adjusted when the image of the camera 1 is displayed on the monitor, and the field of the camera 1 is adjusted when the image of the camera 2 is displayed. It is possible to match the fields without the image disturbance due to the pulse generated at F appearing on the monitor. An example in which the fields are matched when the image from each camera is not displayed on the monitor is shown below.

FIG. 3 is a block diagram showing a circuit configuration of a video switching device using the field matching circuit shown in FIG. Reference numeral 36 is the field matching circuit shown in FIG. 1, and its configuration is the same as that shown in FIG.

A video signal switching circuit 38 includes a timer circuit 40 for generating pulses at predetermined intervals and a one-shot circuit 42 for outputting pulses in response to the output pulse.
An AND gate 44 for inputting the output pulse and the vertical synchronizing signal from the vertical synchronizing signal generator 6, a quinary counter 46 for inputting the output signal to the clock input φ, a signal indicating the count value and the camera 1 A multiplexer 48 for inputting the video signals from 5 to 5 and outputting the video signals from the camera corresponding to the count value of the quinary counter 46 from the sequential video output terminal.

Reference numeral 50 denotes an adder, which inputs the output signal of the quinary counter 46, adds a predetermined value, "1" in the present embodiment, to the count value, and selects a signal indicating the added value by the camera selection. The signal is applied to the coincidence circuit 8 as a signal.

Reference numeral 52 denotes a power supply switching circuit which inputs signals from the quinary counter 46 and the adder 50 and supplies power to the camera corresponding to both output signals. In this embodiment, power is supplied to the camera that applies the video signal to the monitor and then to the camera that applies the video signal.
The power supply switching circuit 52 may be used as a power supply and the code signal from the adder 50 may not be input.

In the video switching device having the above-mentioned structure, the count value of the quinary counter 46 is advanced in response to the output signal of the AND gate 44 which is generated at a constant time interval and is synchronized with the vertical synchronizing signal. A video signal from a camera corresponding to, for example, the camera 1 is output from the multiplexer 48.

At this time, the adder 50 outputs a value obtained by adding "1" to the count value of the quinary counter 46, that is, a camera selection signal corresponding to the camera 2. Therefore, the coincidence circuit 8 for inputting the camera selection signal discriminates the field of the video signal of the camera 2 in the same manner as the above-mentioned operation, and if the field is an even field, it is forcibly shifted and odd-numbered. Fit to the field.

As a result, the field can be matched before the video signal is supplied to the monitor, and it is possible to prevent the image from being disturbed during the field matching operation.

FIG. 4 is a block diagram showing a circuit configuration of another embodiment of the video switching device using the field matching circuit shown in FIG. The same parts as those of the video switching device of FIG. 3 are designated by the same reference numerals. This video switching device is provided with an initial camera selection circuit 59 including a timer 54, a latch circuit 60, and a switching circuit 62 in addition to the field matching circuit 36 and the video signal switching circuit 38. In the configuration shown in FIG. 4, the first switching circuit 20 in the multiplexer 12 of the coincidence circuit 8 is also omitted.

That is, in this video switching device, FIG.
The first switching circuit 20 shown in FIG. 2 is removed, and an OR gate 58 is provided between the AND gate 44 and the quinary counter 46 in the video signal switching circuit 38, and output signals of the AND gate 44 and the timer 54 are output via the OR gate 58. It is configured to be applied to the quinary counter 46. Further, when the count value of the quinary counter 46 makes one round, the end signal is sent to the timer 4
A latch circuit 60 for outputting 0, 54, and a switching circuit 62 for switching and outputting the video signal from the multiplexer 48 are provided to the field discrimination circuit 14 in the coincidence circuit 8 and the sequential video output in response to the end signal. .

In this video switching device, when the power is turned on, the timer 54 operates and its output pulse is applied to the quinary counter 46 via the OR gate 58.
As a result, the quinary counter 46 advances the count value, and the multiplexer 48 sequentially switches and outputs the video signal from the camera in response to the count value.

At this time, the switching circuit 62 is in a state of applying the video signal from the multiplexer 48 to the field discriminating circuit 14 in the coincidence circuit 8, and the fields of all the cameras are sequentially coincident.

After that, when the end signal is output from the latch circuit 60, the timer 54 is stopped in response to this, the timer 40 is activated, and the switching circuit 62 switches its state to output the video to the sequential video output. It is ready to output signals. Therefore, the quinary counter 46 advances its count by the signal from the timer 40, and the video signal output by the multiplexer 48 is also supplied from the sequential video output to the monitor. As described above, also in the apparatus shown in FIG. 4, the fields of all the cameras are matched before the video signals from the cameras are supplied to the monitor.

[0033]

According to the present invention, the field discriminating circuit is provided on the video switching device side, and the field can be matched only by the vertical synchronizing signal, whereby the camera can be downsized and a plurality of remote control devices can be operated. It is possible to prevent the image from being disturbed when the surveillance camera is switched.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a field matching circuit of the present invention.

FIG. 2 is a time chart of signals in FIG.

FIG. 3 is a block diagram showing a configuration of a video switching device using the field matching circuit shown in FIG.

4 is a block diagram showing the configuration of another video switching device using the field matching circuit shown in FIG. 1. FIG.

[Explanation of symbols]

 1 to 5 camera 6 vertical synchronization signal generator 8 coincidence circuit 10 1/4 frequency divider 12 multiplexer 14 field discrimination circuit 16 single pulse generation circuit 18 gate circuit 36 field coincidence circuit 38 video signal switching circuit 50 adder 59 initial camera selection circuit

Claims (3)

(57) [Scope of utility model registration request] 1. A video switching device for switching video signals of a plurality of cameras and outputting the video signals to a monitor or the like, wherein a vertical synchronizing signal generator and a frequency dividing for dividing a synchronizing signal from the vertical synchronizing signal generator. And a multiplexer connected to the selected camera in response to a camera selection signal for selecting the camera, and a pulse from the frequency divider for inputting the video signal from the selected camera through the multiplexer. A field discriminating circuit for discriminating whether the field of the video signal is an odd number field or an even number field and outputting a discrimination signal, a single pulse generating circuit for generating a single pulse in response to the discrimination signal, A gate circuit that outputs a synchronization signal to the plurality of cameras and outputs the single pulse to the selected camera by superimposing the synchronization signal on the synchronization signal. Field matching circuit characterized by and. 2. A video switching device for switching video signals of a plurality of cameras according to a camera selection signal and outputting the video signals to a monitor or the like, and adding a predetermined value to the camera selection signal and outputting the camera selection signal. A vertical synchronizing signal generator, a divider for dividing the synchronizing signal from the vertical synchronizing signal generator, and a multiplexer connected to the selected camera in response to the camera selection signal from the adder. ,
The video signal from the selected camera is input through the multiplexer, and in response to the pulse from the frequency divider, it is determined whether the field of the video signal is an odd field or an even field, and a determination signal is output. A field discrimination circuit for generating a single pulse in response to the discrimination signal, a single pulse generation circuit for outputting the synchronization signal to the plurality of cameras, and outputting the single pulse to the selected camera as the synchronization signal. A video switching device comprising: a gate circuit for superimposing and outputting. 3. A video switching device for switching video signals of a plurality of cameras according to camera selection signals and outputting the video signals to a monitor or the like, wherein the camera selection signals are sequentially output when the power is turned on, and the video signals are output until the output ends. An initial camera selection circuit for preventing output to a monitor or the like, a vertical synchronization signal generator, a frequency divider for dividing a synchronization signal from the vertical synchronization signal generator, and an operation circuit for operating the initial camera selection circuit. A multiplexer connected to the selected camera in response to the camera selection signal, and a video signal from the selected camera input through the multiplexer to output the video signal of the video signal in response to the pulse from the frequency divider. A field discrimination circuit for discriminating whether the field is an odd field or an even field and outputting a discrimination signal, and a single pulse in response to the discrimination signal. And a gate circuit that outputs the synchronization signal to the plurality of cameras and that outputs the single pulse to the selected camera by superimposing the synchronization signal on the synchronization signal. Video switching device.