JPH0481075A - Digital black burst signal generator - Google Patents

Abstract

PURPOSE:To shorten time for locking synchronism by loading a prescribed data among first and second data for each field and generating a vertical address by counting a horizontal synchronizing signal. CONSTITUTION:This device is equipped with a data generation circuit 1, frame counter circuit 2, line selection circuit 3, horizontal counter circuit 4 and digital black burst signal generation circuit 5. When a vertical synchronizing signal VA is set to logic 'L' at time t1, the frame counter circuit 2 loads the first data and when the vertical synchronizing signal VA is turned to logic 'H', the counter counts horizontal synchronizing signals and outputs the vertical address. When the signal is switched to a mutually synchronous vertical synchronizing signal VB at time2, an asynchronous state is continued until the vertical synchronizing signal VB is turned to logic 'L', and when the vertical synchronizing signal VB is turned to the logic 'L' at time3, the second data is loaded. When the vertical synchronizing signal VB is turned to the logic 'H', the counter counts horizontal synchronizing signals and outputs the vertical address. Thus, after switching, time for locking synchronism is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital black burst signal generator used in video signal equipment and the like, and particularly to an interlaced digital black burst signal generator.

[Conventional technology]

The digital black burst signal is the “black” signal of the video signal.
It is a digitized signal consisting only of synchronization signal components and burst signal components. FIG. 3 is a block diagram showing an example of a conventional digital black burst signal generator, which includes a frame counter circuit 6, a line selection circuit 7, a horizontal counter circuit 8, and a digital black burst signal generation circuit 9. There is.

The frame counter circuit 6 has a frame synchronizer logic “
When the frame synchronization signal becomes logic "L", the vertical phase adjustment data for phase adjustment to be applied to the vertical synchronization signal is loaded, and then when the frame synchronization signal becomes logic "H", the counter counts the horizontal synchronization signal and outputs the vertical phase adjustment data for phase adjustment to be applied to the vertical synchronization signal. After one frame period has elapsed, when the frame synchronization signal becomes logic "L", the vertical phase adjustment data is loaded again, the counter is reset, and the frame synchronization signal becomes logic "L" again. When it becomes "H", it outputs the vertical address.Line selection pad 7 is NTS
This is a circuit that selects and outputs a pattern number set for each signal pattern of 525 lines of one C-system frame, and outputs a pattern number corresponding to the vertical address generated by the frame counter circuit 6. The horizontal counter circuit 8 is a circuit that generates a horizontal address for generating a digital black burst signal, and similarly to the frame counter circuit 6, when the horizontal synchronization signal becomes logic "L", it responds to the horizontal synchronization signal. Load the horizontal phase adjustment data for phase adjustment, then the horizontal synchronization signal is
When it becomes "H", the counter counts clock pulses corresponding to the number of horizontal pixels and outputs the horizontal address. The digital black burst signal generation circuit 9 receives the pattern number output from the line selection circuit 7 and the horizontal address output from the horizontal counter circuit 8, and generates a digital black burst signal for each line corresponding to the pattern number. Generate and output a burst signal.By repeating this operation for 525 lines, 1
A digital black burst signal for one frame is generated.

[Problem to be solved by the invention]

In the conventional digital black burst signal generator described above, when a vertical address is generated by a frame counter circuit, the counter is reset by loading vertical phase adjustment data in synchronization with a frame synchronization signal. Therefore, when operating the digital black burst signal generator by switching to mutually asynchronous synchronous signals, the time required to lock to the synchronous signal after switching is at most 1.
There is a drawback that it becomes a one-frame period (two-field period).

An object of the present invention is to provide a digital black burst signal generator that can shorten the time required for synchronization lock after switching to mutually asynchronous synchronization signals.

[Means to solve the problem]

A digital black burst signal generator of the present invention includes means for outputting first and second data for adjusting the phase of a vertical synchronization signal according to field identification signals indicating odd and even fields; means for generating and outputting a vertical address by counting horizontal synchronizing signals after loading one of the first and second data according to the above, and a means set for each signal pattern of each line of one frame. means for selecting and outputting a pattern number according to the vertical address; means for counting the horizontal synchronization signal and a clock signal corresponding to the number of horizontal pixels to generate and output a horizontal address for each line; and means for generating and outputting a digital black burst signal according to the number and the horizontal address, and the second data has the same value as the vertical address value one frame period after loading the first data. This is the configuration that is set so that it can be obtained.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, which includes a data generation circuit 1, a frame counter circuit 2, a line selection circuit 3, a horizontal counter circuit 4, and a digital black burst signal generation circuit 5.

The data generation circuit 1 receives vertical phase adjustment data for adjusting the phase of a field identification signal and a vertical synchronization signal indicating odd and even fields, and generates first and second signals corresponding to the odd and even fields. Generate and output data. When the vertical synchronization signal becomes logic "L", the frame counter circuit 2
When the vertical synchronization signal becomes logic "H", the counter counts the horizontal synchronization signal and outputs a vertical address. After one field period has elapsed, the second data is loaded when the vertical synchronization signal becomes logic "L" again. The second data is set to be the same as the output value of the counter at the time when one field period has elapsed.

Next, when the vertical synchronizing signal becomes logic "H" again, a vertical address is outputted. Therefore, the output of the frame counter circuit 2 is the same as the output of the conventional frame counter circuit 6. The line selection circuit 3 is a circuit that classifies the signal pattern of each line of 525 lines in one frame of the NTSC system, selects and outputs a pattern number set for each pattern, and uses the vertical address generated by the frame counter circuit 2. Correspondingly output the pattern number. The horizontal counter circuit 4 is a circuit that generates a horizontal address for generating a digital black burst signal, and when the horizontal synchronization signal becomes logic "L", it performs horizontal phase adjustment for phase adjustment with respect to the horizontal synchronization signal. When data is loaded and then the horizontal synchronizing signal becomes logic "H", a counter counts clock pulses corresponding to the number of horizontal pixels and generates a horizontal address for each line. The digital black burst signal generation circuit 5 receives the pattern number output from the line selection circuit 3 and the horizontal address output from the horizontal counter circuit 4, and generates a digital black burst signal for each line corresponding to the pattern number. Output. By repeating this operation for 525 lines, a digital black burst signal for one frame is generated.

Next, the operation of the frame counter circuit 2 will be explained with reference to FIG. In the figure, when the vertical synchronization signal VA becomes logic "L" at time t1, the first data is loaded, and then when the vertical synchronization signal VA becomes logic "H", the counter counts the horizontal synchronization signal. output the vertical address.

When switching to the mutually asynchronous vertical synchronizing signal V8 at time t2, the unsynchronized state continues until the vertical synchronizing signal V8 becomes logic "L". When the vertical synchronization signal VB becomes logic "L" at time t3, the second data is loaded, and then when the vertical synchronization signal V8 becomes logic "H", the counter counts the horizontal synchronization signal and reads the vertical address. Output. Therefore, after time t3, a synchronized state is established, and a synchronized digital black burst signal can be generated. In this way, the time required to lock onto the synchronizing signal can be set to one field period at most.

〔Effect of the invention〕

As explained above, according to the present invention, a data generation circuit is provided that outputs first and second data according to a field identification signal that identifies odd and even fields, and the first and second data are generated for each field. By loading predetermined data, counting the horizontal synchronizing signals, and generating vertical addresses, it is possible to lock to the synchronizing signal when switching to mutually asynchronous vertical synchronizing signals and operating the digital black burst signal generator. This has the effect of reducing the time required to complete the process by half of that of the conventional method, that is, to a maximum of one field period.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the operation of a frame counter circuit 2, and FIG. 3 is a block diagram showing an example of a conventional digital black burst signal generator. 1... Data generation circuit, 2, 6... Frame counter circuit, 3, 7-... Line selection circuit, 4, 8... Horizontal counter circuit, 5.9...
...-Digital black burst signal generation circuit.

Claims (1)

[Claims] means for outputting first and second data for adjusting the phase of a vertical synchronization signal according to field identification signals indicating odd and even fields; and means for outputting first and second data according to the vertical synchronization signal. means for generating and outputting a vertical address by counting horizontal synchronizing signals after loading any one of the above, and selecting a pattern number set for each signal pattern of each line of one frame according to the vertical address. means for generating and outputting a horizontal address for each line by counting the horizontal synchronizing signal and a clock signal corresponding to the number of horizontal pixels; and generating a digital black burst signal according to the pattern number and the horizontal address. generating means, wherein the second data is set to have the same value as the vertical address value one frame period after loading the first data. generator.