JPH11266467A - Test pattern generator for image display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test pattern generator for an image display that makes best use of functions of an existing image display. SOLUTION: The proposed test pattern generator is provided with a VCO 1 that is oscillated at a frequency in response to a horizontal synchronizing signal frequency, a horizontal count-down circuit 2 that frequency-divides an oscillated output signal of the VCO 1, generates a horizontal output pulse as well as a plurality of frequency-division signals by combining various frequency division outputs, a vertical count-down circuit 3 that frequency-divides a vertical synchronizing signal based on the 1st frequency division signal from the horizontal count-down circuit 2 as a clock signal to generate a vertical pulse and generates a plurality of frequency division signals by combining various frequency division signals, a self-reset circuit 4 that self-resets the vertical count- down circuit 3 when it is detected that no vertical synchronizing signal is applied externally to the vertical count-down circuit 3 and the image display device is set to test mode, and a mixer 5 that mixed the frequency division output signal of the vertical count-down circuit 3 and the frequency division output signal of the horizontal count-down circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for generating a test pattern signal used in manufacturing and repairing an image display device such as a television receiver or a computer display device. The present invention relates to a test pattern generation device for an image display device using a function existing in the device as much as possible.

[0002]

2. Description of the Related Art In an image display device such as a television receiver or a computer display device, it is necessary to adjust the position of a display screen. In addition, white balance adjustment is required. To perform such adjustment, a test pattern signal for screen position check such as a cross hatch is required.

[0005] Such a test pattern signal for screen position check is required at the time of manufacturing or repairing an image display device. Conventionally, a test pattern signal has been obtained from a dedicated test pattern signal source existing as one device.

[0004]

However, there is a problem that it takes time and effort to prepare a dedicated test pattern signal source. Particularly, when a serviceman visits and repairs a home, it is difficult to carry the signal source.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and comprises a VCO which oscillates at a frequency corresponding to the horizontal synchronizing signal frequency, and a frequency-divided output signal of the VCO. A horizontal countdown circuit that generates a horizontal output pulse and generates a plurality of frequency-divided signals by combining various frequency-divided outputs; and a frequency-divided first frequency-divided signal of the horizontal countdown circuit as a clock signal. A vertical countdown circuit that generates an output pulse and generates a plurality of frequency-divided signals by combining various frequency-divided outputs. An external vertical synchronization signal is not applied to the vertical countdown circuit, and the image display device enters a test mode. A self-reset circuit that self-resets the vertical countdown circuit when the vertical countdown circuit is detected. Characterized in that to obtain a test pattern signal from the mixer and hints the mixer for mixing the divided output signal of the divided output signal and the horizontal countdown circuit.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A test pattern generator for an image display device according to the present invention will be described with reference to FIG. 1 is a VCO that oscillates at a frequency corresponding to the horizontal synchronization signal frequency, and 2 is the VCO
The oscillation output signal of CO1 is divided and a horizontal output pulse Hou is output.
a horizontal countdown circuit for generating a plurality of frequency-divided signals by combining t and various frequency-divided outputs; 3 divides the first frequency-divided signal of the horizontal countdown circuit 2 as a clock signal CK and outputs a vertical signal. The vertical countdown circuit 4 that generates a pulse Vout and generates a plurality of frequency-divided signals by combining various frequency-divided outputs is not applied to the vertical countdown circuit 3 from the outside. A self-reset circuit that self-resets the vertical countdown circuit when it is detected that the output of the vertical countdown circuit 3 is mixed with the frequency-divided output signal of the horizontal countdown circuit 2 OR gate, 6 operates as a blankin which generates horizontal and vertical blanking signals A signal generating source 7 is an adder for adding the output signal of the OR gate 5 to the horizontal and vertical blanking signals, and 8 is selectively switching between the output signal of the adder 7 and the luminance signal from the luminance signal processing circuit 9. Switch.

One of the features of the present invention is that a test pattern signal can be created using an existing circuit block. Therefore, a case where the television receiver shown in FIG. 1 is used in a normal usage will be described first. In this case, the switch 8 has fallen to the terminal a because no test mode signal is applied. A composite video signal is applied to the input terminal 10. The composite video signal is signal-processed by a luminance signal processing circuit 9 including a block for performing various luminance signal processing such as a clamp circuit 11.

On the other hand, the horizontal synchronizing signal H and the vertical synchronizing signal V in the composite video signal are synchronously separated by the synchronous separation circuit 12. The horizontally separated horizontal synchronization signal H is a VCO 1 that oscillates at a frequency 256 times the horizontal synchronization signal frequency fH.
The phase comparator 13 compares the phase of the oscillation output signal with a signal obtained by dividing the oscillation output signal by 256 (an integer multiple of the horizontal synchronizing signal frequency fH can be used as a clock of a comb filter for other purposes). The result of the phase comparison is converted into a direct current and then fed back to the VCO 1. In other words, this is A
An FC circuit will be formed.

The phase-synchronized oscillation output signal of the VCO 1 is applied to the horizontal countdown circuit 2 as a clock signal CK. The horizontal countdown circuit 2 has a plurality of D-type flip-flops connected in series.
A plurality of frequency-divided signals are obtained by combining frequency-divided outputs of a flip-flop with an AND gate or the like. As one of them, the horizontal output pulse Hout is led out to the terminal 14.

The vertical synchronization signal V separated from the synchronization is:
The signal is applied to the reset terminal R of the vertical countdown circuit 3 via the OR gate 15. Vertical countdown circuit 3
Counts (divides) the clock signal (frequency 2fH) from the horizontal countdown circuit 2 from the reset release timing. Similarly to the horizontal countdown circuit 2, the vertical countdown circuit 3 includes a plurality of D-type flip-flops connected in series, and obtains a plurality of frequency-divided signals by combining the divided outputs of the plurality of D-type flip-flops with an AND gate or the like. Like that. The vertical countdown circuit 3 derives a vertical output pulse Vout to a terminal 16.

The horizontal and vertical deflections of the CRT are performed by the horizontal output pulse Hout and the vertical output pulse Vout. On the other hand, since the switch 8 is tilted to the a side, the luminance signal from the luminance signal
After the signal amplitude and the DC level are adjusted in the bright circuit 17, the signal is applied to the RGB matrix circuit 18. R
A color difference signal from a color difference signal source 19 is applied to a GB matrix circuit 18, a matrix of a luminance signal and a color difference signal is obtained, and three primary color signals of RGB are applied to a drive cutoff circuit 20. In the drive cutoff circuit 20, 3
The amplitude and DC level of the primary color signal are adjusted according to the color balance.

The three primary color signals of RGB are deflected by the CRT by the above-mentioned horizontal output pulse Hout and vertical output pulse Vout, and a screen display is performed. Next, a case where a test pattern is required when the image display device is manufactured at a factory or when a service person repairs the image display device will be described. Conventionally, it was necessary to apply a test pattern signal of a white level to the input terminal 10, but this is not necessary according to the present invention.

According to the present invention, a command indicating that the test mode has been entered is applied from the terminal 21 to the switch 8, and the contact is switched to the side b. Also, a command indicating that the test mode has been entered is applied to the self-reset circuit 4 from the terminal 22 to operate the self-reset circuit 4. The self-reset circuit 4 is configured so that the vertical countdown circuit 3
At 2.5H), a self-reset pulse for self-reset is generated.

Note that the vertical countdown circuit 3 needs a self-reset pulse for self-resetting even when there is no signal to which a vertical synchronizing signal is not externally applied.
The self-reset circuit 4 is an existing one. On the other hand, a command indicating that the test mode has been entered is also applied to the terminal 23 and causes the VCO 1 to oscillate at the free-run frequency. (Because the horizontal synchronizing signal does not arrive in the test mode, some types of VCO 1 automatically oscillate at the free-run frequency.) This oscillation output signal is applied to the horizontal countdown circuit 2 and the vertical countdown circuit 3 These signals are used as reference signals for these timings.

From the horizontal countdown circuit 2, 26
20H to 22H, 130H to 13 in 2.5H cycle
The internal logic gate is configured such that an “H” level signal is generated during three periods of 2H, 248H to 250H. This is shown in FIG. Also, from the vertical countdown circuit 3, three cycles of 9.5 to 10 microseconds, 33.5 to 34 microseconds, and 57.5 to 58 microseconds in a 64 microsecond cycle
An internal logic gate is configured such that an "H" level signal is generated during one period. This is shown in FIG.

A test pattern signal can be created by using the "H" level signals from the horizontal countdown circuit 2 and the vertical countdown circuit 3. This test pattern signal is always generated during the operation of the horizontal countdown circuit 2 and the vertical countdown circuit 3, but is generated outside only in response to a command from the terminal 22 indicating that the test mode has been entered. These two signals are applied to the OR gate 5. After passing through the OR gate 5, a blanking signal is added and applied to the switch 8. After that, it is processed in the same manner as in the normal operation and converted into RGB primary color signals.

[0017]

According to the present invention, since a test pattern signal can be created by using a block built in an image display device, there is no problem that it takes time to prepare a dedicated test pattern signal source. This is particularly effective when a serviceman visits and repairs a home.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a test pattern generator of an image display device according to the present invention.

FIG. 2 is a diagram showing a test pattern of the image display device of the present invention.

[Explanation of symbols]

 1 VCO 2 horizontal countdown circuit 3 vertical countdown circuit 4 self reset circuit 5 OR gate 8 switch

Claims (3)

[Claims] 1. A VCO that oscillates at a frequency corresponding to a horizontal synchronizing signal frequency, divides an oscillation output signal of the VCO to create a horizontal output pulse, and combines various divided outputs to generate a plurality of divided signals. And a horizontal countdown circuit for generating a frequency-divided signal by generating a vertical output pulse and combining various frequency-divided outputs to generate a plurality of frequency-divided signals. A vertical countdown circuit, a self-reset circuit that self-resets the vertical countdown circuit when it is detected that a vertical synchronization signal is not applied to the vertical countdown circuit from the outside and the image display device is in a test mode, The divided output signal of the countdown circuit and the divided output signal of the horizontal countdown circuit The test pattern generator of the image display apparatus being characterized in that to obtain a test pattern signal from including the mixer and mixer for mixing the. 2. A VCO that oscillates at a frequency corresponding to the horizontal synchronization signal frequency, divides an oscillation output signal of the VCO to create a horizontal output pulse, and combines various divided outputs to generate a plurality of divided signals. And a horizontal countdown circuit for generating a frequency-divided signal by generating a vertical output pulse and combining various frequency-divided outputs to generate a plurality of frequency-divided signals. A vertical countdown circuit, a self-reset circuit that self-resets the vertical countdown circuit when it is detected that a vertical synchronization signal is not applied to the vertical countdown circuit from the outside and the image display device is in a test mode, The divided output signal of the countdown circuit and the divided output signal of the horizontal countdown circuit And an adder for adding an output signal of the mixer and a horizontal and vertical blanking signal to obtain a test pattern signal from the adder. Test pattern generator. 3. A VCO that oscillates at a frequency corresponding to the horizontal synchronization signal frequency, divides an oscillation output signal of the VCO to create a horizontal output pulse, and combines various divided outputs to generate a plurality of divided signals. And a horizontal countdown circuit for generating a frequency-divided signal by generating a vertical output pulse and combining various frequency-divided outputs to generate a plurality of frequency-divided signals. A vertical countdown circuit, a self-reset circuit that self-resets the vertical countdown circuit when it is detected that a vertical synchronization signal is not applied to the vertical countdown circuit from the outside and the image display device is in a test mode, Mixing the divided output signal of the countdown circuit and the divided output signal of the horizontal countdown circuit A mixer for adding the output signal of the mixer and the horizontal and vertical blanking signals, and a switch for selectively switching the output signal of the adder and the luminance signal from the luminance signal processing circuit. A test pattern generator for an image display device, wherein a test pattern signal is obtained from the switch.