JPH04111577A - Vertical synchronizing circuit - Google Patents

Abstract

PURPOSE:To perform the decision of a non-reference mode even against signals alternately switching from 262H to 263H for each one field by adding simple circuit elements (about 20 gate) CONSTITUTION:A NAND circuit 110 and a NAND circuit 111 are added on the conventional circuit. The NAND circuit 111 outputs a mode set signal MS when all the input becomes '1', while in the NAND circuit 110, Q2, Q4, Q6 of the shift output of input become all '1' when the states of synchronization/ non-synchronization of a timing signal T1 and an external vertical synchronizing signal Vin continue for each one field four times to be inputted to a flip-flop circuit 113. Therefore, the timing signal continuing for each one vertical cycle can be detected, and the synchronizing step-out of the signal can be detected. Thus, even to the signal where the vertical period switches for each one field from 262H to 263H alternately, the non reference mode can be decided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a vertical synchronization circuit for a television receiver or the like, and in particular to a circuit that improves the vertical mode detection circuit.

(Prior Art) A vertical synchronization circuit is used in a system that handles television signals. There is a frequency division type vertical synchronization circuit. This method generates a vertical period signal (internal vertical synchronization signal) by dividing a clock signal with a frequency of n times fh (n is a natural number, fh is the horizontal frequency) that is phase synchronized with the horizontal synchronization signal of the input signal. I try to do that. With this method, a stable synchronization signal can be continuously reproduced even if an external synchronization signal that has been subjected to disturbances such as a weak electric field or a ghost is input.

This frequency-dividing vertical synchronization circuit is suitable for generating various timing signals and memory control signals in digital television receivers that use image memory, etc., which have been put into practical use due to advances in digital technology in recent years. ing.

In a vertical synchronization circuit using the frequency division method, the vertical frequency fv,
The horizontal frequency fh is f v - (11525) ・2 f h - (1
), and if it is a standard signal that satisfies this relationship, stable synchronous reproduction is performed from the frequency division counter, and if it is a non-standard signal that does not satisfy the above relationship, it is performed from the input vertical synchronization signal. Processing is performed to perform direct synchronous playback.

Non-standard signals include special playback from video tape recorders and signals from television games.

FIG. 3 is an example of a conventional frequency division type vertical synchronization circuit.

An nfh clock signal synchronized with the horizontal synchronization signal in the input signal is input to the vertical counter 502 via the input terminal 501. Vertical counter 502 is a vertical period counter, and supplies its count output to reset generator 503 and timing pulse generator 504.

The reset generator 503 outputs a reset pulse at a predetermined count value of the vertical counter 502, and
Supply to 02. A timing pulse generator 504 generates various timing pulses using the count value of the vertical counter 502.

The timing signal T1 generated here is transmitted to the inverting circuit 50.
6 and is also input to the coincidence continuity detector 507. Furthermore, the timing signal T2 is transmitted to the out-of-sync detector 50.
5 is input.

The timing signal T1 is approximately 24 us centered around the standard vertical period (525/2 horizontal period for NTSC signals).
ecST2 is a pulse with a width of approximately 250 μsec.

The out-of-sync detector 505 performs a phase comparison between the timing signal T2 and an external vertical synchronization signal from the input terminal 508,
If out of synchronization, a phase pull-in signal PL is output. When the synchronization is lost and the phase pull-in signal PL is output, the timing signal T2 is a pulse with a wide pulse width, so
Reset generator 503 is set to reset vertical counter 502 unconditionally.

The inverting circuit 506 inverts the timing signal T1 and outputs it to the data input terminal of the shift register 509 and the NAND circuit 51.
0. An external vertical synchronization signal is supplied to the clock input terminal of the shift register 509.

The coincidence continuity detector 507 determines whether the external vertical synchronization signal is continuously obtained during the pulse width of the timing signal T1, outputs a mode reset signal MR, and supplies it to the reset input terminal of the flip-flop circuit 511. are doing. On the other hand, the shift register 509 operates using an external vertical synchronization signal as a clock, and outputs a 3-bit shift output (Ql
, Q2, Q3). The NAND circuit 510 receives an external vertical synchronization signal, an inverted timing signal T1, and a shift output (
Ql, Q2, Q3) are input, and all are “1”.
When this happens, a mode set signal MS is output. If all of them become 1'', this is the case when no external vertical synchronization signal is continuously present within the width of the timing signal T1.

The output of the flip-flop circuit 511 is output as a vertical mode signal VM, and is input to the reset generator 503. When the vertical mode signal vM indicates asynchronous (when the flip-flop circuit 511 is set), the reset generator 503 busses an external vertical synchronization signal and supplies it to the vertical counter 502 as a reset signal.

When the vertical mode signal VM indicates a synchronous state (when the flip-flop circuit 511 is reset), the reset generator 503 outputs a reset pulse in response to a predetermined count value of the vertical counter 502.

FIG. 4 shows a timing chart for explaining the operation of the above vertical synchronization circuit.

FIG. 4(A) shows that the timing signal T1 is at a predetermined phase with respect to the external vertical synchronization signal Vin, indicating a synchronized state. Shift outputs Q1, Q2, Q3 and vertical mode signal VM are at low level.

FIG. 4(B) is a timing chart when synchronization is lost, and a signal for resetting the vertical counter 502 is obtained at time t1.

In Figure 4 (C), the vertical period is 262H per field.
A timing chart is shown in the case of alternating with /263H.

Such a signal in which 262H/263H are alternately switched is obtained, for example, when a still image is obtained when a digital memory is used in special playback of a VTR, or when an output from an electronic still camera is supplied. The reason for performing such switching is to scan the same location in each field instead of interlace scanning one field of images, thereby preventing line flicker from occurring.

However, in this case, the vertical synchronization circuit shown in FIG.
) are not met, so the vertical mode signal V
M never changes. Thus, the vertical counter operates in standard mode and you get normal interlacing on the screen. Furthermore, if a non-standard mode signal such as the one described above is input to the system, line flickering will occur and the screen will deteriorate. Also, such 262H, which is non-standard for signal processing that performs inter-frame calculations,
If the repetitive signal of /263H is regarded as the standard and calculated, the image subjected to signal processing will be degraded.

(Problems to be Solved by the Invention) As described above, according to the conventional vertical synchronization circuit, in the case of a signal in which the vertical period alternates between 262H/263H for each field, the vertical mode is determined to be the standard mode. This results in deterioration of image quality.

Therefore, in this invention, the vertical period is 262 per field.
It is an object of the present invention to provide a vertical synchronization circuit that can determine a non-standard mode even for signals alternately switched with H/263H and obtain appropriate vertical synchronization.

[Structure of the Invention] (Means for Solving the Problems) This invention provides a clock signal having a frequency fh (n is a predetermined natural number, fh is a horizontal frequency) times n times synchronized in phase with a horizontal synchronizing signal of an input video signal. a frequency division counter which uses the clock signal as a clock input and a counter reset signal as a reset input; and a timing signal having a standard vertical period and a predetermined width by manually inputting the output of the frequency division counter. A timing generation circuit to output, the timing signal and an external vertical synchronization signal are input, and the standard mode set signal is output only when the external vertical synchronization signal is continuously obtained during the period in which the timing signal is generated. A coincidence continuous detection circuit that outputs a match continuous detection circuit, a flip-flop circuit that is reset by the standard mode set signal when it is output and outputs a mode signal indicating the standard mode, and a mode signal output from this flip-flop circuit. When the mode signal indicates a standard mode, the reset signal is outputted at a predetermined value of the frequency division counter, and when the mode signal indicates a non-standard mode, the external vertical synchronization signal is outputted to the frequency division counter. a reset generator for supplying the reset signal, the means for setting the flip-flop circuit to output a mode signal indicating the non-standard mode, the timing signal being a data input, and the external vertical synchronization signal being a data input; The shift register includes a predetermined number of stages of shift registers used as a clock, and means for detecting a pattern that continues two or more times in at least every other stage of the shift register.

(Function) With the above means, it is possible to detect successive timing signals every other vertical period, so it is also possible to detect out-of-synchronization of such signals. Therefore, a non-standard mode can be determined even for a signal whose vertical period alternates between 262H and 263H for each field.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of this invention.

An nfh clock signal synchronized with the horizontal synchronization signal in the input signal is input to the vertical counter 102 via the input terminal 101. The vertical counter 102 is a vertical period counter, and supplies its count output to a reset generator 103 and a timing pulse generator 104.

The reset generator 103 outputs a reset pulse at a predetermined count value of the vertical counter 102, and
Supply to 02. The timing noise generator 104 is
Various timing pulses are generated using the count value of the vertical counter 102.

The timing signal T1 generated here is transmitted to the inverting circuit 10.
6 and is also input to the coincidence continuity detector 107 . Further, the timing signal T2 is transmitted to the out-of-synchronization detector 10.
5 is input.

The timing signal T1 is approximately 24 μs centered around the standard vertical period (525/2 horizontal period for NTSC signals).
ec, T2 is a pulse with a width of about 250 μsec.

The out-of-synchronization detector 105 compares the phase of the timing signal T2 and the external vertical synchronization signal Vin from the input terminal 108, and outputs a phase pull-in signal PL in the case of out-of-synchronization. When the synchronization is lost and the phase pull-in signal PL is output, the timing signal T2 is a pulse with a wide pulse width, so it is thought that the input signal is switched and a large phase shift occurs, so the reset generator 103 is unconditionally activated. The vertical counter 502 is set to be reset.

The inverting circuit 106 inverts the timing signal T1 and outputs it to the data input terminal of the shift register 109 and the NAND circuit 11.
0, is supplied to the NAND circuit 111. The clock input terminal of the shift register 109 receives an external vertical synchronization signal V1.
n is supplied.

The coincidence continuity detector 107 determines whether the external vertical synchronization signal Vin is continuously obtained during the pulse width of the timing signal T1, and outputs a mode reset signal MR.
It is supplied to the reset input terminal of the flip-flop circuit 113. On the other hand, the shift register 109 is a 6-bit shift register that operates using the external vertical synchronization signal Vln as a clock, and outputs (Ql, Q2, Q3, Q4°Q
5, Q6) is output.

Here, the NAND circuit 110 receives external vertical synchronization signals VIn,
Inverted timing signal T1, shift output (Ql, Q2, Q
3) as input, and outputs a mode set signal MS when all of them become "1". If all of them become "12", this is the case when the external vertical synchronization signal does not exist within the width of the timing signal T1 four times in a row.

On the other hand, the NAND circuit 111 receives the inverted timing signal T1 and the external vertical synchronization signal VIn as its inputs.

Shift outputs Q2, Q4, and Q6 are set.

This shift output becomes all "1" when a state in which the timing signal T1 and the external vertical synchronization signal V1n are synchronized and asynchronous every other field occurs four times in a row. The outputs of the NAND circuits 110 and 111 are connected to the OR circuit 112.
and is input to the set input terminal of the flip-flop circuit 113 as a mode set signal signal.

The output of the flip-flop circuit 113 is output as a vertical mode signal VM and input to the reset generator 103. When the vertical mode signal VM indicates asynchronous (when the flip-flop circuit 113 is set), the reset generator 103 busses the external vertical synchronization signal and supplies it to the vertical counter 102 as a reset signal.

When the vertical mode signal VM indicates a synchronous state (when the flip-flop circuit 113 is reset), the reset generator 503 outputs a reset pulse in response to a predetermined count value of the vertical counter 502.

FIG. 2 is a timing chart shown to explain the operation of the above circuit. This shows a case where an external vertical synchronization signal Vin is input in which the vertical period alternates between 262H and 263H for each field.

In this case, the external vertical synchronization signal V1n is out of synchronization every other field with respect to the timing signal T1. For this purpose, the shift outputs Q1 to Q6 of the shift register 109
changes as shown in the figure, or when the synchronization occurs for the fourth time, shift outputs Q2, Q4, and Q6 all become "1".
”, a non-standard detection signal is obtained from the NAND circuit 111 and the flip-flop circuit 113 is set.

As a result, the reset generator 103 directly uses the external vertical synchronization signal Vin as a reset signal for the vertical counter 102, and stable vertical synchronization can be obtained.

[Effects of the invention] As described above, according to this invention, the vertical period can be reduced to 1 by simply adding an extremely simple circuit element (approximately 20 gates).
It is possible to determine a non-standard mode even for signals alternately switched between 262H and 263H for each field and obtain appropriate vertical synchronization.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing chart shown to explain the operation of the circuit in FIG. 1, and FIG. 3 is a circuit diagram showing a conventional vertical synchronization circuit. FIG. 4 is a timing chart shown to explain the operation of the circuit shown in FIG. 3. 102... Vertical counter, 1o3... Reset generator, 104... Timing pulse generator, 1o5...
- Out-of-synchronization detector, 106... Inversion circuit, 107...
- Match continuity detector, 109...Shift register, 11
0°111...NAND circuit, 113...Flip-flop circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Scope of Claims] Clock generation means for generating a clock signal having a frequency fh (n is a predetermined natural number, fh is a horizontal frequency) times n times synchronized in phase with a horizontal synchronization signal of an input video signal; a frequency division counter that receives a counter reset signal as an input; a timing generation circuit that receives the output of the frequency division counter as an input and outputs a timing signal having a predetermined width at a standard vertical period; a coincidence continuity detection circuit that outputs a standard mode set signal only when a vertical synchronization signal is input and the external vertical synchronization signal is continuously obtained during the period in which the timing signal is generated; and the standard mode set. When the signal is output, the flip-flop circuit is reset by this signal and outputs a mode signal indicating the standard mode, and the flip-flop circuit is controlled by the mode signal output from this flip-flop circuit, and the mode signal indicates the standard mode. and a reset generator that outputs the reset signal at a predetermined value of the frequency division counter and, when indicating a non-standard mode, supplies the external vertical synchronization signal to the frequency division counter as the reset signal. and, as a means for setting the flip-flop circuit to output a mode signal indicating the non-standard mode, a shift register of several predetermined stages using the timing signal as a data input and the external vertical synchronization signal as a clock; A vertical synchronization circuit comprising means for detecting a continuous pattern twice or more in at least every other stage of the shift register.