JPH01233977A - Scan converter - Google Patents

Abstract

PURPOSE:To decrease the circuit scale by devising the converter such that a readout address does not overtake a write address from the head of a frame of an input video signal at each frame of the input video signal in case of a frame frequency X of the input video signal < a different frame frequency Y when the input video signal with the frame frequency X is outputted as an output video signal with the different frame frequency Y. CONSTITUTION:In case of X<Y, a latch signal generating means 30 generates a readout latch signal after a required time so that the readout address does not overtake the write address from the start of the said input video signal for each frame of the input video signal and an address setting means 31 uses a readout latch signal to set the readout start address in a write frame sequentially and sets the write frame head address sequentially for each write frame. In case of write, a write means 32 writes the input video signal from the frame head address to the frame memory 10 repeated for each frame of the input video signal and in case or readout, a readout means 33 reads out the frame from the readout start address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Frame frequency conversion is performed when an input video signal with a certain frame frequency X is output as an output video signal with a frame frequency Y having a different frame frequency.4. Regarding the Yang converter, the purpose is to reduce the memory capacity for writing input video signals and to reduce the circuit scale.When X<Y, A read latch signal is generated after the time necessary for the read address not to overtake the write address from the beginning of the frame of the input video signal, and
>Y, a latch signal generating means generates a write latch signal from the beginning of the frame of the output video signal before the time necessary to prevent the write address from overtaking the read address, and when X<Y, 1 ．． The read start address is set sequentially for each read frame using the above read wrap signal, and the adjustment frame start address is sequentially set for each write frame, and when X>Y, the above write latch signal is set. address setting means for sequentially setting a write start address for each read frame, and sequentially setting a read frame start address for each read frame;
When <Y, the input video signal is written to the frame memory from the write frame start address that is repeated for each frame of the input video signal, and when X>Y, the input video signal is written to the frame memory set above at the frame beginning timing of the input video signal. Write to the above frame memory from the start address, x>
In the case of Y, when there are two frame start timings of the input video signal at one write start address, the previous write is rewritten by the later write;
<When Y, read from the read start address set above at the frame start timing of the output video signal, and if there are two frame start timings of the output video signal at one read start address, read both times,
>Y, the configuration includes reading means for reading out each frame of the output video signal from the frame memory.

(Industrial Application Field) The present invention relates to a scan converter that performs frame frequency conversion when outputting an input video signal having a certain frame frequency as an output video signal having a different frame frequency.

For example, in the field of office automation (OA'), for example, a video signal displayed on a television receiver is input to an OA device, a personal computer, etc., and the image is displayed on the picture tube. In this case, the frame frequency of the input video signal for television broadcasting is, for example, 30Hz, and one of the 01tl! For example, the frame frequency of the output video signal of a device or a personal computer is 2.
0 Hz or 40)-1 z, and the frame frequencies on both the input side and output side are different. Therefore, in such a case, it is necessary to convert the frame frequency of the input video signal on the output side to extract the output video signal.

[Conventional technology]

FIG. 8 shows a block diagram of a conventional device, and FIG.
Figure 0 shows its operation timing chart. In Figure 8,
1.12 is 1 frame memory, each of which stores 1" frame (
Input video signals for 2 fields can be stored.

For example, a case where the frame frequency of the input video signal is lower than the frame frequency of the output video signal will be explained using FIGS. 8 and 9. For example, the frame frequency is 30H
The input video signal of z (FIG. 9(A)) is supplied to the input switch 2, and the 1 frame period detection circuit 3 detects
Switched every frame by the frame detection signal,
1 frame memory 1.12 is alternately supplied to 1 here.
Written in units of claims.

On the other hand, an output video signal whose frame frequency to be obtained from the output synchronization signal generator 4 is, for example, 40H2 (see FIG. 9(B)
) is output, and is supplied to the output side one frame period monitoring circuit 5 to output the output switching control signal (Fig. 9 (C
)) and is supplied to the output switch 6. in this case,
The 1 frame period monitoring circuit 5 on the output side is supplied with the 1 frame detection signal from the 1 frame period detection circuit 3, and here, the 1 frame period is detected depending on the relationship between the 1 frame period on the input side and the 1 frame period on the output side. L level signal for reading and selecting memory 1, 1 frame memory 2
This is an H level signal for reading and selecting. That is, at timing (3), one frame worth of input video signal A that has already been written in one frame memory 1 is read and selected, and at timing (4), one frame worth of input video signal A that has already been written in one frame memory 2 is selected. The input video signal SB is read out and selected. At timing (5), one frame worth of input video signal C written in one frame memory 1 is read out and selected, and at timing (6)
Since the input video signal C is still being written into the 1-frame memory 2, the input video signal C written in the 1-frame memory 1 is read out again and selected.

In this way, the input video signal is partially overlapped by one frame to obtain the output frame shown in FIG. 9(D).

On the other hand, when the frame frequency of the input video signal is higher than the frame frequency of the output video signal, FIGS.
This will be explained using Figure 0. In the same way as in the previous case, an input video signal with a frame frequency of 30 Hz (Fig. 10 (A)
) is switched every frame and stores 1 frame memory.
, 12 in units of 17 rooms.

The output synchronization signal generator 4 outputs a synchronization signal whose frame frequency to be obtained is, for example, 20 Hz (FIG. 10(B)), and the one frame period monitoring circuit 5 on the output side
The signal is converted into an output switching control signal (FIG. 10(C)) and supplied to the output switch 6. At timing (2), the input video signal A for one frame already written in the one frame memory 11 is read out and selected, and at timing (3)
), the input video signal B for one frame already written in the one frame memory 12 is read and selected, and at timing (4), the input video signal C for one frame already written in the one frame memory 11 is selected. Read and select. At timing (5), 1 frame memory 1
The input video signal E already written in the one frame memory 11 is read and selected without reading out the input video signal E for one frame already written in the one frame memory 11. In this way, the input video signal is partially subtracted for one frame to obtain the output frame shown in FIG. 10(D).

[Problem to be solved by the invention]

The above-mentioned conventional equipment requires two 1-frame memories each having a capacity of 1 frame.
Moreover, this has the problem of increasing the circuit scale.

SUMMARY OF THE INVENTION An object of the present invention is to provide a scan converter that can reduce the capacity of a memory for writing an input video signal and the circuit scale.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention. In the same figure, 10
is a frame memory, which has a storage capacity of one frame or more and less than two frames. Reference numeral 30 denotes a latch signal generating means, which is necessary to prevent the read address from overtaking the write address from the beginning of the frame of the input video signal when X (input video signal frame frequency) < Y (output video signal frame frequency). After time, a latch signal for reading is generated, and when X>Y, a latch signal for aging is generated from the beginning of the frame of the output video signal before the necessary time so that the write address does not overtake the read address. This is a launch signal generating means. Reference numeral 31 denotes an address setting means which sequentially sets a read start address using the read latch signal when X<Y, and sequentially sets an interpolation start address using the write wrap signal when X>Y. 32 is a writing means,
When <Y, the input video signal is written to the room memory 10 from the frame address that is repeated for each frame of the input video signal, and when X>Y, the write start address set above is written at the frame beginning timing of the input video signal. When X>Y, and there are two frame beginning timings of the input video signal at one interpolation start address, the previous interpolation is rewritten by the later interpolation. Reference numeral 32 denotes a readout means, which reads from the above-set readout start address at the frame start timing of the output video signal when X<Y, and when there are two frame start timings of the output video signal at one readout start address, reads 2. When X>Y, the above frame memory 1 is read for each frame of the output video signal.
Read from 0.

[For fishing]

When X<Y, the latch signal generating means 30 calculates, for each frame of the input video signal, the time (T1) required for the read address not to overtake the store address from the beginning of the frame of the input video signal. After that, a read latch signal is generated, and the address setting means 31 sequentially sets the read start address in the occupied frame using the read latch signal, and sequentially sets the write frame start address for each write frame. . When writing, the writing means 32 writes the input video signal into the frame memory 10 from the write frame start address that is repeated for each room of the input video signal, and when reading, the reading means 33 writes the input video signal to the frame memory 10 from the write frame start address that is repeated for each room of the input video signal. It is read from the read start address set above at the frame start timing, and when there are two frame start timings of the output video signal at one read start address, it is read out both times.

On the other hand, when X>Y, the latch signal generating means 30 generates a time (T2 ), a write latch signal is generated, and the address setting means 31 sequentially sets a write start address for each read frame using the write latch signal, and sets the read frame start address for each successive frame. Set sequentially.

When writing, the writing means 32 writes data into the frame memory 10 from the write start address set above at the frame start timing of the input video signal, so that one write start address has two frame start timings of the input video signal. In this case, a later write rewrites the earlier write. At the time of reading, each frame of the output video signal is read out from the frame memory 10 by the reading means 33.

In this way, when X<Y, a ++q period (margin time) is provided to prevent the read address from overtaking the write address, and the read start address is sequentially set and output when time T1 has elapsed after the end of writing. Since reading is started at the frame timing of the video signal, the input video signal can be written here without missing each frame, even if the volume capacity (2) of frame memory 0 is not set to two frames. On the other hand, in the case of X>Y, a time (margin time) is provided to prevent the write address from overtaking the read address, and the input video signal is Writing is performed at the frame timing of the output video signal, and reading is performed at the frame timing of the output video signal, so even if the storage capacity of frame memory 0 is not equal to 2 frames, the input video signal can be stored here and read out with thinning. be able to.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of the present invention.
A) is when the frame frequency X of the input video signal is lower than the frame frequency Y of the output video signal, and (B) is when the room frequency X of the input video signal is higher than the frame frequency Y of the output video signal. FIG.

Figure 2 (A> In the middle, 10 is a frame memory, which can store input ll!I! image signals of 1 frame or more and less than 2° room as described later.The storage capacity is 1 frame compared to the conventional example. It is 6 smaller than the storage capacity of two memories.Writing and reading can be performed at the same time if they are at different addresses.

In the present invention, as will be described later, the capacity will be explained as, for example, a capacity of 1°5 frames.

Reference numeral 11 denotes a synchronization separation circuit that separates a vertical periodic signal from an input video signal. 12 is a write address generation unit that generates a write address and writes data into frame 10.
Reference numeral 13 denotes a latch timing generating section, in which a margin time T1 (time period during which the read address does not overtake the write address) required to prevent the read address from colliding with the write address, which will be described later, is set. The latch control signal is generated after a time T from the generation of the vertical synchronization signal. Reference numeral 14 denotes an address latch control section that wraps the read address generated from the read address generation section 15 using a wrap control signal from the latch timing generation section 13.

Reference numeral 16 denotes an output synchronization signal generating section which outputs a synchronization signal for the output video signal of frame frequency Y to be obtained.

The synchronization separation circuit 11 and the latch timing generation section 13
In the figure, a latch signal generating means 30 is constructed. The address latch control section 14 is the start address setting means 31 in FIG. The write address generating section 12 is the reading means 32 in FIG. The read address generating section 15 and the output synchronizing signal generating section 16 constitute the reading means 33 in FIG.

First, the case of X<Y shown in FIG. 2(A) will be explained with reference to FIGS. 3 and 4. FIG. 3 is a diagram explaining the latch timing of the read start address, and FIG. 4 is a diagram showing the operation timing chart.

In FIG. 3, X indicates the write frequency and y indicates the read frequency in terms of the relationship between the frame address and time, so the difference in slope represents the difference in frequency.

T1 is the margin time required to prevent the read address and write address from colliding, and indicates that if the read address starts within the range surrounded by diagonal lines, the read address and write address will not collide. (If the read address starts outside the range surrounded by diagonal lines, the line with the y slope and the line with the x slope will intersect, and the read address and write address will collide.)

In FIG. 2(A), the input video signal is sent to the synchronous separation circuit 1.
1, the vertical synchronizing signal VS (Fig. 4 (A)) is separated,
The input video signal, which is converted into a write address control signal by the write address generation unit 12 and supplied to the frame memory 10, is output to the frame memory 10 according to the write address control signal.
written to.

In this case, as shown in FIG. 3, the peak frequency is X and is written according to addresses from frame address 1°0 to 1.5J.

The vertical synchronization signal from the synchronization separation circuit 11 is supplied to the latch timing generation section 13, and after a margin time T1, it is converted into a latch control signal and supplied to the address latch control section 14.

Here, the read address from the read address generator 15 is latched, and the input side vertical synchronization signal (FIG. 4(A))
Read start address r after margin time T1 from occurrence of
OFJ (Fig. 3 y.), rlF, + (Fig. 3 y1), [
0,5F-,l (Fig. 3, y., 5) is set.

Now, write frame ``1'' (X■ in Figure 3) from address ``OF'', then write frame [21 (X■ in Figure 3) from address ``1F'' as shown in Figure 3. Two X■ correspond to one frame), while reading frame "1" (y■) in Figure 13) is set to address I'O.
Suppose you are starting from FJ. The read start address is reset from the previous rOFJ to "1F" after a margin time T1 after the writing of frame "1" (Fig. 3 X) is completed (when writing of frame 1 "2" starts). (Figure 4(E)). In synchronization with the synchronization signal of the output video signal from the output synchronization signal generation unit 16 (FIG. 4(C)), every frame on the output side, that is, frame 1°2 from timing ■ starts from address "1F". read out (Fig. 3
■) (Two y■ shown in Fig. 3 constitute one frame) Then, from timing @, the same frame "2" is read from the same address "1F" (Fig. 3 y■') (
The two y' shown in FIG. 3 constitute one frame) (FIG. 4 (F)).

In the same way, frame [2,1 fortune-telling (Fig. 3
The read start address is reset from the previous "1F" to r0.5FJ in the margin time T1m after the end of the readout (FIG. 4(E)).

Frame “3” written from address ro, 5FJ
” (X■ in Figure 3) is from timing O to address ro,
It is read from sFJ (Fig. 3 y■), and in the same way,
Writing and reading of frames [4-1 and below are performed.

In this way, each frame r1, 1r2i, . . . of the input video signal shown in FIG. 4(B) is extracted as an output video signal by partially overlapping the frames as shown in FIG. 4(F). . In this case, a time (margin time) T1 is provided to prevent the read address from overtaking the old address, and the read start address is set to
F, 1F.

Since the setting is repeated in the order of 0.5F and reading is started at the frame timing of the output video signal, even if the storage capacity of the frame memory 10 is not set to 2 frames (for example, 1.5 frames in the embodiment) ), the input video signal can be written here without missing each frame.

Next, the case of X>Y shown in FIG. 2(B) will be explained. In FIG. 2(B), 10 is a frame memory, and 11 is a synchronization separation circuit, which are the same as those shown in FIG. 2(A). Reference numeral 17 denotes an output synchronization signal generating section which outputs a synchronization signal for the output video signal of the obtained Pegi frame frequency Y. Reference numeral 18 is a latch timing generation unit, which will be described later, provides a margin time required to prevent the read address from colliding with the write address (contrary to the case where X<Y, the write address actually overlaps the read address Time to avoid overtaking) T
2 is set, and the time T' from the generation of the vertical synchronization signal
A latch control signal is generated later (time T2 before the generation of the vertical synchronization signal). Reference numeral 19 denotes an address latch control unit, which latches the latch control from the latch timing generation unit 18 (in No. m, the apology address generated from the write address generation unit 20). Reference numeral 21 denotes a read address generation unit, which generates a read address. data is read from frame 10.

Output synchronization signal generation section 17, latch timing generation section 1
8 constitutes latch signal generating means 30 in FIG. The address latch control section 19 is the start address setting means 31 in FIG. The write-in address generating section 20 is the reading means 32 in FIG. Output synchronization signal generator 1
7. In the read address generation section 21, the read means 3 in FIG.
3 are made up.

Here, in the case of X>Y shown in FIG. 2(B), the fifth
This will be explained with reference to FIG. FIG. 5 is a diagram explaining the latch timing of the read start address, and FIG. 6 is an operation timing chart. In FIG. 5, X indicates the write frequency and y indicates the read frequency in relation to the frame address and time, and the difference in slope represents the difference in frequency. T2 is the margin time required to prevent the read address from colliding with the output address.
If the write address starts within the range surrounded by diagonal lines, it means that the read address and write address will not collide (if the write address starts outside the range surrounded by diagonal lines, the slope of y can be changed to 6 lines. (The line with the slope of X intersects, and the read address and write address collide).

In FIG. 2(B), the input video signal is sent to the synchronous separation circuit 1.
1, the vertical synchronizing signal VS (Fig. 6 (Δ)) is separated,
The input video signal, which is converted into a write address control signal by the write address generation unit 20 and supplied to the frame memory 10, is output to frame memory 0 according to the write address control signal.
Occupied by.

Here, the vertical synchronization signal (FIG. 6(C)) from the output synchronization signal generation section 17 is supplied to the latch timing generation section 18 and is made into a latch control signal after time T' (before margin time T2), Supplied to one address lap control section. Here, the write address from the write address generation section 20 is latched, and the write start address l' is reached after a time T' (with a margin of 84 T2) from the generation of the output side vertical synchronizing signal (FIG. 6(C)). 0FJ (x in Figure 5), l'1FJ (X in Figure 5), and f 0.5FJ (X0.5 in Figure 5) are set.

Now, write frame [1-1 (X■ in Figure 5) from address ro, 5FJ, then write frame ``2'' (X■ in Figure 5) from address ``OF'',
Next, frame 1-3'' is written (Fig. 5
A case will be described in which reading of room "1" (y@) in FIG. 5 is performed from address rOFJ, and then reading of room "1" (y2) in FIG. 5 is performed from address ro, 5FJ. Before the margin time T2 when the readout of frame l-OJ (Fig.
The setting is changed from "5F" to "1OF" (Figure 6 ([))
.

In synchronization with the input video signal synchronization signal (FIG. 6(A)) from the read address generation unit 20, every frame on the input side,
In other words, from the timing frame "21 is address l"
0FJ (FIG. 5X), and then from timing O, frame 1'3'' is intercepted from the same address rOFJ (FIG. 5X) (FIG. 6(F)). in this case,
Since the start address "OF" is the same as frame [2, 1], frames 1-3 will be rewritten from this address 10F.

Similarly, the write start address is reset from 1OF1 to 11F (6th
Figure (E)). From timing ■, room "4-1" is written from address rlF, l (Fig. 5 Frame [3-1] is read out, and substantially frame 12'' is thinned out, and subsequent reading is performed in the same manner (FIG. 6(G)).

In this way, each rule of the input video signal shown in FIG.
The frames r1.1r2J, . . . are extracted as output video signals by partially thinning out the frames as shown in FIG. 6(G).

In this case, a time (margin time) T2 is provided to prevent the read address from overtaking the read address, and the read start address is set to OF, 1F at the time T2 before the start of reading.
, 0.5F, reading is performed at the frame timing of the input video signal, and reading is performed at the room timing of the output video signal, so the storage capacity of the frame memory 10 is reduced to 2 frames. Don't make it a minute b
An input video signal (for example, for 1.5 frames in the embodiment) can be written here and read out after being thinned out.

Here, the frame frequency of the input video signal is X, the frame frequency of the output video signal is Y, each writing and reading time is on the output side... 1 field time 1/2X blank time (vertical retrace period) tBi Read side...1 field time 1/2Y blank time (vertical retrace period) tB.

In addition, the method of calculating the time will be explained assuming that the memory address is the address for one field △ the maximum value Z of the memory address (1.5F in FIGS. 3 and 5).

First, when X<Y (Figures 3 and 4), ■ When T1 is the minimum, T , -2・1 (1+(1-t)) mv
2X 2Y 2Y B.

Then, the time 1H until the write address reaches the maximum when d reaches the maximum is as follows, where α is the integer part of Z/A.

Also, from the input side (writing side) one field time (widening time including blank time) and memory address slope (memory address advancement speed), address old history for (Z-α・A) is calculated. t. If it is 1, then from the input side 1゛no yield occupation time (the digging time other than the blank time tBi) and the slope of the memory address (the speed at which the memory address advances), (Z-α・A)
The address interval for minutes is t. 2, it becomes .

Therefore, the width β of the writing time due to the slope is β − Q'2'''Bi ''a 1 when the memory address is the maximum,
Therefore, the maximum time of T1 is as follows.

Therefore, the time T1 when the frame frequency of the input video signal is smaller than the frame frequency of the output video signal is as follows. That is, if the read address is started at a timing within the shaded range in Figure 3, the write address and read address will not collide (the read address will not overtake the write address). ).

Next, when X>Y (FIGS. 5 and 6), (1) T2 is the maximum, and (2) T2 is the minimum.

Also, the minimum memory capacity of the frame memory 10 is M
Therefore, the time T2 when the frame frequency of the input video signal is greater than the frame frequency of the output video signal is as follows. In other words, if the old incoming address is started at the timing within the shaded range in FIG. 5, there will be no collision between the incoming and outgoing addresses (X
<Contrary to the 11th case of Y, there is virtually no case where the internal address overtakes the read address).

Next, a method for calculating the minimum required capacity of the frame memory 10 will be explained. In the case of X<Y, the margin time T is set so that the read address does not overtake the fill address, but if the blank time is not included until 1, as shown in Fig. 7, and the frame error occurs. The minimum memory capacity of 10 is M
Then, M=1F・〈U+2−[). From the above two equations, M=1F・(Yu''2(YuYu)) Y XY −1F・(−2−Yu) XY. On the other hand, in the case of X>Y, the margin time T is set so that the write address does not overtake the read address, but if the blank time is not taken into consideration, from Fig. 7, T = knee 1 YX, and , the minimum memory capacity of the frame memory 10 is M
Then, it becomes M-1F・(U+2゛[). From the above two formulas, M-1F・('+2 (''-1> )X
YX = 1F・<2−−3−>X.

In this way, the minimum required capacity M of the frame memory 10 is
is determined by the input video signal frame frequency X and the output video signal frame frequency Y. 1 and Figures 3 and 4
The read start address in the case of X<Y shown in the figure, the fifth
In the case of X>Y shown in the figure and Fig. 6, the reading start address is a repetition of OF, IF, and 0.5F for each frame, but this is when M is set to 1.5F. , generally changes sequentially as OF, IF, <2-M)F.

〔Effect of the invention〕

As explained above, according to the present invention, the read start address is controlled by time when X<Y, and the write start address is controlled by time when X>Y, so that the read address and the write address do not collide. Therefore, two frames are not needed for frame memory storage.
Compared to the conventional example in which two 1-frame memories are used to write to the U for each frame, a smaller memory capacity is required, thereby making it possible to reduce the circuit scale.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is a block diagram of an embodiment of the present invention, and Figure 3 is a block diagram of an embodiment of the present invention.
A diagram explaining the latch timing of the read start address in the case of <Y, Figure 4 is an operation timing chart in the case of X<Y, and Figure 5 explains the wrap timing of the interpolation start address in the case of X>Y. Figure 6 is an operation timing chart in the case of X>Y, Figure 7 is a diagram explaining the method for determining memory capacity, Figure 8 is a block diagram of a conventional example, Figures 9 and 10 are conventional This is an example timing chart. In the figure, 10 is a frame memory, 11 is a synchronization separation circuit, 12.20 is an input/output address generation section, 13.18 is a wrap timing generation section, 14.19 is an address latch control section, and 15.21 is a read address generation section. 16 and 17 are output synchronizing signal generating sections, 30 is a wrap signal generating means, 31 is a start address setting means, 32 is a read-out means, and 33 is a reading means. °(shi′

Claims (1)

[Claims] In a scan converter that performs frame frequency conversion when outputting an input video signal with a certain frame frequency X as an output video signal with a different frame frequency Y, the storage capacity is for one frame or more and less than two frames. a frame memory (10) with )later,
Generate a latch signal for reading, and when X>Y, for each frame of the output video signal, the time required for the write address to not overtake the read address from the beginning of the frame of the output video signal (T_2) a latch signal generating means (30) that generates a write latch signal, and when X<Y, sequentially sets a read start address for each write frame using the read latch signal, and
The write frame start address is set sequentially for each write frame, and when X>Y, the write start address is sequentially set for each read frame using the write latch signal, and the read frame start address is set for each read frame sequentially. address setting means (31) for sequentially setting start addresses;
When X<Y, the frame memory (
10), and when X>Y, write the input video signal to the frame memory (10) from the write start address set above at the frame beginning timing of the input video signal.
), when X > Y, if there are two frame start timings of the input video signal at one write start address, the previous write will be rewritten by the later write.
The writing means (32) reads from the read start address set above at the frame start timing of the output video signal when X<Y, and when there are two frame start timings of the output video signal at one read start address. Read both times,
A scan converter comprising a reading means (33) for reading each frame of an output video signal from the frame memory (10) when X>Y.