JP2017158092A - Semiconductor device, video system and video signal output method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the occurrence of a state in which a video image is not displayed for a long period of time, even if video data are not input.SOLUTION: A semiconductor device includes: a video data input terminal to which first video data supplied from the outside are input; a discrimination part for discriminating whether the first video data are input; a video data holding part for holding second video data; and an output part which, when the discrimination part has discriminated that the first video data are input, outputs a video signal corresponding to the first video data and when the discrimination part has discriminated that the first video data are not input, outputs an output video signal corresponding to the second video data.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, a video system, and a video signal output method.

  The following techniques are known as techniques related to video signal output control. For example, Patent Document 1 discloses a main CPU, camera input control means for receiving image data output by an imaging device during initialization processing of the main CPU, and output of image data during display of the main CPU to the display. And a display control means.

  In Patent Literature 2, after analyzing the video data and the pixel clock input from the video / audio signal processing unit and determining whether or not the signal is a regular signal, in the case of an irregularity, dummy video data generated in an artificial manner and It describes that TMDS (Transition Minimized Differential Signaling) is generated and output based on a dummy pixel clock.

JP 2012-28868 A JP 2010-147542 A

  A semiconductor device that functions as a video encoder that converts digital video data supplied from the outside into an analog video signal and outputs the analog video signal is known. The video signal output from the video encoder is supplied to a display device such as a liquid crystal display, and a video based on the video signal is displayed on the display. Digital video data supplied to the video encoder is output from, for example, a SoC (System-on-a-chip) functioning as a video decoder.

  In a video system configured by combining a SoC functioning as a video decoder and a semiconductor device functioning as a video encoder, the following problems are assumed. That is, since the integrated circuit constituting the SoC has a relatively large circuit scale, the activation time from power-on to completion of activation is often longer than that of the semiconductor device constituting the video encoder. Therefore, video data is not input to the semiconductor device that constitutes the video encoder until the SoC is completely activated after power-on, and therefore the video encoder cannot output a video signal. It cannot be displayed. Thus, if a period in which no video is displayed on the display device immediately after the power is turned on, the user may mistakenly assume that the video system is out of order. In particular, an in-vehicle video system that displays video captured by an in-vehicle camera is safety-related, and it is not preferable that a period in which no video is displayed on the display device occurs over a long period (for example, several seconds). Conceivable.

  The present invention has been made in view of the above points, and an object of the present invention is to avoid a situation in which no video is displayed for a long period of time even when video data is not input.

  A semiconductor device according to the present invention includes a video data input terminal to which first video data supplied from the outside is input, a determination unit that determines whether or not the first video data is input, and second video data And a video data holding unit for holding the first video data when the determination unit determines that the first video data is input, and the determination unit outputs the video signal according to the first video data. And an output unit that outputs an output video signal corresponding to the second video data when it is determined that there is no input of the first video data.

  A video system according to the present invention includes the above-described semiconductor device and a video data output device that outputs the first video data.

  The video signal output method according to the present invention determines whether or not first video data is input from the outside of the semiconductor device, and inputs the first video data input when it is determined that the first video data is input. A video signal corresponding to the second video data held inside the semiconductor device when the video signal corresponding to the video data is output to the outside of the semiconductor device and it is determined that the first video data is not input Is output to the outside of the semiconductor device.

  According to the present invention, it is possible to avoid a situation in which no video is displayed for a long time even when video data is not input.

It is a block diagram which shows the structure of the video system which concerns on embodiment of this invention. It is a block diagram which shows the structure of the video encoder which concerns on embodiment of this invention. It is a time chart which shows an example of operation | movement of the 2nd selector which concerns on embodiment of this invention. It is a block diagram which shows the partial structure of the video encoder which concerns on embodiment of this invention. It is a time chart which shows an example of operation | movement of the counter and 3rd selector which concern on embodiment of this invention. It is a time chart which shows an example of operation | movement of the counter and 3rd selector which concern on embodiment of this invention.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or equivalent components and parts are denoted by the same reference numerals.

[First embodiment]
FIG. 1 is a block diagram showing a configuration of a video system 100 according to an embodiment of the present invention. The video system 100 includes a video encoder 10, a video decoder 40, a crystal oscillation circuit 50, a video camera 60, and a display 70.

  The video camera 60 is an imaging device that captures images. An analog video signal corresponding to the video imaged by the video camera 60 is supplied to the video decoder 40.

  The video decoder 40 converts the analog video signal supplied from the video camera 60 into digital data. Also, the video decoder 40 recognizes the video shot by the video camera 60, generates a composite video in which characters, figures, symbols, etc. are added to the video, and supplies this to the video encoder 10 as digital video data Dv. To do. The video decoder 40 supplies the video encoder 10 with the video data Dv and the serial communication signals SDA and SCL according to the I2C method including the pixel clock signal Cp and a command for the video encoder 10. The video decoder 40 is configured as, for example, a SoC in which a series of required functions are integrated on a semiconductor chip.

  The crystal oscillation circuit 50 includes a crystal resonator, generates a crystal clock signal Cq, and supplies this to the video encoder 10. The frequencies of the crystal clock signal Cq and the pixel clock signal Cp are substantially the same, for example, 27 MHz.

  The video encoder 10 is configured as a semiconductor device separate from the video decoder 40. The video encoder 10 has input terminals 31, 32, and 33 to which the video data Dv output from the video decoder 40, the serial communication signals SDA and SCL, and the pixel clock signal Cp are input, respectively. The video encoder 10 also has an input terminal 34 to which the crystal clock signal Cq output from the crystal oscillation circuit 50 is input.

Video encoder 10, the composite video signal CVBS generated (Composite Video, Blanking, and Sync ) to the output terminal 35 this in synchronism with the pixel clock signal Cp is an analog video signal corresponding to the digital video data D _V Output from. The composite video signal CVBS output from the output terminal 35 is supplied to the display 70. Note that the video encoder 10, the video decoder 40, and the crystal oscillation circuit 50 may be mounted on the same wiring board.

  The display 70 is a display device such as a liquid crystal display, and displays a video corresponding to the composite video signal CVBS output from the video encoder 10 on a display screen.

  FIG. 2 is a block diagram showing a detailed configuration of the video encoder 10. The video encoder 10 includes an internal video memory 11, a determination unit 12, a first selector 13, a second selector 14, an interface unit 15, a PLL (phase locked loop) circuit 16, a frequency divider circuit 17, and an encode block 20.

  The internal video memory 11 is a memory that holds internal video data as a fixed value in, for example, RGB or YUV format. The internal video data may be video data indicating a monochrome still image such as a blue image or a black image, or may be video data indicating a still image including characters, figures, symbols, and the like.

  The first selector 13 selects either the internal video data stored in the internal video memory 11 or the video data Dv output from the video decoder 40 and supplies the selected video data to the encode block 20. The first selector 13 selects video data based on the determination signal Sd output from the determination unit 12 and the selection command signal Sc output from the interface unit 15.

  The encoding block 20 is a circuit block that converts the digital video data selected by the first selector 13 into an analog composite video signal CVBS using a known technique and outputs it. The encoding block 20 includes a synchronization generation unit 22, a VBI (Vertical Blanking Interval) generation unit 23, a luminance / color difference generation unit 24, a color subcarrier generation unit 25, and a CVBS generation unit 26.

  The synchronization generation unit 22 is a circuit block that generates synchronization timing necessary for displaying an image on the display 70. The VBI generation unit 23 is a circuit block that performs processing for inserting data other than video data (for example, data for copy guard) in the VBI, that is, the vertical blanking interval. The luminance / color difference generation unit 24 is a circuit block that generates a signal indicating the luminance and color difference of the video indicated by the video data supplied via the first selector 13. The color subcarrier generation unit 25 is a circuit block that generates a subcarrier for superimposing a color signal on a luminance signal. The CVBS generation unit 26 includes a digital / analog converter, and integrates signals output from the synchronization generation unit 22, the VBI generation unit 23, the luminance / color difference generation unit 24, and the color subcarrier generation unit 25, respectively. This is a circuit block that performs digital-analog conversion and outputs this as a composite video signal CVBS. The composite video signal CVBS is output from the output terminal 35 and supplied to the display 70. Each circuit block constituting the encode block 20 operates in synchronization with the internal clock signals CLK1 to CLK3 supplied from the frequency divider circuit 17.

The determination unit 12 determines whether the video data Dv output from the video decoder 40 is input to the video encoder 10. For example, the determination unit 12 may determine whether or not the video data Dv is input by determining whether or not at least one of a horizontal synchronization signal and a vertical synchronization signal included in the video data Dv is present. The determination unit 12 generates a determination signal Sd indicating the determination result and supplies it to the first selector 13. The determination unit 12 operates in synchronization with the crystal clock signal Cq output from the crystal oscillation circuit 50. The determination unit 12 is initialized, for example, immediately after power-on or after a system reset and enters an initial state. Determination unit 12, in the initial state, regardless of whether the input video data D _V, and outputs a determination signal Sd which indicates that there is an input of the video data D _V.

  The interface unit 15 supplies the first selector 13 with a selection command signal Sc based on the I2C serial communication signals SDA and SCL output from the video decoder 40. That is, the selection of video data in the first selector 13 is performed based on the determination result in the determination unit 12 and a command from the video decoder 40 supplied via the interface unit 15. The interface unit 15 operates in synchronization with the clock signal selected by the second selector 14 among the pixel clock signal Cp output from the video decoder 40 and the crystal clock signal Cq output from the crystal oscillation circuit 50.

The second selector 14 selects one of the pixel clock signal Cp output from the video decoder 40 and the crystal clock signal Cq output from the crystal oscillation circuit 50, and sends the selected clock signal to the PLL circuit 16. Supply. The second selector 14, the determination signal Sd selects the crystal clock signal Cq is to indicate that there is no input of the video data D _V, to indicate that the determination signal Sd is input video data D _V is the pixel The clock signal Cp is selected.

  The PLL circuit 16 generates a reference clock signal CLK0 that is synchronized with the clock signal selected by the second selector 14 out of the pixel clock signal Cp and the crystal clock signal Cq, and supplies this to the frequency dividing circuit 17.

  The frequency divider circuit 17 generates a plurality of internal clock signals CLK1 to CLK3 having different frequencies from each other by dividing the reference clock signal CLK0, and supplies this to the encode block 20. The internal clock signals CLK1 to CLK3 are appropriately supplied to each circuit block constituting the encode block 20. In this embodiment, the case where three types of internal clock signals are generated in the frequency divider circuit 17 is illustrated, but the present invention is not limited to this, and an internal clock signal having a frequency required in the encode block 20 is illustrated. Is generated in the frequency divider circuit 17.

  Hereinafter, the operation of the video system 100 will be described in time series.

When the video system 100 is powered on, the video encoder 10 and the crystal oscillation circuit 50 are activated. The determination unit 12 starts operating when the crystal clock signal Cq is input. When the power is turned on, the video encoder 10 is initialized, and the values of all the registers constituting the video encoder 10 are reset to initial values. In the initial state, the determination signal Sd judging unit 12 outputs, with or without the input of the video data D _V, the state shown that there is an input of the video data D _V. Accordingly, the first selector 13, of the video data D _V and internal image data, to select the video data D _V. The second selector 14 selects the pixel clock signal Cp from the pixel clock signal Cp and the crystal clock signal Cq.

The video decoder 40 has a longer startup time than the video encoder 10 and cannot perform its function for a while (for example, several seconds) after the power is turned on. Thus, for some time after the power is turned on, the video data D _V and pixel clock signal Cp is the video encoder 10 is not input. Therefore, since the pixel clock signal Cp is not output from the second selector 14, the internal clock signals CLK1 to CLK3 are not generated in the frequency dividing circuit 17, and the encode block 20 maintains the stopped state immediately after the power is turned on.

Thereafter, the determination unit 12 outputs a determination signal Sd which indicates that there is no input video data D _V. The second selector 14 selects the crystal clock signal Cq based on the determination signal Sd and supplies it to the PLL circuit 16. The PLL circuit 16 generates a reference clock signal CLK0 synchronized with the crystal clock signal Cq, and supplies this to the frequency divider circuit 17. The frequency dividing circuit 17 generates internal clock signals CLK1 to CLK3 synchronized with the crystal clock signal Cq, and supplies them to the encode block 20. The encode block 20 starts the operation synchronized with the crystal clock signal Cq when the internal clock signals CLK1 to CLK3 are supplied.

First selector 13 selects the internal image data stored in the internal image memory 11 based on the determination signal Sd indicates that there is no input of the video data D _V, and supplies it to the encoding block 20. The encoding block 20 generates a composite video signal CVBS based on the internal video data and supplies it to the display 70. As a result, a video based on the internal video data (for example, a monochrome still image such as a blue image or a black image) is displayed on the display screen of the display 70.

Thereafter, the video decoder 40 has been up and running, ready to perform its function, the video data D _V and pixel clock signal Cp is inputted to the video encoder 10, the determination unit 12, the input video data D _V The determination signal Sd indicating that there is is output.

The second selector 14 selects the pixel clock signal Cp based on the determination signal Sd indicating that the video data _DV is input, and supplies this to the PLL circuit 16. The PLL circuit 16 generates a reference clock signal CLK0 that is synchronized with the pixel clock signal Cp and supplies it to the frequency divider circuit 17. The frequency dividing circuit 17 generates internal clock signals CLK1 to CLK3 synchronized with the pixel clock signal Cp and supplies them to the encoding block 20. The encode block 20 is operated in synchronization with the pixel clock signal Cp by being supplied with the internal clock signals CLK1 to CLK3.

First selector 13 selects the video data D _V supplied from the video decoder 40 based on the determination signal Sd indicates that there is an input of the video data D _V, and supplies it to the encoding block 20. Encoding block 20 generates a composite video signal CVBS on the basis of the video data _{D V,} and supplies this to the display 70. Thus the display screen of the display 70 is displayed video based on the video data D _V outputted from the video decoder 40.

Even if the video data D _V is input to the video encoder 10, by giving a command to the video encoder 10 by serial communication signals SDA and SCL, also possible to display an image based on the internal video data to the display 70 It is.

As described above, according to the video encoder 10 and video system 100 comprising the same according to the present embodiment, even in a period that is not output video data D _V and pixel clock signal Cp from the video decoder 40, the video encoder 10 is held The video based on the internal video data to be displayed can be autonomously displayed on the display 70. That is, even when video data is not input to the video encoder 10, it is possible to avoid a state where no video is displayed on the display 70 for a long period of time (for example, several seconds). Thereby, it can prevent that a user misidentifies the failure of the video system 100. FIG.

  In the present embodiment, the case where the internal video data is held as a fixed value in the internal video memory 11 is exemplified. However, by assigning a data area equivalent to the internal video memory 11 to the internal register space, any luminance / color can be obtained. The internal video data at the level may be set from the outside of the video encoder 10.

In the present embodiment, the system configuration including the crystal oscillation circuit 50 is illustrated, but the video encoder 10 can appropriately operate even in a system that does not include the crystal oscillation circuit. In a system having no crystal oscillation circuit, the potential of the input terminal 34 to which the crystal clock signal Cq is input is fixed at, for example, the ground level. Accordingly, the determination unit 12, since the operation is stopped, the determination signal Sd is fixed initial state, i.e. the state indicating that there is an input of the video data D _V. Accordingly, the first selector 13 as long as the internal image data is not selected by the selection command signal Sc, to select the video data D _V. On the other hand, the second selector 14 always selects the pixel clock signal Cp. Thus, the display 70, as long as the internal image data is not selected by the selection command signal Sc, is displayed video based on the video data D _V.

  In the present embodiment, the crystal clock signal Cq output from the crystal oscillation circuit 50 provided outside the video encoder 10 is used as a clock signal different from the pixel clock signal Cp. Instead of this, a clock signal output from an oscillation circuit such as a CR oscillation circuit formed in the video encoder 10 may be used.

[Second Embodiment]
Before describing the second embodiment of the present invention, the operation of the second selector 14 according to the first embodiment will be described. FIG. 3 is a time chart illustrating an example of the operation of the second selector 14. The pixel clock signal Cp, the crystal clock signal Cq, the determination signal Sd, and the output of the second selector 14 are input to the second selector 14. Signals are shown.

  As shown in FIG. 3, for example, the second selector 14 selects the pixel clock signal Cp when the determination signal Sd is at a high level, and selects the crystal clock signal Cq when the determination signal Sd is at a low level. Here, since the pixel clock signal Cp and the crystal clock signal Cq are asynchronous, depending on the level inversion timing of the determination signal Sd, a beard-like pulse may be generated as indicated by a broken line in FIG. There is. When such a beard-like pulse is input to the interface unit 15, a timing error may occur in the interface unit 15, which may cause a malfunction.

  FIG. 4 is a block diagram showing a partial configuration of a video encoder 10A according to the second embodiment of the present invention. FIG. 4 shows only the configuration of the interface unit 15 and its input stage. Other components (internal video memory 11, determination unit 12, first selector 13, second selector 14, PLL) The circuit, frequency divider 17 and encode block 20) are not shown.

  The video encoder 10A according to the second embodiment further includes a counter 18 and a third selector 19 with respect to the configuration of the video encoder 10 according to the first embodiment.

  The counter 18 counts the number of pulses of the crystal clock signal Cq, outputs a low level signal before the count value reaches the predetermined value A, and outputs a high level signal when the count value reaches the predetermined value A. Output. The output signal of the counter 18 is supplied to the third selector 19.

  The third selector 19 selects one of the pixel clock signal Cp and the crystal clock signal Cq according to the output signal of the counter 18. The third selector 19 selects the pixel clock signal Cp when the output signal of the counter 18 is at a low level (that is, when the count value of the counter does not reach the predetermined value A), and the output signal of the counter 18 Is at the high level (that is, when the count value of the counter reaches the predetermined value A), the crystal clock signal Cq is selected. That is, the third selector 19 is configured to select the pixel clock signal Cp in the initial state. Of the pixel clock signal Cp and the crystal clock signal Cq, the clock signal selected by the third selector 19 is supplied to the interface unit 15. The interface unit 15 operates in synchronization with the clock signal selected by the third selector 19.

  FIG. 5A is a time chart showing an example of the operations of the counter 18 and the third selector 19 immediately after the power is turned on.

  When the video system 100 is powered on, the crystal oscillation circuit 50 is activated, and the crystal clock signal Cq is input to the video encoder 10A. On the other hand, the pixel clock signal Cp is not input to the video encoder 10A until the video decoder 40 is completely activated after the power is turned on.

  The counter 18 starts counting the number of pulses of the crystal clock signal Cq. Until the count value of the number of pulses of the crystal clock signal Cq reaches the predetermined value A, the output signal of the counter 18 maintains the low level. Thereby, the third selector 19 selects the pixel clock signal Cp. However, as described above, since the pixel clock signal Cp is not input to the video encoder 10A, the pixel clock signal Cp is not output from the third selector 19, and the interface unit 15 does not operate.

  Thereafter, when the count value of the counter 18 reaches the predetermined value A, the counter 18 outputs a high level output signal. As a result, the third selector 19 selects the crystal clock signal Cq and supplies it to the interface unit 15. The interface unit 15 operates in synchronization with the crystal clock signal Cq. Since the counter 18 holds the predetermined value A when the count value reaches the predetermined value A, the output signal of the counter 18 maintains a high level. Thereby, the state in which the crystal clock signal Cq is supplied to the interface unit 15 is maintained.

  As described above, according to the video encoder 10A according to the second embodiment of the present invention, after the count value of the counter 18 reaches the predetermined value A, the clock signal supplied to the interface unit 15 is switched. Since it does not occur, the risk that a beard-like pulse is input to the interface unit 15 can be reduced. Therefore, the occurrence of a timing error in the interface unit 15 can be prevented.

  FIG. 5B is a time chart showing an example of operations of the counter 18 and the third selector 19 in a system that does not have a crystal oscillation circuit.

  In a system without a crystal oscillation circuit, the count value of the counter 18 is always 0, so that the output signal of the counter 18 is always at a low level. Accordingly, the third selector 19 maintains the selection of the pixel clock signal Cp selected in the initial state, and the pixel clock signal Cp is always supplied to the interface unit 15.

  Thus, according to the configuration of the video encoder 10A according to the second embodiment, it is possible to perform an appropriate operation even in a system that does not have a crystal oscillation circuit. Therefore, since it is not necessary to change the circuit configuration depending on the presence or absence of the crystal oscillation circuit, fuse trimming and mask change for selecting the circuit configuration in the manufacturing process are not required.

The video encoders 10 and 10A are examples of the semiconductor device in the present invention. The video system 100 is an example of a video system in the present invention. The video data _DV is an example of first video data in the present invention. The internal video data is an example of the second video data in the present invention. The input terminal 31 is an example of a video data input terminal in the present invention. The input terminal 33 is an example of a first clock input terminal in the present invention. The input terminal 34 is an example of a second clock input terminal in the present invention. The determination unit 12 is an example of a determination unit in the present invention. The first selector 13 and the encode block 20 are an example of an output unit in the present invention. The encoding block 20 is an example of a generation unit in the present invention. The first selector 13 is an example of a first selection unit in the present invention. The second selector 14 is an example of a second selection unit in the present invention. The third selector 19 is an example of a third selection unit in the present invention. The interface unit 15 is an example of an interface unit in the present invention. The counter 18 is an example of a counter in the present invention. The video decoder 40 is an example of a video data output device in the present invention. The video camera 60 is an example of an imaging device in the present invention. The display 70 is an example of a display device in the present invention.

10, 10A Video encoder 11 Internal video memory 12 Judgment unit 13 First selector 14 Second selector 15 Interface unit 16 PLL circuit 17 Frequency divider 18 Counter 19 Third selector 20 Encoding blocks 31, 32, 33, 34 Input terminal 40 video decoder 60 video camera 70 display 100 video system _{D V} image data Sd selection signal Cp pixel clock signal Cq crystal clock signal

Claims (9)

A video data input terminal to which first video data supplied from the outside is input;
A determination unit for determining whether or not the first video data is input;
A video data holding unit for holding second video data;
When the determination unit determines that the first video data is input, the determination unit outputs a video signal corresponding to the input first video data, and the determination unit receives the first video data. An output unit that outputs a video signal corresponding to the second video data when it is determined that there is not,
A semiconductor device including: The determination unit outputs a determination signal indicating a result of determining whether or not the first video data is input;
The output unit is
When the determination signal indicates that the first video data is input, the first video data input is selected, and when the determination signal indicates that the first video data is not input A first selection unit for selecting the second video data;
A generating unit that generates a video signal corresponding to the video data selected by the first selection unit among the first video data and the second video data;
The semiconductor device according to claim 1. The first video data and the second video data are digital data,
The semiconductor device according to claim 2, wherein the generation unit generates an analog video signal as the video signal. A first clock input terminal to which a first clock signal associated with the first video data is input;
A second clock input terminal to which a second clock signal is input;
Further including
4. The semiconductor according to claim 2, wherein the determination unit operates in synchronization with the second clock signal, and outputs a determination signal indicating that the first video data is input in an initial state. apparatus. The first clock signal is selected when the determination signal indicates that the first video data is input, and the first clock signal is selected when the determination signal indicates that the first video data is not input. A second selector for selecting two clock signals;
The semiconductor device according to claim 4, wherein the generation unit operates in synchronization with a clock signal selected by the second selection unit among the first clock signal and the second clock signal. A counter for counting the number of pulses of the second clock signal;
A third selection unit that selects the first clock signal in an initial state and selects the second clock signal when the count value of the counter reaches a predetermined value;
The video data selection command in the first selection unit supplied from the outside is synchronized with the clock signal selected by the third selection unit among the first clock signal and the second clock signal. The semiconductor device according to claim 5, further comprising an interface unit that supplies the first selection unit. A semiconductor device according to any one of claims 1 to 6,
A video data output device for outputting the first video data;
Including video system. An imaging device for imaging video;
A display device for displaying video according to the video signal;
Further including
The video system according to claim 7, wherein the video data output device outputs digital data including video captured by the imaging device as the first video data. Determining whether or not the first video data is input from the outside of the semiconductor device;
When it is determined that there is input of the first video data, a video signal corresponding to the input first video data is output to the outside of the semiconductor device,
A video signal output method for outputting a video signal corresponding to second video data held inside the semiconductor device to the outside of the semiconductor device when it is determined that there is no input of the first video data.

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