JP2017156684A - Video processing device and video display method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video display device in which a video signal is divided and processed with a simplified structure.SOLUTION: A video processing device includes: a division unit to which two or more video signals are input and which outputs the two video signals or two divisional video signals obtained by dividing one video signal into two; first and second receivers to which each output of the division unit is input and which decodes the input signal and outputs the decoded signal; a signal determination unit to which each output of the first and second receivers is input and which determines whether the video expressed by each output is based on the two divisional video signals and outputs the determination result; and a signal processing unit to which each output of the first and second receivers and the determination result are input, and which, if the determination result indicates that the video expressed by each output of the first and second receivers is based on the two divisional video signals, generates a video signal in which the videos are combined.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a video display device and a video display method for displaying a video indicated by a video signal.

  As a video display device to which a plurality of video signals are input, there is one in which different processing is performed according to the resolution of the input video signal (see, for example, Patent Document 1).

  FIG. 7 is a block diagram showing a configuration of a part related to video processing of a video display device such as a projector or a monitor for displaying a video signal. The video display device shown in FIG. 7 includes a dividing unit 102, receivers 103 and 104, a signal processing unit 105, a display unit 106, and a control unit 107. The display unit 106 is a projector or monitor that includes a liquid crystal panel drive unit and a liquid crystal panel, and displays a video signal from the signal processing unit 105. The control unit 107 includes a CPU (Central Processing Unit) and controls the operation of the signal processing unit 105.

  The dividing unit 102 includes two or more video input terminals. As video signals, video signals such as HDMI (registered trademark): (High-Definition Multimedia Interface: high definition multimedia interface) signals and DisplayPort (registered trademark) signals are used. Can be input two or more at the same time.

  When the input video signal has a low resolution (for example, a video signal with 4k resolution and 30 Hz or less), the dividing unit 102 selects two of them and outputs them to the receiver 103 and the receiver 104 as they are. .

  The selection of the video signal in the dividing unit 102 is performed based on the priority order determined for a plurality of video signal input terminals to which each video signal is input. This priority order can be switched by a switch (not shown) provided in the video display device.

  When the video signal with the highest priority input to the dividing unit 102 has a high resolution (for example, a video signal of 60 Hz or higher at 4k resolution), the dot clock synchronized with each pixel of the video signal is very high. If output as it is (4k resolution at 60 Hz, 594 MHz), it cannot be processed as parallel RGB digital signals in a circuit that performs video processing including the receiver 103 and the receiver 104 provided thereafter.

  Therefore, when the video signal input to the dividing unit 102 has a high resolution, the dividing unit 102 divides the size of the video signal in half in the horizontal direction, that is, equally to the left and right without changing the horizontal frequency. In the state where the dot clock is halved, the divided video signals indicating the left and right images are output to the receiver 103 and the receiver 104, respectively.

  In the case of a video signal of 4 Hz and 60 Hz, the dot clock is 594 MHz and the resolution is 4096 × 2016 or 3840 × 2160. The video signal is divided into 1920 × 2160 video signals and output to the receiver 103 and the receiver 104, respectively. Further, the dividing unit 102 notifies the control unit 107 of the contents of the video signal output to the receiver 103 and the receiver 104.

  The receiver 103 and the receiver 104 decode the input HDMI signal and DisplayPort signal, convert them into a dot clock, a parallel RGB digital signal, a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal (hereinafter referred to as a DE signal). The data is sent to the processing unit 105. At this time, when the frequency of the dot clock that can be processed by the circuits after the receiver 103 and the receiver 104 is low, the frequency of the dot clock is further halved, and the above-mentioned parallel operation is performed at both the rising and falling edges of the dot clock. RGB digital signals, horizontal synchronization signals, vertical synchronization signals, and DE signals may be output in synchronization.

  The control unit 107 controls the operation of the entire video display device. Regarding the video signal processing, the signal processing unit 105 is notified of the contents of the video signal output to the receiver 103 and the receiver 104 notified from the dividing unit 102.

  The signal processing unit 105 confirms the contents of the digital video signals input from the receiver 103 and the receiver 104 based on the notification from the control unit 107, and processes the video signal depending on whether the contents are divided into left and right as described above. Change the way.

  When low-resolution video signals are input to the signal processing unit 105 from the receiver 103 and the receiver 104 separately from the left and right parts, they are simultaneously displayed on two screens. In this case, it is conceivable to select either one of them as a full-screen display, but in either case, a video signal whose resolution is converted to an image size suitable for the display unit 106 is generated.

  In addition, when left and right divided video signals are input from the receiver 103 and the receiver 104 to the signal processing unit 105, the left and right screens are combined to generate a video signal whose resolution is converted to an image size suitable for the display unit 106. .

Japanese Patent Laying-Open No. 2015-060021

  In the video display device described above, the video signal processing method performed by the signal processing unit 105 is changed depending on the notification content indicating whether or not the video signal output from the division unit 102 is one image divided into left and right. . The output of the dividing unit 102 is notified from the dividing unit 102 to the signal processing unit 105 via the control unit 107. For this reason, the dividing unit 102 needs to generate a notification signal indicating the output contents in addition to selection and division of the video signal. In addition, in addition to controlling various operations of the entire video display device, the control unit 107 also needs to read notifications from the division unit 102 at any time and notify the signal processing unit 105 of the notifications. It becomes large and the configuration as a device becomes complicated.

  According to the present invention, in a video display device, a video signal is divided and processed with a simpler configuration.

The video processing apparatus of the present invention inputs two or more video signals and outputs two video signals or two divided video signals obtained by dividing one video signal into two parts;
First and second receivers for inputting, decoding and outputting each output of the dividing unit;
A signal determination unit that inputs each output of the first and second receivers, determines whether the video indicated by each output is based on the two divided video signals, and outputs a determination result;
The outputs of the first and second receivers and the determination result are input, and the determination result indicates that the video indicated by the outputs of the first and second receivers is based on two divided video signals. In some cases, the image processing apparatus includes a signal processing unit that generates a video signal obtained by combining the videos.

  A video display device of the present invention includes the above-described video processing device and a display unit that displays a video based on the video signal generated by the signal processing unit.

In the video processing method of the present invention, the dividing unit outputs two video signals or two divided video signals obtained by dividing one video signal into two,
The first and second receivers decode and output the two video signals or two divided video signals obtained by dividing one video signal into two parts,
The signal determination unit determines whether the decoded video signals or the video indicated by the two divided video signals obtained by dividing one video signal into two is based on the two divided video signals. And
In the signal processing unit, when the determination result by the determination unit indicates that the video indicated by the outputs of the first and second receivers is based on two divided video signals, the video is combined. Generate a video signal.

  In the present invention having the above-described configuration, the video display device can be divided and processed with a simpler configuration in the video display device.

It is a block diagram which shows the structure of the part regarding the video processing apparatus of one Embodiment of the video display apparatus by this invention. It is a figure which shows the horizontal direction image size detection circuit which comprises the signal determination part 14 in FIG. It is a figure which shows the vertical direction image size detection circuit which comprises the signal determination part 14 in FIG. It is a figure which shows the size comparison circuit which comprises the signal determination part 14 in FIG. 3 is a timing chart of the horizontal image size detection circuit shown in FIG. 2. 4 is a timing chart of the vertical image size detection circuit shown in FIG. 3. It is a block diagram which shows the structure of the part regarding the video processing of a video display apparatus.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a part related to a video processing apparatus of an embodiment of a video display apparatus according to the present invention.

  The video processing apparatus according to the present embodiment includes a dividing unit 9, receivers 10 and 11, a signal processing unit 12, a display unit 13, and a signal determination unit 14.

  Each of the dividing unit 9, the receivers 10 and 11, the signal processing unit 12, and the display unit 13 is the same as the dividing unit 102, the receivers 103 and 104, the signal processing unit 105, and the display unit 106 illustrated in FIG. A signal determination unit 14 is newly provided instead of the control unit 107 shown in FIG.

  The signal determination unit 14 detects the image sizes of the digital video signals input from the receiver 10 and the receiver 11. If the vertical size is larger than the horizontal size in both of the detected two image sizes, it is determined that the left and right divided video signals are input, and the vertical direction is larger than the horizontal size. Is small, it is determined that an independent single video signal is input instead of the left and right divided video signals, and the determination result is notified to the signal processing unit 12.

  The normal general image size is larger in the horizontal direction than in the vertical direction, so if video signals with an image size that is larger in the vertical direction than the horizontal size are input, There is no problem in the division unit 9 judging that the video signal is divided into left and right. Therefore, by newly providing the signal determination unit 14, the dividing unit 9 does not need to output a notification indicating whether or not the video signal is obtained by dividing one video into left and right. Further, it is possible to automatically determine whether the left-right division is performed without using the control unit 107 shown in FIG.

  Next, a configuration for performing left / right division determination in the signal determination unit 14 will be described. The signal determination unit 14 includes a horizontal image size detection circuit shown in FIG. 2, a vertical image size detection circuit shown in FIG. 3, and a size comparison circuit shown in FIG.

  The horizontal image size detection circuit shown in FIG. 2 includes a counter circuit 18 and a latch circuit 19. The counter circuit 18 receives the dot clock, the DE signal, and the horizontal synchronization signal, and the latch circuit 19 inputs the output of the counter circuit 18 and the horizontal synchronization signal and outputs the horizontal size.

  The counter circuit 18 is a counter that is reset each time by a horizontal synchronization signal, and counts the number of dot clocks only during a period in which the DE signal is active (normally high). The count result is latched each time by the horizontal synchronizing signal in the latch circuit 19, and this result is output as the horizontal size.

  FIG. 5 is a timing chart of the horizontal image size detection circuit shown in FIG. The count value of the counter circuit 18 is counted up for each dot clock during the period when the DE signal is at a high level, and is latched at the rising edge of the horizontal synchronization signal, and the value of the horizontal size is updated. At the same time, the count value of the counter circuit 18 is reset to zero.

  The vertical image size detection circuit shown in FIG. 3 includes a counter circuit 23 and a latch circuit 24. The counter circuit 23 inputs the DE signal and the vertical synchronization signal, and the latch circuit 24 inputs the output of the counter circuit 23 and the vertical synchronization signal to output the vertical size.

  The counter circuit 23 is a counter that is reset each time by the vertical synchronization signal 22 and counts the number of DE signals. The count result is latched each time by the vertical synchronizing signal 22 in the latch circuit 24, and the result is output as the vertical size.

  FIG. 6 is a timing chart of the vertical image size detection circuit shown in FIG. The count value of the counter circuit 23 is counted up for each DE signal, latched at the rising edge of the vertical synchronizing signal, and the vertical size value is updated. At the same time, the count value of the counter circuit 23 is reset to zero.

  The horizontal size and the vertical size are input to the comparison circuit 26 shown in FIG. 4. If the vertical size is larger than the horizontal size, it is determined as a left / right divided video signal, and the vertical size is larger than the horizontal size. If the size is small, it is determined as an independent single video signal that is not divided into left and right parts, and this is used as a left and right division discrimination result.

  The left / right division determination result is transmitted from the signal determination unit 14 shown in FIG. 1 to the signal processing unit 12 and used for processing in the signal processing unit 12.

  As described above, in a video display device such as a projector or a monitor that displays a high-resolution video signal, when the video signal is divided into left and right to reduce the processing speed, the image size is determined by the signal determination unit 14. If the vertical size is larger than the horizontal size, it is determined as a left / right split video signal.If the vertical size is smaller than the horizontal size, By determining that the video signal is an independent single video signal and using the determination result in the signal processing unit 12, the dividing unit 9 outputs a notification indicating whether or not the video signal is one image divided into left and right. This eliminates the need for this, and since it is possible to automatically determine whether left and right splitting is performed without using the control unit 107 shown in FIG. 7, the processing as a system can be simplified. Kill.

  In each embodiment described above, the illustrated configuration is merely an example, and the present invention is not limited to the configuration.

A part or all of the above-described embodiment can be described as follows, but is not limited to the following configuration.
(Supplementary Note 1) A division unit that inputs two or more video signals and outputs two video signals or two divided video signals obtained by dividing one video signal into two parts;
First and second receivers for inputting, decoding and outputting each output of the dividing unit;
A signal determination unit that inputs each output of the first and second receivers, determines whether the video indicated by each output is based on the two divided video signals, and outputs a determination result;
The outputs of the first and second receivers and the determination result are input, and the determination result indicates that the video indicated by the outputs of the first and second receivers is based on two divided video signals. In some cases, a video processing apparatus including a signal processing unit that generates a video signal obtained by combining the videos.
(Supplementary note 2) In the video processing device according to supplementary note 1,
The video processing apparatus, wherein the signal determination unit determines that the signal is based on the two divided video signals based on a comparison result of a horizontal size and a vertical size of a video indicated by each output of the first and second receivers.
(Supplementary Note 3) In the video processing device according to Supplementary Note 1 or Supplementary Note 2,
The dividing unit outputs a video signal obtained by dividing one video signal into two in the horizontal direction as the two divided signals,
The video processing apparatus determines that the signal determination unit is based on the two divided video signals when a vertical size of a video indicated by each output of the first and second receivers is larger than a horizontal size.
(Supplementary Note 4) In the video processing device according to Supplementary Note 3,
The signal determination unit
A vertical image size detection circuit for detecting a vertical size of an image indicated by each output of the first and second receivers;
A horizontal image size detection circuit for detecting a horizontal size of an image indicated by each output of the first and second receivers;
The vertical direction size detected by the vertical direction image size detection circuit is compared with the horizontal direction size detected by the horizontal direction image size detection circuit. When the vertical size is larger than the horizontal size, the two divided video signals are And a comparison circuit for outputting a left / right division determination result indicating that
(Additional remark 5) The video display apparatus which has a video processing apparatus in any one of additional remark 1 thru | or additional remark 4, and the display part which displays the image | video by the video signal produced | generated by the said signal processing part.
(Supplementary Note 6) The dividing unit outputs two video signals or two divided video signals obtained by dividing one video signal into two parts,
The first and second receivers decode and output the two video signals or two divided video signals obtained by dividing one video signal into two parts,
The signal determination unit determines whether the decoded video signals or the video indicated by the two divided video signals obtained by dividing one video signal into two is based on the two divided video signals. And
In the signal processing unit, when the determination result by the determination unit indicates that the video indicated by the outputs of the first and second receivers is based on two divided video signals, the video is combined. A video processing method for generating a video signal.

9 Dividing unit 10, 11 Receiver 12 Signal processing unit 13 Display unit 14 Signal determining unit 18, 23 Counter circuit 19, 24 Latch circuit 26 Comparison circuit

Claims (6)

A division unit that inputs two or more video signals and outputs two video signals or two divided video signals obtained by dividing one video signal into two parts;
First and second receivers for inputting, decoding and outputting each output of the dividing unit;
A signal determination unit that inputs each output of the first and second receivers, determines whether the video indicated by each output is based on the two divided video signals, and outputs a determination result;
The outputs of the first and second receivers and the determination result are input, and the determination result indicates that the video indicated by the outputs of the first and second receivers is based on two divided video signals. In some cases, a video processing apparatus including a signal processing unit that generates a video signal obtained by combining the videos. The video processing apparatus according to claim 1,
The video processing apparatus, wherein the signal determination unit determines that the signal is based on the two divided video signals based on a comparison result of a horizontal size and a vertical size of a video indicated by each output of the first and second receivers. The video processing apparatus according to claim 1 or 2,
The dividing unit outputs a video signal obtained by dividing one video signal into two in the horizontal direction as the two divided signals,
The video processing apparatus determines that the signal determination unit is based on the two divided video signals when a vertical size of a video indicated by each output of the first and second receivers is larger than a horizontal size. The video processing apparatus according to claim 3.
The signal determination unit
A vertical image size detection circuit for detecting a vertical size of an image indicated by each output of the first and second receivers;
A horizontal image size detection circuit for detecting a horizontal size of an image indicated by each output of the first and second receivers;
The vertical direction size detected by the vertical direction image size detection circuit is compared with the horizontal direction size detected by the horizontal direction image size detection circuit. When the vertical size is larger than the horizontal size, the two divided video signals are And a comparison circuit for outputting a left / right division determination result indicating that 5. A video display device comprising: the video processing device according to claim 1; and a display unit configured to display an image based on the video signal generated by the signal processing unit. In the dividing unit, two video signals or two divided video signals obtained by dividing one video signal into two are output.
The first and second receivers decode and output the two video signals or two divided video signals obtained by dividing one video signal into two parts,
The signal determination unit determines whether the decoded video signals or the video indicated by the two divided video signals obtained by dividing one video signal into two is based on the two divided video signals. And
In the signal processing unit, when the determination result by the determination unit indicates that the video indicated by the outputs of the first and second receivers is based on two divided video signals, the video is combined. A video processing method for generating a video signal.

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