CN107454283B - Video signal output system and method - Google Patents
Video signal output system and method Download PDFInfo
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- CN107454283B CN107454283B CN201610382390.2A CN201610382390A CN107454283B CN 107454283 B CN107454283 B CN 107454283B CN 201610382390 A CN201610382390 A CN 201610382390A CN 107454283 B CN107454283 B CN 107454283B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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Abstract
The invention relates to a video signal output system and a method. The video signal output system comprises a first video chip and a second video chip. The first video chip comprises a first video signal output circuit and an analog signal generating circuit. The analog signal generating circuit is used for outputting a first analog signal and a second analog signal. The second video chip comprises a second video signal output circuit. The first video signal output circuit generates a first horizontal synchronization signal according to the first analog signal and generates a first vertical synchronization signal according to the second analog signal. The second video signal output circuit generates a second horizontal synchronizing signal according to the first analog signal and generates a second vertical synchronizing signal according to the second analog signal.
Description
Technical Field
The present invention relates to a video signal output system and method, and more particularly, to a video signal output system with a synchronization signal simulation function.
Background
With the progress of technology, various displays are continuously being developed. Referring to fig. 1, a conventional video signal output system 100 is shown. The video signal output system 100 is used for displaying a picture on a display 190. The video signal output system 100 includes a video chip 110. The video input signal IN10 is first processed by the video chip 110 and then transmitted to the display 190 for playback. For example, the video chip 110 usually performs processes such as decompression, resolution adjustment, frame rotation, frame chrominance adjustment, and frame sharpness adjustment on the video input signal IN 10.
The video chip 110 includes a video signal output circuit 113 and a video input terminal 114. A video input signal IN10 is input by the video input terminal 114. The video signal output circuit 113 generates a horizontal synchronization signal (horizontal synchronization signal) and a vertical synchronization signal (vertical synchronization signal) according to the video input signal IN10, and outputs a video output signal OUT10 including the horizontal synchronization signal and the vertical synchronization signal to the display 190. The display 190 displays a frame according to the horizontal synchronization signal and the vertical synchronization signal to ensure that the frame can be displayed normally.
During the power-on process, the video input signal IN10 is not always input to the video chip 110, so the video signal output circuit 113 will generate the horizontal synchronization signal and the vertical synchronization signal by itself to ensure the normal display of the picture.
Referring to fig. 2, a schematic diagram of another conventional video signal output system 200 is shown. When the display 290 is large in size, the video signal output system 200 needs to adopt a dual-chip architecture to increase the processing efficiency. The video signal output system 200 includes a first video chip 210 and a second video chip 220. The first video chip 210 includes a first video signal output circuit 213 and a first video input terminal 214. The second video chip 220 includes a second video signal output circuit 223 and a second video input terminal 224.
The video input signal IN20 is divided into a first video input signal IN21 for the left half of the picture and a second video input signal IN22 for the right half of the picture. A first video input signal IN21 is input by the first video input terminal 214. The first video signal output circuit 213 generates a first horizontal synchronization signal and a first vertical synchronization signal according to the first video input signal IN21, and outputs a first video output signal OUT21 containing the first horizontal synchronization signal and the first vertical synchronization signal to the display 290.
A second video input signal IN22 is provided by the second video input 224. The second video signal output circuit 223 generates a second horizontal synchronization signal and a second vertical synchronization signal according to the second video input signal IN22, and outputs a second video output signal OUT22 containing the second horizontal synchronization signal and the second vertical synchronization signal to the display 290.
The display 290 displays the left half of the image according to the first horizontal synchronization signal and the first vertical synchronization signal, and displays the right half of the image according to the second horizontal synchronization signal and the second vertical synchronization signal, so as to ensure that the image can be displayed normally.
During the power-on process, it is not necessary to input the video input signal IN20 to the video signal output system 200, if the first video signal output circuit 213 generates the first horizontal synchronization signal and the first vertical synchronization signal by itself, and the second video signal output circuit 223 generates the second horizontal synchronization signal and the second vertical synchronization signal by itself, the first horizontal synchronization signal and the second horizontal synchronization signal may be asynchronous, the first vertical synchronization signal and the second vertical synchronization signal may also be asynchronous, and when the asynchronous condition occurs, the image of the display 290 cannot be normally lighted.
Disclosure of Invention
The invention provides a video signal output system with a synchronous signal simulation function, which utilizes an analog signal to generate two groups of horizontal synchronous signals and two groups of vertical synchronous signals. Therefore, the condition of signal asynchronism can be effectively avoided, and the picture of the display can be normally lightened.
According to an aspect of the present invention, a video signal output system having a synchronization signal simulation function is provided. The video signal output system and the display are arranged on a television, for example. The video signal output system comprises a first video chip and a second video chip. The first video chip comprises a first video signal output circuit and an analog signal generating circuit. The first video signal output circuit is used for outputting a first video output signal to the display to display a part of the picture. The first video output signal comprises a first horizontal synchronization signal and a first vertical synchronization signal. The analog signal generating circuit is used for outputting a first analog signal and a second analog signal. The second video chip comprises a second video signal output circuit. The second video signal output circuit is used for outputting a second video output signal to the display to display the rest part of the picture. The second video output signal comprises a second horizontal synchronization signal and a second vertical synchronization signal. In an analog mode, the first video signal output circuit generates a first horizontal synchronization signal according to the first analog signal and generates a first vertical synchronization signal according to the second analog signal. The second video signal output circuit generates a second horizontal synchronization signal according to the first analog signal and generates a second vertical synchronization signal according to the second analog signal.
According to another aspect of the present invention, a video signal output method having a synchronization signal simulation function is provided. The video signal output method is used for displaying a picture on a display. The video signal output method includes the following steps. A first video output signal is output to the display to display a portion of the frame. The first video output signal comprises a first horizontal synchronization signal and a first vertical synchronization signal. And outputting a second video output signal to the display to display the rest part of the picture. The second video output signal comprises a second horizontal synchronization signal and a second vertical synchronization signal. Outputting a first analog signal and a second analog signal. In an analog mode, a first horizontal synchronization signal is generated according to the first analog signal, and a first vertical synchronization signal is generated according to the second analog signal. A second horizontal synchronization signal is generated according to the first analog signal, and a second vertical synchronization signal is generated according to the second analog signal.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
fig. 1 is a schematic diagram of a conventional video signal output system.
Fig. 2 is a schematic diagram of another conventional video signal output system.
FIG. 3 is a schematic diagram of a video signal output system with a function of synchronizing signal simulation according to an embodiment of the present invention.
FIG. 4 is a flowchart illustrating a video signal output method in an analog mode according to an embodiment of the invention.
FIG. 5 is a schematic diagram of a video signal output system with a function of synchronizing signal simulation according to an embodiment of the present invention.
FIG. 6 is a flowchart illustrating a method for switching between an emulation mode and a boot mode.
FIG. 7 is a flowchart illustrating a method for determining a steady state of a video input signal.
The element numbers in the figures are illustrated as follows:
100. 200, 300, 500: video signal output system
110: video chip
113: video signal output circuit
114: video input terminal
190. 290, 390, 590: display device
210. 310, 510: first video chip
213. 313, 513: first video signal output circuit
214. 514: a first video input terminal
220. 320, 520: second video chip
223. 323, 523: second video signal output circuit
224. 524: a second video input terminal
315. 515: pulse width modulation circuit
316. 516: first video graphics array input
326. 526: second video graphics array input
517: first controller
518: first multiplexer
527: second controller
528: second multiplexer
C2: control signal
C51: a first control signal
C52: the second control signal
IN10, IN20, IN 50: video input signal
IN21, IN 51: first video input signal
IN22, IN 52: second video input signal
M31: a first pulse width modulation signal
M32: second pulse width modulation signal
OUT 10: video output signal
OUT21, OUT31, OUT 51: first video output signal
OUT22, OUT32, OUT 52: second video output signal
S2: status signal
S410, S420, S430, S610, S620, S630, S640, S650, S710, S720, S730, S740, S750, S760, S770: procedure step
Detailed Description
Referring to fig. 3, a schematic diagram of a video signal output system 300 with a function of synchronizing signal simulation according to an embodiment of the invention is shown. The video signal output system 300 is used for displaying a picture on a display 390. The video signal output system 300 includes a first video chip 310 and a second video chip 320. The first Video chip 310 includes a first Video signal output circuit 313, a Pulse Width Modulation (PWM) circuit 315, and a first Video Graphics Array (VGA) input 316. The second video chip 320 includes a second video signal output circuit 323 and a second VGA input 326.
The first video signal output circuit 313 outputs the first video output signal OUT31 to the display 390 for displaying a portion of a frame, and the second video signal output circuit 323 outputs the second video output signal OUT32 to the display 390 for displaying another portion of the frame. For example, the display 390 displays the left half of the picture according to the first video output signal OUT31, and the display 390 displays the right half of the picture according to the second video output signal OUT 32.
The first video output signal OUT31 includes a first horizontal synchronization signal and a first vertical synchronization signal, and the second video output signal OUT32 includes a second horizontal synchronization signal and a second vertical synchronization signal. The first horizontal synchronization signal and the second horizontal synchronization signal must be synchronized, otherwise the picture of the display 390 may not be lighted normally. Similarly, the first vertical synchronization signal and the second vertical synchronization signal must be synchronized, otherwise the display 390 may not be normally lighted.
In one embodiment, after the video signal output system 300 is turned On, a start-up picture is usually displayed On the display 390, and the start-up picture is usually an On Screen Display (OSD) picture. At this time, there may not be any video input signal inputted to the video signal output system 300, so the first video signal output circuit 313 and the second video signal output circuit 323 cannot generate the first horizontal synchronization signal and the second horizontal synchronization signal synchronized with each other according to the video input signal, nor generate the first vertical synchronization signal and the second vertical synchronization signal synchronized with each other according to the video input signal. Therefore, the video signal output system 300 can directly enter an analog mode after being turned on.
Referring to fig. 4, a flow chart of a video signal output method in an analog mode according to an embodiment of the invention is shown. The video signal output method of fig. 4 is described with the video signal output system 300 of fig. 3 as an example, but not limited thereto. In the analog mode, in step S410, the pwm circuit 315 outputs the first pwm signal M31 and the second pwm signal M32.
In step S420, the first video signal output circuit 313 generates the first horizontal synchronization signal according to the first PWM signal M31 and generates the first vertical synchronization signal according to the second PWM signal M32.
In step S430, the second video signal output circuit 323 generates the second horizontal synchronization signal according to the first PWM signal M31 and the second vertical synchronization signal according to the second PWM signal M32.
That is, the first horizontal synchronization signal and the second horizontal synchronization signal are generated according to the same first pwm signal M31, so that the first horizontal synchronization signal and the second horizontal synchronization signal can be synchronized; and the first vertical synchronization signal and the second vertical synchronization signal are generated by the same second pwm signal M32, so that the first vertical synchronization signal and the second vertical synchronization signal can be synchronized, thereby solving the problem that the first video signal output circuit 313 and the second video signal output circuit 323 cannot generate the first horizontal synchronization signal and the second horizontal synchronization signal synchronized with each other according to the video input signal, or cannot generate the first vertical synchronization signal and the second vertical synchronization signal synchronized with each other according to the video input signal, and the picture of the display 390 may not be normally lighted when there is no video input signal input.
In one example, the frequency of the first pwm signal M31 is about 60kHz, and the frequency of the second pwm signal M32 is about 60Hz, so as to meet the specifications of the horizontal sync signal and the vertical sync signal in 1280 × 960@60Hz, respectively, as set by VESA. However, this is not a limitation of the present invention as long as the first horizontal synchronization signal and the first vertical synchronization signal generated by the first video signal output circuit 313 according to the first pwm signal M31 and the second pwm signal M32 and the second horizontal synchronization signal and the second vertical synchronization signal generated by the second video signal output circuit 323 according to the first pwm signal M31 and the second pwm signal M32 can normally light up the screen of the display 390.
In one embodiment, the first video chip 310 receives the first PWM signal M31 through the thirteenth pin of the original first VGA input 316 and receives the second PWM signal M32 through the fourteenth pin of the original first VGA input 316. The second video chip 320 receives the first PWM signal M31 via the thirteenth pin of the original second video graphics array input 326 and receives the second PWM signal M32 via the fourteenth pin of the original second video graphics array input 326. In this way, the first video chip 310 and the second video chip 320 can generate the horizontal synchronization signal and the vertical synchronization signal synchronously by using the original first video graphic array input end 316 and the original second video graphic array input end 326 without changing the internal circuit design.
Referring to fig. 5, a schematic diagram of a video signal output system 500 with a function of synchronizing signal simulation according to an embodiment of the invention is shown. The video signal output system 500 is used for displaying a picture on a display 590. The video signal output system 500 includes a first video chip 510 and a second video chip 520. A video input signal IN50 is divided into a first video input signal IN51 and a second video input signal IN 52. A first video input signal IN51 is input to the first video chip 510 via the first video input 514, and a second video input signal IN52 is input to the second video chip 520 via the second video input 524.
The first video chip 510 includes a first video signal output circuit 513, a first video input terminal 514, a pulse width modulation circuit 515, a first video graphics array input terminal 516, a first controller 517 and a first multiplexer 518. The second video chip 520 includes a second video signal output circuit 523, a second video input 524, a second VGA input 526, a second controller 527, and a second multiplexer 528. The first video input 514 and the second video input 524 can be, for example but not limited to, displayport (dp).
Similarly, the first video signal output circuit 513 is configured to output a first video output signal OUT51 to the display 590 for displaying a portion of a picture; the second video signal output circuit 523 is used for outputting a second video output signal OUT52 to the display 590 for displaying another part of the picture. For example, the display 590 displays the left half of the image according to the first video output signal OUT51, and the display 590 displays the right half of the image according to the second video output signal OUT 52. The first video output signal OUT51 includes a first horizontal synchronization signal and a first vertical synchronization signal, and the second video output signal OUT52 includes a second horizontal synchronization signal and a second vertical synchronization signal.
The video output system 500 can operate in an analog mode and a normal mode. IN one embodiment, the analog mode and the normal mode can be switched according to the steady states of the first video input signal IN51 and the second video input signal IN 52. The following description will be made by taking fig. 6 as an example. Referring to fig. 6, a flow chart of a method for switching between the simulation mode and the normal mode is shown.
First, in step S610, the video signal output system 500 is turned on.
Next, in step S620, the video signal output system 500 directly enters the analog mode. In the analog mode, the first controller 517 outputs the first control signal C51 to the first multiplexer 518, so as to control the first multiplexer 518 to output the first pwm signal M51 and the second pwm signal M52 to the first video signal output circuit 513. The first video signal output circuit 513 generates a first horizontal synchronization signal according to the first pwm signal M51 and a first vertical synchronization signal according to the second pwm signal M52. The second controller 527 outputs the second control signal C52 to the second multiplexer 528, so as to control the second multiplexer 528 to output the first pwm signal M51, the second pwm signal M52 to the second video signal output circuit 523. The second video signal output circuit 523 generates a second horizontal synchronization signal according to the first pulse width modulation signal M51 and a second vertical synchronization signal according to the second pulse width modulation signal M52.
IN step S630, the first controller 517 determines whether the first video input signal IN51 is stable according to the first video input signal IN 51. If the first controller 517 determines that the first video input signal IN51 is stable, step S640 is performed; if the first controller 517 determines that the first video input signal IN51 is unstable, the process proceeds to step S620.
IN step 640, the first controller 517 determines whether the second video input signal IN52 is stable according to a status signal S2 output by the second controller 527, and if the first controller 517 determines that the second video input signal IN52 is stable according to the status signal S2, the process proceeds to step S650; if the first controller 517 determines that the second video input signal IN52 is unstable according to the status signal S2, the process proceeds to step S620. The second controller 527 determines whether the second video input signal IN52 is stable according to the second video input signal IN 52. If the second controller 517 determines that the second video input signal IN52 is stable, a status signal S2 indicating that the second video input signal IN52 is stable is output to the first controller 517, and if the second controller 517 determines that the second video input signal IN52 is unstable, a status signal S2 indicating that the second video input signal IN52 is unstable is output to the first controller 517.
In step S650, the video signal output system 500 enters the normal mode. The first controller 517 outputs a first control signal C51 to the first multiplexer 518 to control the first multiplexer 518 to output the first video input signal IN51 to the first video signal output circuit 513. The first video signal output circuit 513 generates a first horizontal synchronization signal and a first vertical synchronization signal according to the first video input signal IN 51. IN addition, the first controller 517 outputs a control signal C2 to the second controller 527, so as to control the second controller 527 to output a second control signal C52 to the second multiplexer 528, so as to control the second multiplexer 528 to output the second video input signal IN52 to the second video signal output circuit 523. The second video signal output circuit 523 generates a second horizontal synchronization signal and a second vertical synchronization signal according to the second video input signal IN 52.
After the video signal output system 500 enters the normal mode, the determination of steps S630 and S640 are repeated to determine whether the first video input signal IN51 or the second video input signal IN52 is IN an unstable state. When the first video input signal IN51 or the second video input signal IN52 is IN an unstable state, the process returns to step S620, so that the video signal output system 500 enters the analog mode. IN an example, when the video signal output system 500 enters the analog mode due to the unstable state of the first video input signal IN51 or the second video input signal IN52, the video signal output system 500 may cause the display 590 to display an alarm picture, which is usually an On Screen Display (OSD) picture, for warning the user that the video input signal is unstable.
Referring to fig. 7, a flow chart of a method for determining a stable state of a video input signal is shown. The first controller 517 may determine whether the first video input signal IN51 is stable through the determination method of fig. 7. Similarly, the second controller 527 can determine whether the second video input signal IN52 is stable through the determination method of fig. 7.
In step S710, the timer is reset to zero.
In step S720, a timer is started to start counting the accumulated time.
In step S730, it is determined whether the horizontal scanning value is within a predetermined interval, such as an interval of ± 80?
In step S740, it is determined whether the vertical scan value is within a predetermined interval, such as an interval of ± 4?
In step S750, it is determined whether the synchronization polarity is not changed?
In one embodiment, the order of steps S730, S740, and S750 may be changed. Alternatively, in an embodiment, step S730, step S740, and step S750 may be performed simultaneously.
If the determination result is "no" in any of the steps S730, S740, and S750, the process returns to step S710 to reset the timer to zero, and the timer is restarted in step S720. Only if yes is obtained in step S730, step S740, and step S750, the process proceeds to step S760.
In step S760, it is determined whether the accumulated time reaches a predetermined duration? If the accumulated time does not reach the predetermined duration (e.g., 100 ms), the determination of step S730, step S740, and step S750 is performed again. Step S760 is not entered until the accumulated time reaches the predetermined duration.
That is, in order to determine whether the satisfaction of the above three conditions is maintained for the predetermined duration, the determination of repeating steps S730, S740, and S750 is performed until the cumulative time has not reached the predetermined duration. Before the accumulated time has not reached the predetermined duration, if any condition cannot be met, the process jumps back to step S710 to count the accumulated time again. When the accumulated time reaches the predetermined duration and the three conditions are repeatedly determined to be satisfied, it is determined that the three conditions are satisfied for the predetermined duration.
Finally, after establishing that the three conditions are satisfied for a predetermined duration, the process proceeds to step S770. In step S770, it is determined that the signal is stable.
In the above example, in the analog mode, the horizontal synchronization signal is generated according to a first PWM signal generated by a PWM circuit, and the vertical synchronization signal is generated according to a second PWM signal generated by the PWM circuit. However, the pwm circuit is only an example of the analog signal generating circuit of the present invention, the first pwm signal is only an example of a first analog signal of the present invention, and the second pwm signal is only an example of a second analog signal of the present invention, which is not limited by the present invention. In another example, the analog signal generating circuit can be a processor, the first analog signal can be generated by the processor in cooperation with suitable software to control the voltage level of a first General Purpose input/output port (General Purpose I/O), and the second analog signal can be generated by the processor in cooperation with suitable software to control the voltage level of a second General Purpose input/output port (General Purpose I/O).
According to the embodiments of the video signal output system and method, the system adopting the dual-chip architecture can generate two groups of synchronous horizontal synchronous signals and two groups of synchronous vertical synchronous signals through the same group of pulse width modulation signals. Therefore, the condition of signal asynchronism can be effectively avoided, and the picture of the display can be normally lightened.
Although the present invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A video signal output system with synchronous signal simulation function for displaying a picture on a display comprises:
a first video chip, comprising:
a first video signal output circuit for outputting a first video output signal to the display to display a portion of the frame, wherein the first video output signal includes a first horizontal synchronization signal (horizontal sync signal) and a first vertical sync signal (vertical sync signal); and
an analog signal generating circuit for outputting a first analog signal and a second analog signal; and
a second video chip, comprising:
a second video signal output circuit for outputting a second video output signal to the display to display the rest of the frame, wherein the second video output signal comprises a second horizontal synchronization signal and a second vertical synchronization signal;
in an analog mode, the first video signal output circuit generates the first horizontal synchronization signal according to the first analog signal and generates the first vertical synchronization signal according to the second analog signal; the second video signal output circuit generates the second horizontal synchronization signal according to the first analog signal and generates the second vertical synchronization signal according to the second analog signal;
in the analog mode, the first video chip judges whether a first video input signal is stable, and the second video chip judges whether a second video input signal is stable;
after the first video chip judges that the first video input signal is stable and the second video chip judges that the second video input signal is stable, the video signal output circuit system enters a normal mode;
in the normal mode, the first video signal output circuit generates the first horizontal synchronization signal according to the first video input signal and generates the first vertical synchronization signal according to the first video input signal, and the second video signal output circuit generates the second horizontal synchronization signal according to the second video input signal and generates the second vertical synchronization signal according to the second video input signal.
2. The video signal output system of claim 1, wherein the analog signal generating circuit is a Pulse Width Modulation (PWM) circuit, the first analog signal is a first PWM signal, and the second analog signal is a second PWM signal.
3. A video signal output system according to claim 1, wherein:
in the normal mode, the first video chip judges whether the first video input signal is in an unstable state;
after the first video chip determines that the first video input signal is in the unstable state, the first video signal output circuit system is switched from the normal mode to the analog mode.
4. A video signal output system according to claim 1, wherein:
in the analog mode, the frame includes an On Screen Display (OSD) picture.
5. A video signal output system according to claim 1, wherein:
the first Video chip further comprises a Video Graphics Array (VGA) input terminal, the first Video chip receives the first analog signal through a thirteenth pin of the VGA input terminal and receives the second analog signal through a fourteenth pin of the VGA input terminal;
the second video chip further comprises a second video graphic array input end, and the second video chip receives the first analog signal through a thirteenth pin of the second video graphic array input end and receives the second analog signal through a fourteenth pin of the second video graphic array input end.
6. A video signal output method with synchronous signal simulation function is used for displaying a picture on a display, and comprises the following steps:
outputting a first video output signal to the display to display a portion of the frame, wherein the first video output signal comprises a first horizontal synchronization signal (horizontal synchronization signal) and a first vertical synchronization signal (vertical synchronization signal);
outputting a second video output signal to the display to display the rest of the frame, wherein the second video output signal comprises a second horizontal synchronization signal and a second vertical synchronization signal; and
outputting a first analog signal and a second analog signal;
in an analog mode, generating the first horizontal synchronization signal according to the first analog signal and generating the first vertical synchronization signal according to the second analog signal; generating the second horizontal synchronization signal according to the first analog signal, and generating the second vertical synchronization signal according to the second analog signal;
further comprising:
in the simulation mode, judging whether a first video input signal is stable and judging whether a second video input signal is stable; and
entering a normal mode after determining that the first video input signal is stable and the second video input signal is stable;
wherein in the normal mode, the first horizontal synchronization signal is generated according to the first video input signal, and the first vertical synchronization signal is generated according to the first video input signal; the second horizontal synchronization signal is generated according to the second video input signal, and the second vertical synchronization signal is generated according to the second video input signal.
7. The method of claim 6, wherein the first analog signal is a first PWM signal generated by a Pulse Width Modulation (PWM) circuit, and the second analog signal is a second PWM signal generated by the PWM circuit.
8. The video signal output method of claim 6, further comprising:
under the normal mode, judging whether the first video input signal is in an unstable state; and
after determining that the first video input signal is in the unstable state, switching from the normal mode to the analog mode.
9. The video signal output method of claim 6, further comprising:
in the analog mode, the frame includes an On Screen Display (OSD) picture.
10. The video signal output method according to claim 6,
a thirteenth pin of the first Video Graphics Array (VGA) receives the first analog signal, and a fourteenth pin of the first VGA receives the second analog signal;
the thirteenth pin of the second VGA input receives the first analog signal, and the fourteenth pin of the second VGA input receives the second analog signal.
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