CN107454283B - Video signal output system and method - Google Patents

Abstract

The present invention relates to a video signal output system and method. The video signal output system includes a first video chip and a second video chip. The first video chip includes a first video signal output circuit and an analog signal generating circuit. The analog signal generating circuit is used to output a first analog signal and a second analog signal. The second video chip includes a second video signal output circuit. The first video signal output circuit generates a first horizontal synchronization signal according to the first analog signal, and generates a first vertical synchronization signal according to the second analog signal. The second video signal output circuit generates a second horizontal synchronization signal according to the first analog signal, and generates a second vertical synchronization signal according to the second analog signal.

Description

Video signal output system and method

technical field

The present invention relates to a video signal output system and method, and particularly to a video signal output system with a synchronization signal simulation function.

Background technique

With the advancement of technology, various types of monitors are constantly being introduced. Please refer to FIG. 1 , which is a schematic diagram of a conventional video signal output system 100 . The video signal output system 100 is used for displaying a picture on a display 190 . The video signal output system 100 includes a video chip 110 . The video input signal IN10 is appropriately processed by the video chip 110, and then transmitted to the display 190 for playback. For example, the video chip 110 usually performs processing procedures such as decompression, resolution adjustment, image rotation, image chromaticity adjustment, and image sharpness adjustment on the video input signal IN10.

The video chip 110 includes a video signal output circuit 113 and a video input terminal 114 . The video input signal IN10 is input from the video input terminal 114 . The video signal output circuit 113 generates a horizontal synchronous signal and a vertical synchronous signal according to the video input signal IN10 , and outputs the video output signal OUT10 including the horizontal synchronous signal and the vertical synchronous signal to the display 190 . The display 190 displays the picture according to the horizontal synchronization signal and the vertical synchronization signal, so as to ensure that the picture can be displayed normally.

During the booting process, the video input signal IN10 may not necessarily be input to the video chip 110, so the video signal output circuit 113 will generate the horizontal synchronization signal and the vertical synchronization signal by itself to ensure that the picture can be displayed normally.

Please refer to FIG. 2 , which is a schematic diagram of another conventional video signal output system 200 . When the size of the display 290 is large, the video signal output system 200 needs to adopt a two-chip architecture to increase the processing efficiency. The video signal output system 200 includes a first video chip 210 and a second video chip 220 . The first video chip 210 includes a first video signal output circuit 213 and a first video input terminal 214 . The second video chip 220 includes a second video signal output circuit 223 and a second video input terminal 224 .

The video input signal IN20 is divided into a first video input signal IN21 in the left half of the screen and a second video input signal IN22 in the right half of the screen. The first video input signal IN21 is input from the first video input terminal 214 . The first video signal output circuit 213 generates a first horizontal synchronization signal and a first vertical synchronization signal according to the first video input signal IN21, and outputs a first video output signal OUT21 to Display 290.

The second video input signal IN22 is sent from the second video input terminal 224 . The second video signal output circuit 223 generates a second horizontal synchronization signal and a second vertical synchronization signal according to the second video input signal IN22, and outputs a second video output signal OUT22 to Display 290.

The display 290 displays the left half of the picture according to the first horizontal synchronization signal and the first vertical synchronization signal, and displays the right half of the picture according to the second horizontal synchronization signal and the second vertical synchronization signal, so as to ensure that the picture can be displayed normally.

During the booting process, the video input signal IN20 may not necessarily be input to the video signal output system 200. If the first video signal output circuit 213 generates the first horizontal synchronization signal and the first vertical synchronization signal by itself, the second video signal output circuit 223 automatically generates the first horizontal synchronization signal and the first vertical synchronization signal. Generate a second horizontal synchronization signal and a second vertical synchronization signal. The first horizontal synchronization signal and the second horizontal synchronization signal may be out of synchronization, and the first vertical synchronization signal and the second vertical synchronization signal may be out of synchronization. However, when an out-of-sync situation occurs, the screen of the display 290 will not be able to light up normally.

SUMMARY OF THE INVENTION

The present invention provides a video signal output system with a synchronization signal analog function, which utilizes analog signals to generate two groups of horizontal synchronization signals and two groups of vertical synchronization signals. In this way, the situation in which the signals are not synchronized can be effectively avoided, so that the screen of the display can be lit normally.

According to an aspect of the present invention, a video signal output system with a synchronization signal analog function is provided. The video signal output system is used for displaying a picture on a display, and the video signal output system and the display are arranged on a TV, for example. The video signal output system includes a first video chip and a second video chip. The first video chip includes a first video signal output circuit and an analog signal generation circuit. The first video signal output circuit is used for outputting a first video output signal to the display for displaying a part of the picture. The first video output signal includes a first horizontal synchronization signal and a first vertical synchronization signal. The analog signal generating circuit is used for outputting a first analog signal and a second analog signal. The second video chip includes a second video signal output circuit. The second video signal output circuit is used for outputting a second video output signal to the display for displaying the rest of the picture. The second video output signal includes a second horizontal synchronization signal and a second vertical synchronization signal. In an analog mode, the first video signal output circuit generates a first horizontal synchronization signal according to the first analog signal, and generates a first vertical synchronization signal according to the second analog signal. The second video signal output circuit generates a second horizontal synchronization signal according to the first analog signal, and generates a second vertical synchronization signal according to the second analog signal.

According to another aspect of the present invention, a video signal output method with a synchronization signal simulation function is provided. The video signal output method is used to display a picture on a display. The video signal output method includes the following steps. A first video output signal is output to the display to display a part of the picture. The first video output signal includes a first horizontal synchronization signal and a first vertical synchronization signal. A second video output signal is output to the display for displaying the rest of the picture. The second video output signal includes a second horizontal synchronization signal and a second vertical synchronization signal. A first analog signal and a second analog signal are output. In an analog mode, the first horizontal synchronization signal is generated according to the first analog signal, and the first vertical synchronization signal is generated according to the second analog signal. A second horizontal synchronization signal is generated according to the first analog signal, and a second vertical synchronization signal is generated according to the second analog signal.

Description of drawings

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a conventional video signal output system.

FIG. 2 is a schematic diagram of another conventional video signal output system.

3 is a schematic diagram illustrating a video signal output system with a synchronization signal simulation function according to an embodiment of the present invention.

FIG. 4 is a flowchart illustrating a video signal output method in an analog mode according to an embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating a video signal output system with a synchronization signal simulation function according to an embodiment of the present invention.

FIG. 6 is a flowchart illustrating a method for switching between the simulation mode and the boot mode.

FIG. 7 is a flowchart illustrating a method for determining a steady state of a video input signal.

The component numbers in the figure are explained as follows:

100, 200, 300, 500: Video signal output system

110: Video chip

113: Video signal output circuit

114: Video input terminal

190, 290, 390, 590: Display

210, 310, 510: the first video chip

213, 313, 513: the first video signal output circuit

214, 514: the first video input terminal

220, 320, 520: the second video chip

223, 323, 523: the second video signal output circuit

224, 524: the second video input terminal

315, 515: Pulse width modulation circuit

316, 516: the first video graphics array input

326, 526: the second video graphics array input

517: First Controller

518: First Multiplexer

527: Second Controller

528: Second Multiplexer

C2: Control signal

C51: The first control signal

C52: The second control signal

IN10, IN20, IN50: Video input signal

IN21, IN51: the first video input signal

IN22, IN52: the second video input signal

M31: The first pulse width modulation signal

M32: The second pulse width modulation signal

OUT10: Video output signal

OUT21, OUT31, OUT51: the first video output signal

OUT22, OUT32, OUT52: the second video output signal

S2: Status signal

S410, S420, S430, S610, S620, S630, S640, S650, S710, S720, S730, S740, S750, S760, S770: Process Steps

Detailed ways

Please refer to FIG. 3 , which illustrates a schematic diagram of a video signal output system 300 having a synchronization signal simulation function according to an embodiment of the present invention. The video signal output system 300 is used for displaying a picture on a display 390 . The video signal output system 300 includes a first video chip 310 and a second video chip 320 . The first video chip 310 includes a first video signal output circuit 313 , a PWM circuit 315 and a first video graphics array (VGA) input terminal 316 . The second video chip 320 includes a second video signal output circuit 323 and a second video graphics array input terminal 326 .

The first video signal output circuit 313 is used to output the first video output signal OUT31 to the display 390 to display a part of the picture, and the second video signal output circuit 323 is used to output the second video output signal OUT32 to the display 390 to display the picture. another part. For example, the display 390 displays the left half of the picture according to the first video output signal OUT31, and the display 390 displays the right half of the picture according to the second video output signal OUT32.

The first video output signal OUT31 includes a first horizontal synchronization signal and a first vertical synchronization signal, and the second video output signal OUT32 includes a second horizontal synchronization signal and a second vertical synchronization signal. The first horizontal synchronization signal and the second horizontal synchronization signal must be synchronized, otherwise the picture of the display 390 may not be properly lit. Likewise, the first vertical synchronization signal and the second vertical synchronization signal must be synchronized, otherwise the picture of the display 390 may not be properly lit.

In one embodiment, after the video signal output system 300 is turned on, a startup picture is usually displayed on the display 390, and the startup picture is usually an on screen display picture (OSD picture). At this time, no video input signal may be input to the video signal output system 300, so the first video signal output circuit 313 and the second video signal output circuit 323 cannot generate the first horizontal synchronization signal and the The second horizontal synchronization signal also cannot generate the first vertical synchronization signal and the second vertical synchronization signal synchronized with each other according to the video input signal. Therefore, after the video signal output system 300 is turned on, it will directly enter an analog mode.

Please refer to FIG. 4 , which is a flowchart of a method for outputting a video signal in an analog mode according to an embodiment of the present invention. The video signal output method of FIG. 4 is illustrated with the video signal output system 300 of FIG. 3 as an example, but is not limited thereto. In the analog mode, in step S410, the pulse width modulation circuit 315 outputs the first pulse width modulation signal M31 and the second pulse width modulation signal M32.

In step S420, the first video signal output circuit 313 generates a first horizontal synchronization signal according to the first pulse width modulation signal M31, and generates a first vertical synchronization signal according to the second pulse width modulation signal M32.

In step S430, the second video signal output circuit 323 generates a second horizontal synchronization signal according to the first pulse width modulation signal M31, and generates a second vertical synchronization signal according to the second pulse width modulation signal M32.

That is to say, the first horizontal synchronization signal and the second horizontal synchronization signal are generated according to the same first pulse width modulation signal M31, so that the first horizontal synchronization signal and the second horizontal synchronization signal can be synchronized; and the first vertical synchronization signal The second vertical synchronization signal and the second vertical synchronization signal are generated by the same second pulse width modulation signal M32, so that the first vertical synchronization signal and the second vertical synchronization signal can be synchronized. The video signal output circuit 313 and the second video signal output circuit 323 cannot generate the first horizontal synchronization signal and the second horizontal synchronization signal synchronized with each other according to the video input signal, nor can they generate the first vertical synchronization signal synchronized with each other according to the video input signal The synchronization signal and the second vertical synchronization signal may cause the problem that the picture of the display 390 may not be properly lit.

In an example, the frequency of the first pulse width modulation signal M31 is about 60kHz, and the frequency of the second pulse width modulation signal M32 is about 60Hz, so as to conform to the horizontal synchronization signal and the vertical synchronization signal in 1280*960@60Hz specified by VESA respectively. Specifications. However, this is not a limitation of the present invention, as long as the first horizontal synchronization signal and the first vertical synchronization signal generated by the first video signal output circuit 313 according to the first pulse width modulation signal M31 and the second pulse width modulation signal M32, and The second video signal output circuit 323 generates the second horizontal synchronization signal and the second vertical synchronization signal according to the first pulse width modulation signal M31 and the second pulse width modulation signal M32, so that the screen of the display 390 can be normally lit.

In one embodiment, the first video chip 310 receives the first pulse width modulation signal M31 through the thirteenth pin of the original first video graphics array input terminal 316, and transmits the first pulse width modulation signal M31 through the original first video graphics array input. The fourteenth pin of the terminal 316 receives the second PWM signal M32. The second video chip 320 receives the first pulse width modulation signal M31 through the thirteenth pin of the original second video graphics array input terminal 326 , and receives the first pulse width modulation signal M31 through the fourteenth connection of the original second video graphics array input terminal 326 . The pin receives the second pulse width modulation signal M32. In this way, the first video chip 310 and the second video chip 320 can use the original first video graphics array input terminal 316 and the second video graphics array input terminal 326 to generate synchronization without changing the internal circuit design. The horizontal sync signal and vertical sync signal.

Please refer to FIG. 5 , which illustrates a schematic diagram of a video signal output system 500 having a synchronization signal analog function according to an embodiment of the present invention. The video signal output system 500 is used for displaying a picture on a display 590 . The video signal output system 500 includes a first video chip 510 and a second video chip 520 . A video input signal IN50 is divided into a first video input signal IN51 and a second video input signal IN52. The first video input signal IN51 is input to the first video chip 510 via the first video input terminal 514 , and the second video input signal IN52 is input to the second video chip 520 via the second video input terminal 524 .

The first video chip 510 includes a first video signal output circuit 513, a first video input terminal 514, a pulse width modulation circuit 515, a first video graphics array input terminal 516, a first controller 517 and a first Multiplexer 518. The second video chip 520 includes a second video signal output circuit 523 , a second video input terminal 524 , a second video graphics array input terminal 526 , a second controller 527 and a second multiplexer 528 . Wherein, the first video input terminal 514 and the second video input terminal 524 can be, for example, but not limited to, DisplayPort (DP).

Similarly, the first video signal output circuit 513 is used for outputting the first video output signal OUT51 to the display 590 to display a part of the picture; the second video signal output circuit 523 is used for outputting the second video output signal OUT52 to the display 590 for displaying a part of the picture. Display another part of the screen. For example, the display 590 displays the left half of the picture according to the first video output signal OUT51, and the display 590 displays the right half of the picture according to the second video output signal OUT52. The first video output signal OUT51 includes a first horizontal synchronization signal and a first vertical synchronization signal, and the second video output signal OUT52 includes a second horizontal synchronization signal and a second vertical synchronization signal.

The video output system 500 is operable in an analog mode and a normal mode. In one embodiment, the analog mode and the normal mode can be switched according to the steady state of the first video input signal IN51 and the second video input signal IN52. The following description takes FIG. 6 as an example. Please refer to FIG. 6 , which is a flowchart of a method for switching between the simulation mode and the normal mode.

First, in step S610, the video signal output system 500 is powered on.

Next, in step S620, the video signal output system 500 directly enters the analog mode. In the analog mode, the first controller 517 outputs the first control signal C51 to the first multiplexer 518 to control the first multiplexer 518 to output the first pulse width modulation signal M51 and the second pulse width modulation signal M52 to the first multiplexer 518. A video signal output circuit 513 . The first video signal output circuit 513 generates a first horizontal synchronization signal according to the first pulse width modulation signal M51, and generates a first vertical synchronization signal according to the second pulse width modulation signal M52. The second controller 527 outputs the second control signal C52 to the second multiplexer 528 to control the second multiplexer 528 to output the first pulse width modulation signal M51 and the second pulse width modulation signal M52 to the second video signal output circuit 523. The second video signal output circuit 523 generates a second horizontal synchronization signal according to the first pulse width modulation signal M51, and generates a second vertical synchronization signal according to the second pulse width modulation signal M52.

In step S630, the first controller 517 determines whether the first video input signal IN51 is stable according to the first video input signal IN51. If the first controller 517 determines that the first video input signal IN51 is stable, the process proceeds to step S640; if the first controller 517 determines that the first video input signal IN51 is unstable, the process proceeds to step S620.

In step 640, the first controller 517 judges whether the second video input signal IN52 is stable according to a state signal S2 output by the second controller 527, if the first controller 517 judges that the second video input signal IN52 is stable according to the state signal S2 , then go to step S650; if the first controller 517 judges that the second video input signal IN52 is unstable according to the state signal S2, go to step S620. The second controller 527 determines whether the second video input signal IN52 is stable according to the second video input signal IN52. If the second controller 517 determines that the second video input signal IN52 is stable, it outputs a state signal S2 representing the stability of the second video input signal IN52 to the first controller 517. If the second controller 517 determines that the second video input signal IN52 is not stable If it is stable, the state signal S2 representing the instability of the second video input signal IN52 is output to the first controller 517 .

In step S650, the video signal output system 500 enters the normal mode. The first controller 517 outputs the first control signal C51 to the first multiplexer 518 to control the first multiplexer 518 to output the first video input signal IN51 to the first video signal output circuit 513 . The first video signal output circuit 513 generates a first horizontal synchronization signal and a first vertical synchronization signal according to the first video input signal IN51. In addition, the first controller 517 outputs the control signal C2 to the second controller 527 to control the second controller 527 to output the second control signal C52 to the second multiplexer 528 to control the second multiplexer 528 to output the second The video input signal IN52 is to the second video signal output circuit 523 . The second video signal output circuit 523 generates a second horizontal synchronization signal and a second vertical synchronization signal according to the second video input signal IN52.

After the video signal output system 500 enters the normal mode, steps S630 and S640 are repeatedly performed to determine whether the first video input signal IN51 or the second video input signal IN52 is in an unstable state. When the first video input signal IN51 or the second video input signal IN52 is in an unstable state, the process returns to step S620, and the video signal output system 500 enters the analog mode. In an example, when the video signal output system 500 enters the analog mode because the first video input signal IN51 or the second video input signal IN52 is in an unstable state, the video signal output system 500 can display a warning screen on the display 590, The warning picture is usually an on screen display picture (OSD picture) to warn the user that the current video input signal is unstable.

Please refer to FIG. 7 , which is a flowchart of a method for determining a steady state of a video input signal. The first controller 517 can determine whether the first video input signal IN51 is stable through the determination method of FIG. 7 . Likewise, the second controller 527 can determine whether the second video input signal IN52 is stable through the determination method of FIG. 7 .

In step S710, the timer is reset to zero.

In step S720, a timer is started to start counting the accumulated time.

In step S730, it is determined whether the horizontal scan value is within a predetermined interval, such as the interval of ±80?

In step S740, it is determined whether the vertical scan value is within a predetermined interval, for example, the interval of ±4?

In step S750, it is judged whether the synchronization polarity has not changed?

In one embodiment, the sequence of steps S730, S740, and S750 can be changed. Alternatively, in one embodiment, step S730, step S740, and step S750 may be performed simultaneously.

When any of the above steps S730, S740, and S750 is determined but the result is "No", it is necessary to return to step S710, reset the timer to zero, and restart the timer in step S720. Step S760 is entered only when the above-mentioned step S730, step S740, and step S750 all obtain the judgment result of "Yes".

In step S760, it is determined whether the accumulated time has reached a predetermined duration? If the accumulated time does not reach the predetermined duration (for example, 100 milliseconds), the judgments of steps S730, S740, and S750 are performed again. Step S760 is not entered until the accumulated time reaches the predetermined duration.

That is, in order to determine whether the above three conditions are satisfied for the predetermined duration, the determination of steps S730 , S740 and S750 are repeated until the accumulated time has not reached the predetermined duration. Before the accumulated time has reached the predetermined duration, if any conditions cannot be met, it will jump back to step S710 to re-time the accumulated time. When the accumulated time reaches the predetermined duration, and the three conditions can be satisfied after repeated multiple judgments, it can be established that the above-mentioned three conditions are established and maintained for the predetermined duration.

Finally, after the establishment of the above three conditions is established and maintained for a predetermined duration, the process proceeds to step S770. In step S770, it is determined that the signal is stable.

In the above example, in the analog mode, the horizontal synchronization signal is generated according to a first pulse width modulation signal generated by a pulse width modulation circuit, and the vertical synchronization signal is generated according to a second pulse width modulation circuit. produced by the width modulated signal. However, the PWM circuit is only an example of the analog signal generating circuit of the present invention, the first PWM signal is only an example of a first analog signal of the present invention, and the second PWM signal is only a second example of the present invention An example of an analog signal is not a limitation of the present invention. In another example, the analog signal generating circuit can be a processor, and the first analog signal can be generated by the processor cooperating with appropriate software to control the potential level of a first general purpose I/O port. The two analog signals can be generated by controlling the potential level of a second general purpose I/O port (General Purpose I/O) by the processor with appropriate software.

According to various embodiments of the video signal output system and method, the system using the dual-chip architecture can generate two sets of synchronized horizontal synchronization signals and two synchronized sets of vertical synchronization signals through the same set of pulse width modulation signals. In this way, the situation in which the signals are not synchronized can be effectively avoided, so that the screen of the display can be lit normally.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be defined by the claims.

Claims (10)

1. A video signal output system with a synchronous signal simulation function for displaying a picture on a display, comprising: A first video chip, comprising: a first video signal output circuit for outputting a first video output signal to the display to display a part of the picture, wherein the first video output signal includes a first horizontal synchronous signal and a first a vertical synchronous signal; and an analog signal generating circuit for outputting a first analog signal and a second analog signal; and A second video chip, including: a second video signal output circuit for outputting a second video output signal to the display to display the rest of the picture, wherein the second video output signal includes a second horizontal synchronization signal and a second vertical synchronization signal ; Wherein, in an analog mode, the first video signal output circuit generates the first horizontal synchronization signal according to the first analog signal, and generates the first vertical synchronization signal according to the second analog signal; the second video signal outputs The circuit generates the second horizontal synchronization signal according to the first analog signal, and generates the second vertical synchronization signal according to the second analog signal; In the simulation mode, the first video chip determines whether a first video input signal is stable, and the second video chip determines whether a second video input signal is stable; After the first video chip determines that the first video input signal is stable, and the second video chip determines that the second video input signal is stable, the video signal output circuit system enters a normal mode; In the normal mode, the first video signal output circuit generates the first horizontal synchronization signal according to the first video input signal, generates the first vertical synchronization signal according to the first video input signal, and outputs the second video signal The circuit generates the second horizontal synchronization signal according to the second video input signal, and generates the second vertical synchronization signal according to the second video input signal. 2 . The video signal output system of claim 1 , wherein the analog signal generating circuit is a pulse width modulation circuit (PWM circuit), the first analog signal is a first pulse width modulation signal, the first The two analog signals are a second pulse width modulation signal. 3. video signal output system as claimed in claim 1 is characterized in that: In the normal mode, the first video chip determines whether the first video input signal is in an unstable state; After the first video chip determines that the first video input signal is in the unstable state, the first video signal output circuit system switches from the normal mode to the analog mode. 4. video signal output system as claimed in claim 1 is characterized in that: In the simulation mode, the picture includes an on screen display picture (OSD picture). 5. video signal output system as claimed in claim 1 is characterized in that: The first video chip further includes a first video graphics array (VGA) input end, the first video chip receives the first analog signal through the thirteenth pin of the first video graphics array input end, and receiving the second analog signal through the fourteenth pin of the input end of the first video graphics array; The second video chip further includes a second video graphics array input end, the second video chip receives the first analog signal through the thirteenth pin of the second video graphics array input end, and passes the second video graphics array The fourteenth pin of the input terminal receives the second analog signal. 6. A video signal output method with a synchronization signal simulation function for displaying a picture on a display, comprising: outputting a first video output signal to the display to display a part of the picture, wherein the first video output signal includes a first horizontal synchronous signal and a first vertical synchronous signal; outputting a second video output signal to the display for displaying the rest of the frame, wherein the second video output signal includes a second horizontal synchronization signal and a second vertical synchronization signal; and outputting a first analog signal and a second analog signal; In an analog mode, the first horizontal synchronization signal is generated according to the first analog signal, and the first vertical synchronization signal is generated according to the second analog signal; the second horizontal synchronization signal is generated according to the first analog signal, and generating the second vertical synchronization signal according to the second analog signal; Also includes: In the analog mode, determining whether a first video input signal is stable, and determining whether a second video input signal is stable; and After determining that the first video input signal is stable, and determining that the second video input signal is stable, enter a normal mode; In the normal mode, the first horizontal synchronization signal is generated according to the first video input signal, the first vertical synchronization signal is generated according to the first video input signal, and the second horizontal synchronization signal is generated according to the second video input signal A synchronization signal is generated, and the second vertical synchronization signal is generated according to the second video input signal. 7 . The video signal output method of claim 6 , wherein the first analog signal is a first pulse width modulation signal generated by a pulse width modulation circuit (PWM circuit), and the second analog signal is a second pulse width modulation signal generated by the pulse width modulation circuit. 8. The video signal output method as claimed in claim 6, further comprising: In the normal mode, determining whether the first video input signal is in an unstable state; and After determining that the first video input signal is in the unstable state, switch from the normal mode to the analog mode. 9. The video signal output method as claimed in claim 6, further comprising: In the simulation mode, the picture includes an on screen display picture (OSD picture). 10. The video signal output method according to claim 6, wherein, The thirteenth pin of the first video graphics array input end (Video Graphics Array, VGA) receives the first analog signal, and the fourteenth pin of the first video graphics array input end receives the second analog signal; The thirteenth pin of a second video graphics array input terminal receives the first analog signal, and the fourteenth pin of the second video graphics array input terminal receives the second analog signal.

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