JPH078014B2 - Sync signal generator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a sync signal generation circuit, and more particularly to a sync signal generation circuit that conforms to various revision systems required for video cameras, VTRs, and the like.

[Prior Art] As shown in FIG. 3, a conventional sync signal generating circuit of this type has an original oscillation frequency (hereinafter, referred to as f _CK ) that is an integral multiple of a horizontal sync frequency (hereinafter, referred to as f _H ). Frequency divider 1 that divides (abbreviated) to f _H (or 2f _H ), and second divider that divides the output of the first frequency divider 1 to a vertical synchronization frequency (hereinafter abbreviated as f _V ). It is composed of a divider 2 and a synthesizing circuit 4 for synthesizing the outputs of the first and second frequency dividers to form a synchronizing signal required for television equipment.

[Problems to be Solved by the Invention] By the way, in the conventional synchronous signal generating circuit, a synchronous or asynchronous counter type circuit or shift register type circuit is used for the frequency divider. Of these, especially when using a counter-type circuit, f _CK
The first frequency divider 1 for dividing f to f _H (or 2 _H ) is
The frequency dividing operation by this counter becomes a source of frequency dividing noise. That is, of the frequencies between f _{CK and} f _H generated by the first frequency divider, those that fall within the video band of the television-related equipment that uses this synchronization signal generation circuit are fed through the signal system as noise. By doing so, the S / N ratio of the video signal is reduced. In particular, in devices that handle very small signals, such as video cameras, these signals are susceptible to these noises because of the high gain of the signal system.Specifically, this noise is a fixed pattern with vertical stripes on the screen. Image quality is degraded.

On the other hand, in the case of a shift register type frequency divider,
Since a signal having a frequency located in the middle of f _CK to f _H is not generated, it is possible to fundamentally cut off the generation of noise components in the video band. However, since the frequency divider of this system rotates specific data in the shift register at a constant cycle, normal sentence-circulation operation cannot be performed unless the initial value of the shift register is set. Therefore, in this method, as shown in FIG. 3, an initial reset circuit 7 is provided to reset the shift register when the equipment is started up.

However, in this system, even if the initial value is set at startup, the stability of the power supply is not so high when the battery is driven like a VTR integrated video camera. Since an instantaneous voltage drop is caused at the time of rising, the data in the shift register may change due to such a disturbance factor. When the data in the shift register changes, normal frequency division operation is not performed in this frequency divider thereafter.

Therefore, the purpose of the present invention is to use f as a frequency divider.
_To prevent this from becoming a noise source for the video band by using one that does not generate a signal at an intermediate frequency between _CK and f _H , and even if the data in the register of the frequency divider is destroyed by disturbance. The purpose of the present invention is to provide a synchronizing signal generation circuit that can return the frequency divider to the normal state again.

[Means for Solving the Problems] The sync signal generation circuit of the present invention uses an f _CK that does not generate a signal in the video band of a television-related device so as not to become a noise source in that band. First to f _H
Frequency divider, a second frequency divider that receives the output of the first frequency divider to generate a vertical synchronizing signal, and a necessary synchronizing signal that receives the outputs of the first and second frequency dividers. And a third frequency divider that _divides f _CK that operates only within the vertical blanking period determined by this synthesis circuit,
A comparator circuit for determining whether the frequency division number of the first frequency divider is normal with respect to the third frequency divider, and the comparator frequency division number of the first frequency divider. Is determined to be not normal, the first frequency divider is reset.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
Here, the first frequency divider 1 which receives the f _CK and generates the horizontal synchronizing signal is a shift register type circuit which does not become a noise source in the video band but requires setting of an initial value or a circuit equivalent thereto. To use. That is, for example, when f _CK = 1212f _H (19.070MHz), the frequency divider may be configured by using 1212 stages of shift registers, or ½f counter is 606f _H (9.535MHz). After dividing to
It may be configured by using a shift register of 606 stages. The output of the first frequency divider 1 is output by the second frequency divider 2.
Divide to f _V to generate vertical sync signal. The horizontal synchronizing signal and the vertical synchronizing signal are input to the synthesizing circuit 4 which sends out necessary synchronizing signals including a blanking period signal. f
The clock of _CK is also input to the frequency divider 3 of FIG. 3, but this third frequency divider 3 has the first blanking period after the vertical blanking period determined by the combining circuit 4 is entered. The output of the frequency divider 1 is used as a trigger. Third frequency divider 3
Is used as a reference for determining whether or not the frequency division state of the first frequency divider 1 is normal, so it is not necessary to continuously send f _H pulses, and f _CK = 1
In the case of 212f _H , the third frequency divider may be adapted to generate an output pulse at the 1212th pulse after receiving the trigger. Since the first and third frequency dividers operate with the same clock, the outputs of both frequency dividers are generated in synchronization, but these outputs are input to the comparison circuit 5 and the first frequency divider is input. It is determined whether or not the operation of 3 is normal. Comparison circuit 5
If the first frequency divider 1 determines that the operation of the first frequency divider 1 is not normal, the first frequency divider is reset and the frequency divider returns to the normal state after this point.

Here, if a disturbance is applied during the operation of the third frequency divider, the reference third frequency divider causes a miscount,
It is possible to generate a false reset pulse, but
Since the frequency divider of No. 2 restarts every vertical blanking period, it returns to the normal operation when the disturbance factor disappears.

FIG. 2 is a block diagram showing another embodiment of the present invention. This embodiment is an example suitable for the case where it is necessary to apply an external reset, and the determination result of the comparison circuit 5 is sent to an external control circuit (for example, a microcomputer) 6. The external control circuit 6 receives the external reset signal or the abnormality detection signal of the comparison circuit 5 and outputs the reset signal to the first frequency divider 1.

In the above embodiment, the third frequency divider operates by using the output of the first frequency divider as a trigger to count the clock of f _CK , but instead of this, the vertical blanking period is entered. It is also possible to start counting the clocks of f _CK and f _CK and be reset by the output of the first frequency divider 1.

The second and third frequency dividers may use circuits of either counter type or shift register type. This is because even if the counter type circuit is used, the second frequency divider does not become a noise source for the video band, and the third frequency divider operates only in the blanking period.

EFFECTS OF THE INVENTION As described above, according to the present invention, the main frequency division is performed by the shift register type which does not generate a signal in the video band and requires the initial value setting or the first frequency divider corresponding to this. The operation is performed, and the operation of the first frequency divider is confirmed by operating another third frequency divider within the vertical blanking period, and if there is a malfunction, the first frequency divider is reset. Therefore, according to the present invention, no noise is given to the video band when f _CK is _divided into f _H , and even if the first divider malfunctions due to disturbance or the like. It is possible to provide a synchronization signal generation circuit capable of self-restoration.

[Brief description of drawings]

1 and 2 are block diagrams showing an embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional example. 1 ... 1st frequency divider, 2 ... 2nd frequency divider, 3 ... 3rd frequency divider, 4 ... Combining circuit, 5 ... Comparison circuit, 6 ... External control circuit.

Claims (1)

[Claims] 1. A first frequency divider for dividing a signal having an oscillation frequency that is an integral multiple of the horizontal synchronizing frequency into the horizontal synchronizing frequency,
A second frequency divider that divides the output signal of the first frequency divider to a vertical synchronizing frequency, and a synchronization that is necessary for the video equipment by inputting the output signals of the first frequency divider and the second frequency divider. A combining circuit that generates a signal, a third frequency divider that operates only within a vertical blanking period and divides a signal having an oscillation frequency that is an integral multiple of the horizontal synchronization frequency, and a first frequency divider. A synchronization signal generating circuit comprising: a comparator that compares the output from a third frequency divider to determine whether the frequency division state of the first frequency divider is normal or not. A synchronization signal generating circuit, wherein the first frequency divider is reset when it is determined that the frequency division state of the frequency divider is abnormal.