JPH0766893B2 - Multilayer capacitor element - Google Patents

Multilayer capacitor element

Info

Publication number
JPH0766893B2
JPH0766893B2 JP63307386A JP30738688A JPH0766893B2 JP H0766893 B2 JPH0766893 B2 JP H0766893B2 JP 63307386 A JP63307386 A JP 63307386A JP 30738688 A JP30738688 A JP 30738688A JP H0766893 B2 JPH0766893 B2 JP H0766893B2
Authority
JP
Japan
Prior art keywords
dielectric
thickness
electrode
multilayer capacitor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63307386A
Other languages
Japanese (ja)
Other versions
JPH02153512A (en
Inventor
洋一郎 横谷
博司 加賀田
純一 加藤
公一 釘宮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63307386A priority Critical patent/JPH0766893B2/en
Priority to US07/443,167 priority patent/US5016137A/en
Publication of JPH02153512A publication Critical patent/JPH02153512A/en
Publication of JPH0766893B2 publication Critical patent/JPH0766893B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】 産業上の利用分野 本発明は積層コンデンサ素子に関し、特に小型大容量で
かつ電極コストの小さいものに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer capacitor element, and more particularly to a multilayer capacitor element having a large capacity and a low electrode cost.

従来の技術 近年セラミックコンデンサは素子の小型化、大容量化へ
の要求から、積層型セラミックコンデンサが、急速に普
及しつつある。また、回路の高周波化により、従来アル
ミ電解コンデンサまたはタンタル電解コンデンサが用い
られていた0.1μF以上の大容量領域に、セラミック積
層コンデンサを用いる必要が発生している。
2. Description of the Related Art In recent years, with respect to ceramic capacitors, monolithic ceramic capacitors are rapidly becoming popular due to demands for smaller size and larger capacity of elements. Further, due to the high frequency of the circuit, it has become necessary to use a ceramic multilayer capacitor in a large capacity region of 0.1 μF or more, which has conventionally been used an aluminum electrolytic capacitor or a tantalum electrolytic capacitor.

素子形状を小さく保ちながら大容量のセラミック積層コ
ンデンサを得るには、高誘電率の誘電体を用いる、誘電
体層の厚さを薄くする、容量を構成する内部電極層の層
数を増やし、かつ1層当りの電極面積を増やすことが必
要となる。
To obtain a large-capacity ceramic multilayer capacitor while keeping the element shape small, use a dielectric with a high dielectric constant, reduce the thickness of the dielectric layer, increase the number of internal electrode layers that make up the capacitance, and It is necessary to increase the electrode area per layer.

しかし誘電体層の厚さを薄くすると、誘電体誘電特性上
の問題点が発生するほか、素子の絶縁耐圧の低下、寿命
特性の低下などの問題点がある。また誘電体層の厚さを
薄くし、内部電極の層数を増すと内部電極の入っている
部分といない部分との焼成後の収縮の相違より素子に歪
がはいり、層間剥離やクラックの発生する問題点があ
る。また、内部電極層数、一層当りの電極面積の増大
は、とくにパラジウムなどの貴金属電極を使用する場合
において内部電極コストによる素子価格の増大をまねく
問題点があった。
However, when the thickness of the dielectric layer is reduced, there are problems in dielectric properties of the dielectric, and there are problems such as a decrease in withstand voltage of the device and a decrease in life characteristics. When the thickness of the dielectric layer is reduced and the number of layers of the internal electrodes is increased, the element is distorted due to the difference in shrinkage after firing between the part with internal electrodes and the part without internal electrodes, resulting in delamination and cracking. There is a problem to do. Further, the increase in the number of internal electrode layers and the electrode area per layer has a problem that the element price increases due to the internal electrode cost particularly when a precious metal electrode such as palladium is used.

発明が解決しようとする課題 本発明では以上の問題点に鑑み、小型の形状を保ったま
ま大容量を達成しかつ電極コストの小さい積層コンデン
サ素子を提供することを課題とする。
SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a multilayer capacitor element that achieves a large capacity while maintaining a compact shape and has a low electrode cost.

課題を解決するための手段 本発明は上記課題を解決するため、誘電体磁器層を介し
て少なくとも2層以上の内部電極層を交互に積層した積
層コンデンサ素子において、誘電体磁器層をPb,Ca,Srお
よびBaの内少なくともPbを含む組成物Aと、Mg,Ni,Zn,C
u,Ti,Zr,Nb,TaおよびWの内少なくとも2種の元素を含
む組成物Bの両者を含む酸化物から構成し、かつ、前記
内部電極層がパラジウム金属もしくはパラジウムを主成
分とする合金から構成し、かつ、前記誘電体磁器層の厚
さをxμm、前記内部電極層の厚さをyμmとしたと
き、 7.0μm≧ x ≧1.0μm 0.7μm≧ y ≧0.07μm 100.0≧x/y≧10.0 としたものである。
Means for Solving the Problems In order to solve the above problems, the present invention provides a multilayer capacitor element in which at least two or more internal electrode layers are alternately laminated with dielectric ceramic layers interposed between the dielectric ceramic layers of Pb and Ca. Composition A containing at least Pb of Sr, Ba and Mg, Ni, Zn, C
An alloy composed of an oxide containing both of the composition B containing at least two elements of u, Ti, Zr, Nb, Ta and W, and the internal electrode layer containing palladium metal or palladium as a main component And the thickness of the dielectric ceramic layer is x μm and the thickness of the internal electrode layer is y μm, 7.0 μm ≧ x ≧ 1.0 μm 0.7 μm ≧ y ≧ 0.07 μm 100.0 ≧ x / y ≧ It was set to 10.0.

作用 上記構成のセラミック積層コンデンサ素子においては、
Pbを含有する複合酸化物系誘電体材料とパラジウム系電
極材料の組み合わせにより、誘電体層,電極層共従来に
比べてはるかに薄膜化が可能となり、この薄膜化された
構成により、絶縁不良、寿命不良、構造欠陥が防止さ
れ、かつ寿命の低下がみられない。
Action In the ceramic multilayer capacitor element having the above configuration,
By combining Pb-containing complex oxide-based dielectric material and palladium-based electrode material, both the dielectric layer and the electrode layer can be made much thinner than conventional ones. Poor life and structural defects are prevented, and the life is not shortened.

実施例 実施例−1 誘電体層の出発原料の組成としては、次に示す組成式で
表わされる材料を用いた。
Examples Example-1 As the composition of the starting material for the dielectric layer, the materials represented by the following composition formulas were used.

A:Pb1.0(Mg1/3Nb2/30.7Ti1.19(Ni1/21/20.11O3 B:Pb0.88Sr0.15(Zn1/3Nb2/30.85Ti0.153.03+MnO2
0.35wt% C:Pb0.60Ca0.45(Mg1/3Nb2/30.95Zr0.053.05 D:Pb1.00Ba0.03(Mg1/3Nb2/30.90(Ni1/3Ta2/30.05
(Cu1/21/20.053.03 誘電体粉末は通常のセラック製造方法に従い製造した。
誘電体粉末は、仮焼後直径0.6mmのジルコニア質玉石と
ともに媒体撹拌ミルを用い湿式粉砕し、平均粒径0.14μ
mで粒径分布のそろった粉末とした。仮焼粉末は仮焼粉
末に対し6wt%のアクリル系樹脂、70wt%の溶剤および
有機系分散剤と、直径3mmのジルコニア質玉石ととも
に、振動ミル(ペイントコンディショナー)中でスラリ
ー化し、リバースロールコータを用い有機フィルム上に
所定の厚さに塗布し乾燥した。
A: Pb 1.0 (Mg 1/3 Nb 2/3 ) 0.7 Ti 1.19 (Ni 1/2 W 1/2 ) 0.11 O 3 B: Pb 0.88 Sr 0.15 (Zn 1/3 Nb 2/3 ) 0.85 Ti 0.15 O 3.03 + MnO 2
0.35wt% C: Pb 0.60 Ca 0.45 (Mg 1/3 Nb 2/3 ) 0.95 Zr 0.05 O 3.05 D: Pb 1.00 Ba 0.03 (Mg 1/3 Nb 2/3 ) 0.90 (Ni 1/3 Ta 2/3 ) 0.05
The (Cu 1/2 W 1/2 ) 0.05 O 3.03 dielectric powder was manufactured according to the usual shellac manufacturing method.
After calcination, the dielectric powder was wet pulverized with a zirconia boulder with a diameter of 0.6 mm using a medium stirring mill, and the average particle size was 0.14 μm.
A powder having a uniform particle size distribution was obtained. The calcined powder was slurried in a vibration mill (paint conditioner) together with 6 wt% acrylic resin, 70 wt% solvent and organic dispersant, and zirconia cobblestone with a diameter of 3 mm, and the reverse roll coater was used. The organic film used was applied to a predetermined thickness and dried.

内部電極の出発原料には、パラジウム黒粉末を用い、5w
t%のアクリル系樹脂、60wt%の溶剤および有機系分散
剤とともに、3本ロール混合器を用いスラリー化した。
この電極ペーストは、グラビア転写法を用い、有機フィ
ルム上に所定の厚さにあらかじめ定められた内部電極パ
ターンを印刷した。
Palladium black powder was used as the starting material for the internal electrodes, and
A three-roll mixer was used to form a slurry together with t% acrylic resin, 60 wt% solvent and organic dispersant.
This electrode paste was printed with a predetermined internal electrode pattern having a predetermined thickness on an organic film by using a gravure transfer method.

次に金属製定盤上に有機フィルム上に形成した上記誘電
体シートを圧着し、有機フィルムを剥離する操作を繰り
返して所定の厚さまで積層したダミー層の上に、上記の
内部電極パターンを所定の位置に圧着しその有機フィル
ムを剥離し、そのうえに誘電体シートを圧着しその有機
フィルムを剥離する操作を、内部電極層が51層積層され
るまで繰り返し、その上に再び誘電体シートのみを所定
の厚みまで積層してダミー層を形成した。積層体は所定
の位置で切断し、積層チップとした。
Next, the dielectric sheet formed on the organic film is pressure-bonded on a metal surface plate, and the operation of peeling off the organic film is repeated to form a predetermined internal electrode pattern on the dummy layer laminated to a predetermined thickness. The operation of pressure-bonding to the position and peeling off the organic film, pressure-bonding the dielectric sheet on it and peeling off the organic film is repeated until 51 layers of the internal electrode layers are laminated, and only the dielectric sheet is again given the predetermined thickness. A dummy layer was formed by laminating up to the thickness. The laminated body was cut at a predetermined position to obtain a laminated chip.

積層チップは磁器容器中に粗粒マグネシア粉を敷き詰め
た上にならべ、350℃まで10時間かけて昇温し6時間保
持後冷却してバインダ分をバーンアウトした。冷却後容
器内の積層チップ上に、誘電体仮焼粉と粗粒マグネシャ
を重量比で1:3に混合したマッフル粉を積層体が隠れる
程度かぶせ、マグネシア容器に蓋をして、再び前記管状
炉炉心管中に挿入し、8ppm酸素混入窒素ガスを毎分300c
c流しながら、誘電体材料Aについては1000℃、B,C,Dに
ついては850℃まで300℃/時で昇温し、45分間保持後室
温まで降温した。
The laminated chip was prepared by laying coarse-grained magnesia powder in a porcelain container, heating it to 350 ° C. over 10 hours, holding it for 6 hours, and cooling it to burn out the binder. After cooling, cover the laminated chip in the container with muffle powder, which is a mixture of dielectric calcined powder and coarse-grained magnesia in a weight ratio of 1: 3, until the laminated body is covered, cover the magnesia container, and re-tube. Inserted in the furnace core tube, 8ppm oxygen-containing nitrogen gas at 300c / min
While flowing c, the dielectric material A was heated to 1000 ° C., and B, C, and D were heated to 850 ° C. at 300 ° C./hour, held for 45 minutes, and then cooled to room temperature.

焼成後の積層チップは、内部電極が露出した断面に焼付
け銀ペーストを塗布し、空気中700℃で10分間焼き付け
て、外部電極とした。
After firing, the laminated chip was coated with a baking silver paste on the cross-section where the internal electrodes were exposed and baked in air at 700 ° C. for 10 minutes to form external electrodes.

作成した積層コンデンサ素子は外形3.2x1.6x1.25mm電極
一層あたりの有効面積は2.97mm2である。
The prepared multilayer capacitor element has an outer shape of 3.2x1.6x1.25mm and the effective area per one electrode layer is 2.97mm 2 .

作成した積層コンデンサ素子は、20℃、1kHz、信号電圧
1Vの交流で容量とtanδを測定し、5V直流電圧印加後1
分値の抵抗値を測定した。さらに、各試料10ケの試料に
ついて50V直流電圧を印加し絶縁破壊の有無を調べた。
また別の各試料10ケの試料については85℃湿度85%中に
5Vの直流電圧を印加して200時間放置したのち、素子の
絶縁抵抗値を測定した抵抗値が1x107以下となったもの
を不良とした。さらに別の各試料10ケの試料について
は、内部電極層を電極面に垂直に研磨して露出させ、試
料中の層間剥離、クラックの有無を確認した。
The created multilayer capacitor element is 20 ℃, 1kHz, signal voltage
Measure the capacity and tan δ with 1V AC and apply 5V DC voltage. 1
The resistance value of the minute value was measured. Furthermore, a DC voltage of 50 V was applied to each of the 10 samples, and the presence or absence of dielectric breakdown was examined.
For each of the other 10 samples, the humidity is 85%
After applying a DC voltage of 5 V and leaving it for 200 hours, the insulation resistance of the device was measured and the resistance was 1 × 10 7 or less. For each of 10 other samples, the internal electrode layers were polished and exposed perpendicularly to the electrode surface, and the presence or absence of delamination and cracks in the samples were confirmed.

第1表に各試料番号とその誘電体の組成、誘電体層厚、
電極膜厚をしめす。電極層厚さは印刷時の固形分塗着量
より計算した。第2表に各試料の上記の各測定結果を示
す。
Table 1 shows each sample number, its dielectric composition, dielectric layer thickness,
Show the electrode film thickness. The electrode layer thickness was calculated from the amount of solid content applied during printing. Table 2 shows the above measurement results of each sample.

第1表、第2表より明かな様に、本願発明の積層コンデ
ンサ素子は、従来のものと比べてはるかに薄膜化が可能
で、容量もほぼ計算値通り得られ、構造欠陥もほぼ無く
なり、良好な特性が得られる。誘電体厚さが1.0μmよ
り小さいものは、誘電体層の緻密性が不足し電極間に貫
通孔があるため絶縁破壊寿命不良が発生すると考えられ
る。電極層厚さが1.0μm以上または誘電体層厚さとの
比が10以下のものは誘電体層と電極層の間に欠陥が発生
し絶縁破壊、寿命不良が発生する。電極層厚みが0.07μ
m以下のものは電極の連続性がなくなり容量が低下す
る。
As is clear from Tables 1 and 2, the multilayer capacitor element of the present invention can be made much thinner than the conventional one, the capacitance can be obtained almost according to the calculated value, and the structural defects are almost eliminated. Good characteristics are obtained. If the dielectric thickness is less than 1.0 μm, it is considered that the dielectric layer lacks the denseness and there is a through hole between the electrodes, so that a dielectric breakdown life failure occurs. If the thickness of the electrode layer is 1.0 μm or more or the ratio to the thickness of the dielectric layer is 10 or less, defects occur between the dielectric layer and the electrode layer, resulting in dielectric breakdown and poor life. Electrode layer thickness is 0.07μ
If m or less, the continuity of the electrode is lost and the capacity is reduced.

実施例−2 誘電体原料は実施例−1のA,Dを用い、電極原料は実施
例−1と同様とし、第1表第2表の試料No.7と22を同様
の方法で積層し、バインダをバーンアウトした。冷却後
容器内の積層チップ上に、誘電体仮焼粉と粗粒マグネシ
ャを重量比で1:3に混合したマッフル粉を積層体が隠れ
る程度かぶせ、マグネシア容器に蓋をして、今回は空気
中で誘電体材料Aについては1000℃、B,C,Dについては8
50℃まで300℃/時で昇温し、45分間保持後室温まで降
温した。
Example-2 A and D of Example-1 were used as the dielectric raw material, the electrode raw material was the same as in Example-1, and sample Nos. 7 and 22 in Table 1 and Table 2 were laminated in the same manner. , Burned out the binder. After cooling, cover the laminated chips in the container with muffle powder, which is a mixture of the calcined dielectric powder and the coarse-grained magnesia in a weight ratio of 1: 3, until the laminated body is covered, cover the magnesia container, and air this time. Among them, 1000 ° C for dielectric material A and 8 for B, C, D
The temperature was raised to 50 ° C at 300 ° C / hour, held for 45 minutes, and then lowered to room temperature.

焼成後の積層チップは、実施例−1と同様に内部電極が
露出した断面に焼付け銀ペーストを塗布し、空気中700
℃で10分間焼き付けて、外部電極とした。作成した素子
は実施例−1同様に外形3.2x1.6x1.25mm電極一層あたり
の有効面積は2.97mm2である。
The laminated chip after firing was applied with a baking silver paste on the cross section in which the internal electrodes were exposed in the same manner as in Example-1, and 700
It was baked at 10 ° C. for 10 minutes and used as an external electrode. The produced element has an outer shape of 3.2 × 1.6 × 1.25 mm and an effective area of 2.97 mm 2 per electrode layer as in Example 1.

作成した積層コンデンサ素子は、20℃、1kHz、信号電圧
1Vの交流で容量とtanδを測定し、5V直流電圧印加後1
分値の抵抗値を測定した。さらに、各試料10ケの試料に
ついて250V直流電圧を印加し絶縁破壊の有無を調べた。
また別の各試料10ケの試料については85℃湿度85%中に
12.5Vの直流電圧を印加して200時間放置したのち、素子
の絶縁抵抗値を測定して抵抗値が1x107以下となったも
のを不良とした。さらに別の各試料10ケの試料について
は、電極層を電極面に垂直な面で研磨して露出させ、試
料中の層間剥離、クラックの有無を確認した。
The created multilayer capacitor element is 20 ℃, 1kHz, signal voltage
Measure the capacity and tan δ with 1V AC and apply 5V DC voltage. 1
The resistance value of the minute value was measured. Further, a DC voltage of 250 V was applied to each of the 10 samples, and the presence or absence of dielectric breakdown was examined.
For each of the other 10 samples, the humidity is 85%
After applying a DC voltage of 12.5 V and leaving it for 200 hours, the insulation resistance value of the device was measured and the device having a resistance value of 1 × 10 7 or less was determined to be defective. For each of 10 other samples, the electrode layer was polished and exposed on a surface perpendicular to the electrode surface, and the presence or absence of delamination and cracks in the sample was confirmed.

第3表に各試料の上記の各測定結果を示す。Table 3 shows the above measurement results of each sample.

第3表より明かな様に、素子を空気中で焼成して、電極
中にPbが含有され、Pd3Pbを結晶相として含むものは、
高電圧まで絶縁破壊が起こらず寿命特性も向上する。
As is clear from Table 3, the element which is obtained by firing the element in air and containing Pb in the electrode and containing Pd 3 Pb as a crystal phase is
Dielectric breakdown does not occur up to high voltage and life characteristics are improved.

発明の効果 本発明によれば、電極部と誘電体部のあいだの焼成収
縮、熱膨張の差によって生ずる内部欠陥を少なくでき、
薄い誘電体層を用いた積層コンデンサ素子の信頼性が向
上するばかりでなく、電極層の薄層化により電極コスト
が削減される。
EFFECTS OF THE INVENTION According to the present invention, it is possible to reduce internal defects caused by the difference in firing shrinkage and thermal expansion between the electrode part and the dielectric part,
Not only the reliability of the multilayer capacitor element using a thin dielectric layer is improved, but also the electrode cost is reduced by making the electrode layer thinner.

フロントページの続き (72)発明者 釘宮 公一 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (56)参考文献 特開 昭62−86814(JP,A)Front page continuation (72) Inventor Koichi Kugimiya 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP 62-86814 (JP, A)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】誘電体磁器層を介して少なくとも2層以上
の内部電極層を交互に積層した積層コンデンサ素子であ
って、 前記誘電体磁器層がPb,Ca,SrおよびBaの内少なくともPb
を含む組成物Aと、Mg,Ni,Zn,Cu,Ti,Zr,Nb,TaおよびW
の内少なくとも2種の元素を含む組成物Bの両者を含む
酸化物からなり、 かつ、前記内部電極層がパラジウム金属もしくはパラジ
ウムを主成分とする合金からなり、 かつ、前記誘電体磁器層の厚さをxμm、前記内部電極
層の厚さをyμmとしたとき、 7.0μm≧ x ≧1.0μm 0.7μm≧ y ≧0.07μm 100.0≧x/y≧10.0 であることを特徴とする積層コンデンサ素子。
1. A multilayer capacitor element in which at least two or more internal electrode layers are alternately laminated with a dielectric ceramic layer interposed therebetween, wherein the dielectric ceramic layer is at least Pb among Pb, Ca, Sr and Ba.
Composition A containing Mg, Ni, Zn, Cu, Ti, Zr, Nb, Ta and W
Of the composition B containing at least two elements, and the internal electrode layer is formed of palladium metal or an alloy containing palladium as a main component, and the thickness of the dielectric porcelain layer is The thickness is x μm, and the thickness of the internal electrode layers is y μm, 7.0 μm ≧ x ≧ 1.0 μm 0.7 μm ≧ y ≧ 0.07 μm 100.0 ≧ x / y ≧ 10.0.
【請求項2】内部電極層がPbをふくむPdを主成分とし、
Pd3Pbを含有することを特徴とする請求項1に記載の積
層コンデンサ素子。
2. The internal electrode layer is mainly composed of Pd including Pb,
The multilayer capacitor element according to claim 1, which contains Pd 3 Pb.
JP63307386A 1988-12-05 1988-12-05 Multilayer capacitor element Expired - Fee Related JPH0766893B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP63307386A JPH0766893B2 (en) 1988-12-05 1988-12-05 Multilayer capacitor element
US07/443,167 US5016137A (en) 1988-12-05 1989-11-30 Multi-layer ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63307386A JPH0766893B2 (en) 1988-12-05 1988-12-05 Multilayer capacitor element

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JPH02153512A JPH02153512A (en) 1990-06-13
JPH0766893B2 true JPH0766893B2 (en) 1995-07-19

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Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58165741U (en) * 1982-04-30 1983-11-04 株式会社日立製作所 Laminated disk device
JPS6083314A (en) * 1983-10-14 1985-05-11 日本電気株式会社 Laminated ceramic capacitor and method of producing same
JPS60243902A (en) * 1984-05-17 1985-12-03 マルコン電子株式会社 High dielectric constant porcelain composition
JPS61251016A (en) * 1985-04-30 1986-11-08 株式会社東芝 Manufacture of laminate type ceramic element
JPS6286814A (en) * 1985-10-14 1987-04-21 株式会社村田製作所 Laminated ceramic capacitor
JPS648227U (en) * 1987-07-03 1989-01-18
JPH0449325U (en) * 1990-08-30 1992-04-27

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JPH02153512A (en) 1990-06-13

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