JPH0774047A - Manufacture of monolithic ceramic capacitor - Google Patents

Manufacture of monolithic ceramic capacitor

Info

Publication number
JPH0774047A
JPH0774047A JP24369793A JP24369793A JPH0774047A JP H0774047 A JPH0774047 A JP H0774047A JP 24369793 A JP24369793 A JP 24369793A JP 24369793 A JP24369793 A JP 24369793A JP H0774047 A JPH0774047 A JP H0774047A
Authority
JP
Japan
Prior art keywords
thickness
ceramic
internal electrodes
ceramic green
ceramic capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24369793A
Other languages
Japanese (ja)
Inventor
Harunobu Sano
野 晴 信 佐
Hiroyuki Matsumoto
本 宏 之 松
Yukio Hamachi
地 幸 生 浜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP24369793A priority Critical patent/JPH0774047A/en
Publication of JPH0774047A publication Critical patent/JPH0774047A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)

Abstract

PURPOSE:To provide a manufacturing method, of a monolithic ceramic capacitor, wherein, when dielectric ceramic layers between internal electrodes for the monolithic ceramic capacitor are thin, a crack and a delamination are not caused in its manufacture and a withstand-voltage defect and an insulation- resistance defect are not caused. CONSTITUTION:The manufacturing method of a monolithic ceramic capacitor refers to a monolithic ceramic capacitor in which a plurality of dielectric ceramic layers in a thickness of 15mum or lower, a plurality of internal electrodes formed between the dielectric ceramic layers and external electrodes formed so as to be connected electrically to the exposed internal electrodes are contained. Films which constitute the internal electrodes are formed in such a way that they are formed on ceramic green sheets, that their central-line average roughness is at 0.5mum or lower and their 10-point average roughness is at 1/4 or lower with reference to the thickness of the ceramic green sheets regarding their surface roughness and that their thickness as a metal is at 1.5mum or lower and at 1/7 or lower with reference to the thickness of the ceramic green sheets. Then, a laminated body which is obtained by laminating a plurality of ceramic green sheets is fired.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は積層セラミックコンデ
ンサの製造方法に関し、特に、誘電体セラミック層の厚
みが15μm以下の積層セラミックコンデンサの製造方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a laminated ceramic capacitor, and more particularly to a method for manufacturing a laminated ceramic capacitor having a dielectric ceramic layer with a thickness of 15 μm or less.

【0002】[0002]

【従来の技術】積層セラミックコンデンサは、複数の誘
電体セラミック層と、各誘電体セラミック層間に形成さ
れる複数の内部電極と、誘電体セラミック層の各端面に
おいて、これらの内部電極と接続される外部電極とを含
む。
2. Description of the Related Art A monolithic ceramic capacitor has a plurality of dielectric ceramic layers, a plurality of internal electrodes formed between the dielectric ceramic layers, and is connected to these internal electrodes at each end face of the dielectric ceramic layer. Including external electrodes.

【0003】従来、積層セラミックコンデンサは、以下
のような工程を経て製造されていた。
Conventionally, a monolithic ceramic capacitor has been manufactured through the following steps.

【0004】まず、ドクターブレード法などによってシ
ート状に成形したセラミックグリーンシートを準備す
る。そして、セラミックグリーンシートの上面に、たと
えばパラジウム,銀−パラジウム,ニッケルなどの内部
電極となる金属を含む導電ペーストを所定のパターンで
スクリーン印刷する。このとき、大きなセラミックグリ
ーンシートを用い、後の工程で積層後に切断することに
よって、複数個の積層セラミックコンデンサを製造する
のが常である。したがって、内部電極を構成するための
上記導電ペースト層は、セラミックグリーンシートにお
いて、複数個の領域に分散して形成される。
First, a ceramic green sheet formed into a sheet by a doctor blade method or the like is prepared. Then, a conductive paste containing a metal to be an internal electrode such as palladium, silver-palladium, or nickel is screen-printed on the upper surface of the ceramic green sheet in a predetermined pattern. At this time, it is usual to manufacture a plurality of laminated ceramic capacitors by using a large ceramic green sheet and cutting it after laminating in a later step. Therefore, the conductive paste layer for forming the internal electrodes is formed in a plurality of regions dispersed in the ceramic green sheet.

【0005】次に、導電ペースト層を形成したセラミッ
クグリーンシートを複数枚積層し、厚み方向にプレスす
ることによって圧着する。そののち、圧着された積層体
を、個々の積層セラミックコンデンサを得るための積層
体が得られるように切断する。
Next, a plurality of ceramic green sheets each having a conductive paste layer formed thereon are laminated and pressed in the thickness direction to be pressure-bonded. After that, the pressure-bonded laminated body is cut so as to obtain a laminated body for obtaining individual monolithic ceramic capacitors.

【0006】次に、得られた個々の積層体を焼成して、
焼結体を得る。そののち、焼結体の端面に、内部電極と
導通する外部電極を焼き付けることによって、積層セラ
ミックコンデンサが完成される。
Next, the obtained individual laminated bodies are fired,
Obtain a sintered body. After that, the laminated ceramic capacitor is completed by baking external electrodes that are electrically connected to the internal electrodes on the end faces of the sintered body.

【0007】[0007]

【発明が解決しようとする課題】近年のエレクトロニク
スの発展に伴って、電子部品の小型化が急速に進行し、
積層セラミックコンデンサも小型化の傾向が顕著になっ
てきた。積層セラミックコンデンサを小型化する方法と
しては、内部電極間の誘電体セラミック層の厚みを薄く
する方法が知られている。
With the recent development of electronics, miniaturization of electronic parts is rapidly progressing,
The trend toward miniaturization of monolithic ceramic capacitors has become remarkable. As a method of miniaturizing a monolithic ceramic capacitor, a method of reducing the thickness of a dielectric ceramic layer between internal electrodes is known.

【0008】しかしながら、従来の積層セラミックコン
デンサの製造方法では、内部電極間の誘電体セラミック
層を薄くしていくと、誘電体セラミック層の厚みに対す
る内部電極となる導電ペースト層の厚みの比率が大きく
なるので、焼成の際に、導電ペースト層の収縮によっ
て、誘電体セラミック層の収縮が支配され、クラックが
発生したり、デラミネーションが発生するという問題が
あった。
However, in the conventional method for manufacturing a monolithic ceramic capacitor, as the dielectric ceramic layer between the internal electrodes is made thinner, the ratio of the thickness of the conductive paste layer serving as the internal electrode to the thickness of the dielectric ceramic layer increases. Therefore, during firing, the contraction of the conductive paste layer governs the contraction of the dielectric ceramic layer, and there is a problem that cracks or delamination occurs.

【0009】また、導電ペースト層の表面には凹凸があ
るため、焼成中にボイドが生じやすく、また、内部電極
の厚みが不均一になり、内部電極が玉状になる。そし
て、内部電極間の誘電体セラミック層を薄くしていく
と、ボイドや内部電極が玉状になっている部分での電界
集中が起こりやすくなり、耐圧不良や絶縁抵抗不良が発
生するという問題があった。
Further, since the surface of the conductive paste layer has irregularities, voids are likely to occur during firing, and the thickness of the internal electrodes becomes non-uniform, and the internal electrodes become ball-shaped. Then, when the dielectric ceramic layer between the internal electrodes is made thinner, electric field concentration is more likely to occur in the voids and the ball-shaped portions of the internal electrodes, resulting in the problem of breakdown voltage failure and insulation resistance failure. there were.

【0010】それゆえに、この発明の主たる目的は、積
層セラミックコンデンサの内部電極間の誘電体セラミッ
ク層が薄い場合、特に15μm以下の誘電体セラミック
層の場合に、その製造時にクラックおよびデラミネーシ
ョンが発生せず、耐圧不良や絶縁抵抗不良のない積層セ
ラミックコンデンサの製造方法を提供することである。
Therefore, the main object of the present invention is to produce cracks and delamination during the production of a thin dielectric ceramic layer between the internal electrodes of a monolithic ceramic capacitor, especially when the dielectric ceramic layer is 15 μm or less. It is an object of the present invention to provide a method for manufacturing a monolithic ceramic capacitor that does not have a withstand voltage defect or an insulation resistance defect.

【0011】[0011]

【課題を解決するための手段】この発明は、厚みが15
μm以下の複数の誘電体セラミック層と、それぞれの一
方端縁が誘電体セラミック層の各端面に露出するよう
に、誘電体セラミック層間に形成された複数の内部電極
と、露出した内部電極に電気的に接続されるように形成
された外部電極とを含む積層セラミックコンデンサの製
造方法であって、内部電極を構成するための膜を、セラ
ミックグリーンシート上に、その表面粗さについて、中
心線平均粗さ(Ra)が0.5μm以下で、十点平均荒
さがセラミックグリーンシートの厚みに対して1/4以
下となるように、かつ、金属としての厚みが1.5μm
以下で、セラミックグリーンシートの厚みに対して1/
7以下となるように形成する工程と、内部電極を構成す
るための膜が形成されたセラミックグリーンシートを複
数枚積層して、積層体を得る工程と、積層体を焼成する
工程とを含む、積層セラミックコンデンサの製造方法で
ある。
The present invention has a thickness of 15
A plurality of dielectric ceramic layers having a thickness of μm or less, a plurality of internal electrodes formed between the dielectric ceramic layers so that one end of each is exposed on each end face of the dielectric ceramic layer, and the exposed internal electrodes are electrically connected. A method for manufacturing a monolithic ceramic capacitor including external electrodes formed so as to be electrically connected to each other, wherein a film for forming internal electrodes is provided on a ceramic green sheet with respect to its surface roughness and a center line average. The roughness (Ra) is 0.5 μm or less, the ten-point average roughness is ¼ or less of the thickness of the ceramic green sheet, and the metal thickness is 1.5 μm.
Below, 1 / the thickness of the ceramic green sheet
A step of forming a laminated body by laminating a plurality of ceramic green sheets on which films for forming internal electrodes are formed, and a step of firing the laminated body. It is a manufacturing method of a monolithic ceramic capacitor.

【0012】[0012]

【作用】本願発明者らは、厚みが15μm以下の誘電体
セラミック層を有する積層セラミックコンデンサにおい
て、クラックおよびデラミネーションがなく、耐圧不良
や絶縁抵抗不良のない積層セラミックコンデンサを得る
ことを鋭意検討した結果、セラミックグリーンシート上
に形成される内部電極となる金属を含む膜の表面粗さお
よび金属厚みを限定することによって、耐圧不良や絶縁
抵抗不良がなく、誘電体セラミック層が薄く、小型で大
容量の積層セラミックコンデンサが得られることを見い
だした。
The inventors of the present application have earnestly studied to obtain a laminated ceramic capacitor having a dielectric ceramic layer having a thickness of 15 μm or less, which is free from cracks and delamination, and has neither breakdown voltage nor insulation resistance. As a result, by limiting the surface roughness and the metal thickness of the film containing the metal that will be the internal electrodes formed on the ceramic green sheet, there is no defective withstand voltage or defective insulation resistance, and the dielectric ceramic layer is thin, small and large. It has been found that a monolithic ceramic capacitor having a capacity can be obtained.

【0013】すなわち、セラミックグリーンシート上
に、たとえばスクリーン印刷法によって形成される金属
粉末と有機物とから形成される内部電極となる膜の表面
粗さを、中心線平均粗さ(Ra)が0.5μm以下で、
十点平均粗さがセラミックグリーンシートの厚みに対し
て1/4以下となるように限定することによって、焼成
中にボイドが発生しにくくなり、内部電極の連続性が確
保できる。そのため、内部電極が玉状にならず、誘電体
セラミック層を薄くしても、内部電極間で電界集中など
が起こりにくくなり、積層セラミックコンデンサにおい
て、耐圧不良や絶縁抵抗不良を低減することができる。
また、内部電極の連続性が向上することから、容量のば
らつきが小さくなり、容量低下などの容量不良がなくな
る。
That is, the center line average roughness (Ra) of the surface roughness of a film, which is an internal electrode formed of a metal powder and an organic substance, formed by screen printing on a ceramic green sheet is 0. Below 5 μm,
By limiting the ten-point average roughness to 1/4 or less of the thickness of the ceramic green sheet, voids are less likely to occur during firing, and continuity of the internal electrodes can be secured. Therefore, the internal electrodes do not become ball-shaped, and even if the dielectric ceramic layer is thinned, electric field concentration is less likely to occur between the internal electrodes, and withstand voltage failure and insulation resistance failure can be reduced in the multilayer ceramic capacitor. .
Further, since the continuity of the internal electrodes is improved, the variation in the capacitance is reduced, and the capacitance failure such as the capacitance reduction is eliminated.

【0014】また、内部電極となる膜の金属としての厚
みが1.5μm以下で、セラミックグリーンシートの厚
みに対して1/7以下となるように限定することによっ
て、焼成の際の、内部電極となる膜の収縮による誘電体
セラミック層の収縮への影響を小さくすることができ
る。そのため、クラックが発生したり、デラミネーショ
ンが発生する問題のない、小型で大容量の積層セラミッ
クコンデンサを製造することができる。
Further, by limiting the thickness of the metal film of the internal electrode to 1.5 μm or less, which is 1/7 or less of the thickness of the ceramic green sheet, the internal electrode during firing is limited. It is possible to reduce the influence of the shrinkage of the film that becomes the above on the shrinkage of the dielectric ceramic layer. Therefore, it is possible to manufacture a small-sized and large-capacity monolithic ceramic capacitor without the problem of cracks and delamination.

【0015】[0015]

【発明の効果】この発明によれば、誘電体セラミック層
が15μm以下と薄くなっても、その製造時にクラック
やデラミネーションが発生せず、また、ボイドなどの発
生が抑えられるので、絶縁抵抗不良,耐圧不良を低減す
ることができる。
According to the present invention, even if the thickness of the dielectric ceramic layer is as thin as 15 μm or less, cracks and delamination do not occur at the time of manufacture, and the occurrence of voids is suppressed. , It is possible to reduce the breakdown voltage failure.

【0016】さらに、内部電極の連続性が向上するの
で、静電容量のばらつきなどが小さくなる。したがっ
て、信頼性品質が高く、かつ、製造コストが安く、小型
で大容量の積層セラミックコンデンサを得ることができ
る。
Further, since the continuity of the internal electrodes is improved, the variation in capacitance is reduced. Therefore, it is possible to obtain a small-sized and large-capacity monolithic ceramic capacitor with high reliability and quality, low manufacturing cost.

【0017】この発明の上述の目的,その他の目的,特
徴および利点は、以下の実施例の詳細な説明から一層明
らかとなろう。
The above and other objects, features and advantages of the present invention will become more apparent from the detailed description of the embodiments below.

【0018】[0018]

【実施例】(実施例1)まず、純度99.8%以上のB
aCO3 ,CaCO3 ,TiO2 ,ZrO2 ,MnO2
を準備し、{(Ba0.9 Ca0.1 )O}1.01(Ti0.8
Zr0.2 )O2+0.25重量%MnO2 の割合となる
ように配合し、配合原料を得た。この配合原料をボール
ミルで湿式混合し、粉砕したのち乾燥し、空気中にて1
100℃で2時間仮焼して、仮焼物を得た。この仮焼物
を乾式粉砕機によって粉砕し、粒径が1μm以下の原料
粉末を得た。
Example (Example 1) First, B having a purity of 99.8% or more
aCO 3 , CaCO 3 , TiO 2 , ZrO 2 , MnO 2
Is prepared, {(Ba 0.9 Ca 0.1 ) O} 1.01 (Ti 0.8
Zr 0.2 ) O 2 +0.25 wt% MnO 2 were blended to obtain a blended raw material. The blended raw materials are wet mixed in a ball mill, pulverized, dried and then dried in air 1
It was calcined at 100 ° C. for 2 hours to obtain a calcined product. The calcined product was crushed by a dry crusher to obtain a raw material powder having a particle size of 1 μm or less.

【0019】この原料粉末に、ポリビニルブチラール系
バインダおよびエタノールなどの有機溶剤を加えて、ボ
ールミルによって湿式混合し、セラミックスラリを調製
した。そののち、セラミックスラリをドクターブレード
法によってシート成形し、厚み20μmの矩形のセラミ
ックグリーンシートを得た。
A polyvinyl butyral binder and an organic solvent such as ethanol were added to this raw material powder, and the mixture was wet mixed by a ball mill to prepare a ceramic slurry. After that, the ceramic slurry was formed into a sheet by a doctor blade method to obtain a rectangular ceramic green sheet having a thickness of 20 μm.

【0020】次に、このセラミックグリーンシート上
に、粒径および粒度分布の異なる数種類のNiを主体と
するNi粉末の導電ペーストをスクリーン印刷すること
によって、表1に示すA〜Fの表面粗さおよび金属厚み
の異なる内部電極を構成するための導電ペースト層を形
成した複数枚のセラミックグリーンシートを得た。
Next, the ceramic green sheet was screen-printed with a conductive paste of several kinds of Ni powders containing Ni having different particle sizes and particle size distributions to screen-print the surface roughnesses A to F shown in Table 1. Also, a plurality of ceramic green sheets having conductive paste layers for forming internal electrodes having different metal thicknesses were obtained.

【0021】[0021]

【表1】 [Table 1]

【0022】これらの表面厚さおよびNi金属厚みの異
なる導電ペースト層が形成されたセラミックグリーンシ
ートを、それぞれ個々に導電ペースト層の引き出されて
いる側が互い違いとなるように複数枚積層し、積層体を
得た。
A plurality of ceramic green sheets on which conductive paste layers having different surface thicknesses and Ni metal thicknesses are formed are laminated so that the sides from which the conductive paste layers are drawn out are staggered, and a laminated body is formed. Got

【0023】得られた積層体を、N2 雰囲気中にて40
0℃の温度に加熱し、バインダを燃焼させたのち、酸素
分圧10-9〜10-12 MPaのH2 −N2 −H2 O混合
ガスからなる還元性雰囲気中にて1300℃で2時間焼
成し、セラミック焼結体を得た。
The obtained laminated body was subjected to 40% N 2 atmosphere.
After heating to a temperature of 0 ° C. to burn the binder, it is heated at 1300 ° C. in a reducing atmosphere composed of H 2 —N 2 —H 2 O mixed gas with an oxygen partial pressure of 10 −9 to 10 −12 MPa at 2300 ° C. It was fired for a time to obtain a ceramic sintered body.

【0024】焼成後、得られたセラミック焼結体の各端
面に銀ペーストを塗布し、N2 雰囲気中において600
℃の温度で焼き付け、内部電極と電気的に接続された外
部電極を形成した。
After firing, silver paste was applied to each end surface of the obtained ceramic sintered body, and the silver paste was heated to 600 in an N 2 atmosphere.
Baking was performed at a temperature of ° C to form an external electrode electrically connected to the internal electrode.

【0025】このようにして得られた積層セラミックコ
ンデンサの外形寸法は、幅1.6mm、長さ3.2m
m、厚さ1.2mmであり、内部電極間に介在する誘電
体セラミック層の厚みは15μmであった。また、有効
誘電体セラミック層の総数は19であり、一層当たりの
対向電極の面積は2.1mm2 であった。
The external dimensions of the monolithic ceramic capacitor thus obtained are 1.6 mm in width and 3.2 m in length.
m, the thickness was 1.2 mm, and the thickness of the dielectric ceramic layer interposed between the internal electrodes was 15 μm. The total number of effective dielectric ceramic layers was 19, and the area of the counter electrode per layer was 2.1 mm 2 .

【0026】各試料を5000個ずつ、静電容量(C)
および誘電損失(tanδ)を測定するために、自動ブ
リッジ式測定器を用いて、周波数1KHz、1Vrms
を印加し温度25℃にて測定した。
5000 pieces of each sample, capacitance (C)
In order to measure the dielectric loss (tan δ) and an automatic bridge type measuring instrument, the frequency is 1 KHz, 1 Vrms.
Was applied and the temperature was measured at 25 ° C.

【0027】次に、各試料を5000個ずつ、絶縁抵抗
計を用いて、25Vの直流電圧を1分間印加して、25
℃での絶縁抵抗値(R)を測定し、静電容量(C)と絶
縁抵抗値(R)との積、すなわちCR積を求めた。な
お、静電容量(C)と絶縁抵抗値(R)との積であるC
R積が1000MΩ・μF以下の試料を不良として、そ
の個数を示した。
Next, a DC voltage of 25 V was applied for 1 minute using an insulation resistance tester to 5000 samples,
The insulation resistance value (R) at ° C was measured, and the product of the electrostatic capacitance (C) and the insulation resistance value (R), that is, the CR product was obtained. C, which is the product of the electrostatic capacitance (C) and the insulation resistance value (R)
The number of samples whose R product was 1000 MΩ · μF or less was regarded as defective and the number thereof was shown.

【0028】また、耐電圧の測定として、各試料を20
000個ずつ、直流75Vを3秒間印加し、そのときの
絶縁抵抗値が108 Ω以下の試料を不良として、その個
数を示した。
For the measurement of withstand voltage, 20 samples of each sample were used.
A DC voltage of 75 V was applied to each of the 000 samples for 3 seconds, and a sample having an insulation resistance value of 10 8 Ω or less at that time was regarded as defective and the number thereof was shown.

【0029】さらに、上述のようにして得られた積層コ
ンデンサチップを、各試料200個ずつ樹脂で固めて研
磨し、倍率200倍の顕微鏡観察を行い、デラミネーシ
ョンの有無を検査した。
Further, the laminated capacitor chips obtained as described above were fixed by 200 pieces of each sample with a resin and polished, and observed under a microscope at a magnification of 200 times to inspect for the presence of delamination.

【0030】以上の各試験の結果を表2に合わせて示
す。
The results of the above tests are also shown in Table 2.

【0031】[0031]

【表2】 [Table 2]

【0032】(実施例2)純度99.9%以上のBaT
iO3 と純度98%以上のCeO2 ,TiO2 ,BaZ
rO3 ,MnO2 を準備し、BaTiO3 100モル部
に対して、CeO2 を3モル部,TiO2 を4.5モル
部,BaZrO3 を3モル部,MnO2 を0.15モル
部となるように配合して、配合原料を得た。この配合原
料をボールミルで湿式混合し、粉砕したのち乾燥し、粒
径が1μm以下の原料粉末を得た。
(Example 2) BaT having a purity of 99.9% or more
iO 3 and CeO 2 , TiO 2 , or BaZ with a purity of 98% or more
Prepare and rO 3, MnO 2, with respect to BaTiO 3 100 molar parts, a CeO 2 3 molar parts, the TiO 2 4.5 parts by mole, 3 parts by mole of BaZrO 3, and the MnO 2 0.15 molar parts The ingredients were blended to obtain a blended raw material. The blended raw materials were wet mixed in a ball mill, pulverized and dried to obtain raw material powder having a particle size of 1 μm or less.

【0033】この原料粉末に、ポリビニルブチラール系
バインダおよびエタノールなどの有機溶剤を加えて、ボ
ールミルによって湿式混合し、セラミックスラリを調製
した。そののち、セラミックスラリをドクターブレード
法によってシート成形し、厚み10μmの矩形のセラミ
ックグリーンシートを得た。
A polyvinyl butyral binder and an organic solvent such as ethanol were added to this raw material powder, and the mixture was wet mixed by a ball mill to prepare a ceramic slurry. After that, the ceramic slurry was formed into a sheet by a doctor blade method to obtain a rectangular ceramic green sheet having a thickness of 10 μm.

【0034】次に、このセラミックグリーンシート上
に、粒径および粒度分布の異なる数種類のPdを主体と
するPd粉末の導電ペーストをスクリーン印刷すること
によって、表3に示すF〜Jの表面粗さおよび金属厚み
の異なる内部電極を構成するための導電ペースト層を形
成した複数枚のセラミックグリーンシートを得た。
Next, on this ceramic green sheet, a conductive paste of Pd powder mainly composed of several kinds of Pd having different particle sizes and particle size distributions was screen-printed to give surface roughnesses F to J shown in Table 3. Also, a plurality of ceramic green sheets having conductive paste layers for forming internal electrodes having different metal thicknesses were obtained.

【0035】[0035]

【表3】 [Table 3]

【0036】これらの表面厚さおよびPd金属厚みの異
なる導電ペースト層が形成されたセラミックグリーンシ
ートを、それぞれ個々に導電ペースト層の引き出されて
いる側が互い違いとなるように複数枚積層し、積層体を
得た。
A plurality of ceramic green sheets on which the conductive paste layers having different surface thicknesses and Pd metal thicknesses are formed are laminated so that the sides from which the conductive paste layers are drawn out are alternately staggered to form a laminate. Got

【0037】得られた積層体を、大気中にて400℃の
温度に加熱し、バインダを燃焼させたのち、大気中にて
1300℃で2時間焼成し、セラミック焼結体を得た。
The obtained laminated body was heated to a temperature of 400 ° C. in the atmosphere to burn the binder, and then fired in the atmosphere at 1300 ° C. for 2 hours to obtain a ceramic sintered body.

【0038】焼成後、得られたセラミック焼結体の各端
面に銀ペーストを塗布し、大気中において750℃の温
度で焼き付け、内部電極と電気的に接続された外部電極
を形成した。
After firing, silver paste was applied to each end surface of the obtained ceramic sintered body and baked at a temperature of 750 ° C. in the atmosphere to form an external electrode electrically connected to the internal electrode.

【0039】このようにして得られた積層セラミックコ
ンデンサの外形寸法は、幅1.6mm、長さ3.2m
m、厚さ1.2mmであり、内部電極間に介在する誘電
体セラミック層の厚みは7.5μmであった。また、有
効誘電体セラミック層の総数は19であり、一層当たり
の対向電極の面積は2.1mm2 であった。
The external dimensions of the monolithic ceramic capacitor thus obtained are 1.6 mm in width and 3.2 m in length.
m, the thickness was 1.2 mm, and the thickness of the dielectric ceramic layer interposed between the internal electrodes was 7.5 μm. The total number of effective dielectric ceramic layers was 19, and the area of the counter electrode per layer was 2.1 mm 2 .

【0040】得られた各試料について、実施例と同様の
方法で各特性を測定した。以上の各試験の結果を表4に
合わせて示す。
The characteristics of each of the obtained samples were measured in the same manner as in the examples. The results of the above tests are also shown in Table 4.

【0041】[0041]

【表4】 [Table 4]

【0042】表2および表4から明らかなように、この
発明の製造方法によって作製した積層セラミックコンデ
ンサは、コンデンサ特性を損なうことなく、デラミネー
ションのような致命的欠陥の発生を防止することがで
き、耐圧不良,絶縁抵抗不良などがなく、静電容量や誘
電損失のばらつきも小さい。
As is clear from Tables 2 and 4, the laminated ceramic capacitor manufactured by the manufacturing method of the present invention can prevent the occurrence of fatal defects such as delamination without impairing the capacitor characteristics. In addition, there are no breakdown voltage failures, insulation resistance failures, etc., and variations in capacitance and dielectric loss are small.

【0043】それに対し、この発明の範囲外では、次の
ような特性を示し好ましくない。
On the other hand, outside the scope of the present invention, the following characteristics are not preferable.

【0044】Eのような中心線平均粗さRaが0.5μ
mよりも大きい導電ペースト層が形成されたセラミック
グリーンシートを用いた積層セラミックコンデンサで
は、絶縁抵抗不良,耐圧不良が発生し、静電容量および
誘電損失のばらつきが大きくなる。
The centerline average roughness Ra like E is 0.5 μ.
In a multilayer ceramic capacitor using a ceramic green sheet having a conductive paste layer larger than m, defective insulation resistance and defective withstand voltage occur, resulting in large variations in capacitance and dielectric loss.

【0045】Fのような金属厚みtが1.5μmよりも
大きい導電ペースト層が形成されたセラミックグリーン
シートを用いた積層セラミックコンデンサでは、デラミ
ネーション不良が発生し、それに伴い、絶縁抵抗不良,
耐圧不良が発生する。また、静電容量の値が小さくな
り、ばらつきも大きくなる。さらに、誘電損失の値が大
きくなり、ばらつきも大きくなる。
A laminated ceramic capacitor using a ceramic green sheet on which a conductive paste layer having a metal thickness t of more than 1.5 μm, such as F, causes delamination failure, which causes insulation resistance failure.
A breakdown voltage occurs. Further, the value of the electrostatic capacitance becomes small and the variation becomes large. Further, the value of the dielectric loss becomes large, and the variation also becomes large.

【0046】Jのような十点平均粗さRzの厚みがセラ
ミックグリーンシート厚みに対して1/4よりも大きい
導電ペースト層が形成されたセラミックグリーンシート
を用いた積層セラミックコンデンサでは、絶縁抵抗不
良,耐圧不良が発生し、静電容量および誘電損失のばら
つきが大きくなる。
A multilayer ceramic capacitor using a ceramic green sheet having a conductive paste layer having a thickness of 10-point average roughness Rz larger than ¼ of the thickness of the ceramic green sheet, such as J, has a poor insulation resistance. ∙ Defects in withstand voltage occur, resulting in large variations in capacitance and dielectric loss.

【0047】Kのような金属厚みtがセラミックグリー
ンシート厚みに対して1/7よりも大きい導電ペースト
層が形成されたセラミックグリーンシートを用いた積層
セラミックコンデンサでは、デラミネーション不良が発
生し、それに伴い、絶縁抵抗不良,耐圧不良が発生す
る。また、静電容量の値が小さくなり、ばらつきも大き
くなる。さらに、誘電損失の値が大きくなり、ばらつき
も大きくなる。
In a laminated ceramic capacitor using a ceramic green sheet having a conductive paste layer in which a metal thickness t such as K is greater than 1/7 of the ceramic green sheet thickness, delamination failure occurs, and As a result, insulation resistance defects and breakdown voltage defects occur. Further, the value of the electrostatic capacitance becomes small and the variation becomes large. Further, the value of the dielectric loss becomes large, and the variation also becomes large.

【0048】なお、この発明の実施例において、内部電
極を構成するための膜の形成方法として、スクリーン印
刷による形成方法を示したが、形成方法としては、これ
に限定されるものではなく、たとえば、予めキャリアフ
ィルム上に形成した膜をセラミックグリーンシート上に
転写することによって形成する方法や、グラビア印刷に
よる形成方法でも同様の効果が得られる。
In the embodiments of the present invention, the film forming method for forming the internal electrodes is shown by the screen printing method, but the forming method is not limited to this. The same effect can be obtained by a method of forming a film formed on a carrier film in advance by transferring it onto a ceramic green sheet or a forming method by gravure printing.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 厚みが15μm以下の複数の誘電体セラ
ミック層、 それぞれの一方端縁が前記誘電体セラミック層の各端面
に露出するように、前記誘電体セラミック層間に形成さ
れた複数の内部電極、および露出した前記内部電極に電
気的に接続されるように形成された外部電極を含む積層
セラミックコンデンサの製造方法であって、 前記内部電極を構成するための膜を、セラミックグリー
ンシート上に、その表面粗さについて、中心線平均粗さ
(Ra)が0.5μm以下で、十点平均粗さ(Rz)が
前記セラミックグリーンシートの厚みに対して1/4以
下となるように、かつ、金属としての厚みが1.5μm
以下で、前記セラミックグリーンシートの厚みに対して
1/7以下となるように形成する工程、 前記内部電極を構成するための前記膜が形成された前記
セラミックグリーンシートを複数枚積層して、積層体を
得る工程、および前記積層体を焼成する工程を含む、積
層セラミックコンデンサの製造方法。
1. A plurality of dielectric ceramic layers having a thickness of 15 μm or less, and a plurality of internal electrodes formed between the dielectric ceramic layers such that one edge of each is exposed at each end face of the dielectric ceramic layer. And a method for manufacturing a laminated ceramic capacitor including an external electrode formed so as to be electrically connected to the exposed internal electrode, wherein a film for forming the internal electrode is formed on a ceramic green sheet, Regarding the surface roughness, the center line average roughness (Ra) is 0.5 μm or less and the ten-point average roughness (Rz) is 1/4 or less of the thickness of the ceramic green sheet, and Thickness as metal is 1.5μm
In the following, a step of forming the ceramic green sheet to have a thickness of 1/7 or less with respect to the thickness of the ceramic green sheet, stacking a plurality of the ceramic green sheets having the film for forming the internal electrodes, and stacking the stacked layers. A method of manufacturing a monolithic ceramic capacitor, comprising the steps of obtaining a body and firing the laminate.
JP24369793A 1993-09-02 1993-09-02 Manufacture of monolithic ceramic capacitor Pending JPH0774047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24369793A JPH0774047A (en) 1993-09-02 1993-09-02 Manufacture of monolithic ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24369793A JPH0774047A (en) 1993-09-02 1993-09-02 Manufacture of monolithic ceramic capacitor

Publications (1)

Publication Number Publication Date
JPH0774047A true JPH0774047A (en) 1995-03-17

Family

ID=17107646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24369793A Pending JPH0774047A (en) 1993-09-02 1993-09-02 Manufacture of monolithic ceramic capacitor

Country Status (1)

Country Link
JP (1) JPH0774047A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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JP2009124172A (en) * 2009-02-05 2009-06-04 Shoei Chem Ind Co Method of manufacturing laminated electronic component
JP2009147359A (en) * 2009-02-05 2009-07-02 Shoei Chem Ind Co Conductor paste for internal electrode of laminated electronic component and laminated electronic component using the same
JP2010165964A (en) * 2009-01-19 2010-07-29 Murata Mfg Co Ltd Multilayer coil and method of manufacturing the same
US7817043B2 (en) 2004-11-30 2010-10-19 Canon Kabushiki Kaisha Radio frequency tag
US8867190B2 (en) 2011-09-08 2014-10-21 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component having an average surface roughness to provide adhesion strength between a dielectric layer and inner electrode and fabrication method thereof
JP2017017310A (en) * 2015-06-26 2017-01-19 株式会社村田製作所 Mounting substrate
US10325721B2 (en) 2015-03-27 2019-06-18 Tdk Corporation Multilayer ceramic electronic device with dielectric layers and internal electrode layers

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100351039B1 (en) * 1999-10-28 2002-08-30 가부시키가이샤 무라타 세이사쿠쇼 Monolithic ceramic electronic component and method for making the same
US7817043B2 (en) 2004-11-30 2010-10-19 Canon Kabushiki Kaisha Radio frequency tag
JP2010165964A (en) * 2009-01-19 2010-07-29 Murata Mfg Co Ltd Multilayer coil and method of manufacturing the same
JP2009124172A (en) * 2009-02-05 2009-06-04 Shoei Chem Ind Co Method of manufacturing laminated electronic component
JP2009147359A (en) * 2009-02-05 2009-07-02 Shoei Chem Ind Co Conductor paste for internal electrode of laminated electronic component and laminated electronic component using the same
US8867190B2 (en) 2011-09-08 2014-10-21 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component having an average surface roughness to provide adhesion strength between a dielectric layer and inner electrode and fabrication method thereof
US10325721B2 (en) 2015-03-27 2019-06-18 Tdk Corporation Multilayer ceramic electronic device with dielectric layers and internal electrode layers
US10636568B2 (en) 2015-03-27 2020-04-28 Tdk Corporation Multilayer ceramic electronic device with dielectric layers and internal electrode layers
US10726992B2 (en) 2015-03-27 2020-07-28 Tdk Corporation Multilayer ceramic electronic device with dielectric layers and internal electrode layers
JP2017017310A (en) * 2015-06-26 2017-01-19 株式会社村田製作所 Mounting substrate

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