JP2017017310A - Mounting substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mounting substrate mounted with a multilayer ceramic capacitor in which insertion loss characteristics hardly change due to the difference in a mounting position.SOLUTION: A multilayer ceramic capacitor 10 connected to an output electrode 104 and an input electrode 106 of a mounting substrate 100A includes a laminated body 12. In a lamination direction x of the laminated body 12, each of a minimal length from a first inner electrode 16a' on an outside to a surface of an external electrode 20 on a first main surface 12a side and a minimal length from a second inner electrode 16b' on the outside to a surface of an external electrode 20 on a second main surface 12b side is equal to or less than 40 μm. In a width direction y of the laminated body 12, each of a minimal length from an end portion of an inner electrode 16 to a surface of an external electrode 20 on a first side surface 12c side and a minimal length from the end portion of the inner electrode 16 to a surface of an external electrode 20 on a second side surface 12d side is equal to or less than 40 μm.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a mounting substrate, and in particular, a laminated body having a plurality of laminated dielectric layers and a plurality of internal electrodes, and an external electrode formed on an end surface of the laminated body so as to be electrically connected to the internal electrodes It is related with the mounting board | substrate with which the multilayer ceramic capacitor provided with was mounted.

In an electronic circuit using an IC such as an operational amplifier, a signal output from the IC is amplified by superimposing a direct current with a transistor and sent to the next electronic component. However, depending on the electronic component that receives the signal, it may be more convenient to suppress the direct current flow and receive only the signal. Therefore, a capacitor is inserted between the IC and the electronic component that receives the signal, and the signal is allowed to pass while being suppressed. Such a capacitor is called a coupling capacitor. This coupling capacitor is required to have a lower insertion loss in a wider frequency region in order not to attenuate the signal over a wide frequency range.
The insertion loss is greatly influenced by the capacitance component in the low frequency region, and is greatly affected by two components of the equivalent series inductance and the equivalent series resistance in the high frequency region.
Here, there is a multilayer capacitor described in Patent Document 1 as a coupling capacitor. Patent Document 1 describes that the multilayer capacitor is mounted on the substrate so that the internal electrode of the multilayer capacitor is perpendicular to the surface direction of the mounting surface of the substrate in order to further reduce the equivalent series inductance. Here, as a mounting method of the multilayer capacitor, generally, a method of picking up the taped multilayer capacitor with a nozzle of a mounting machine and mounting it on a substrate is taken. Therefore, in order for the internal electrodes to be perpendicular to the surface direction of the mounting surface of the substrate, it is necessary to align the stacking directions of the internal electrodes in advance.

JP 2004-296940 A

  However, in the multilayer ceramic capacitor such as the multilayer capacitor described in Patent Document 1, the internal electrode is embedded inside, and the stacking direction of the internal electrode is difficult to distinguish from the appearance. Therefore, it is necessary to determine the stacking direction of the internal electrodes before taping the multilayer ceramic capacitor, which is costly to determine and if the direction of the internal electrodes is incorrect, the equivalent series inductance cannot be kept low. As a result, when mounted on the substrate, there is a risk that the insertion loss characteristic varies in the high frequency region.

  Therefore, a main object of the present invention is to provide a mounting board on which a multilayer ceramic capacitor having a small change in insertion loss characteristics due to a difference in mounting posture is mounted.

A mounting substrate according to the present invention includes an output electrode that outputs a signal including a frequency region of 10 GHz or more, an input electrode that inputs a signal including a frequency region of 10 GHz or more, and a multilayer ceramic capacitor connected to the output electrode and the input electrode A mounting board comprising:
A multilayer ceramic capacitor comprises a rectangular parallelepiped laminate,
The multilayer body includes a plurality of dielectric layers and a plurality of internal electrodes that are stacked, and further, a first main surface and a second main surface that are opposed to the stacking direction, and a width direction orthogonal to the stacking direction. A first side surface and a second side surface facing each other, and a first end surface and a second end surface facing each other in a length direction orthogonal to the stacking direction and the width direction;
Multilayer ceramic capacitors
A first external electrode that covers the first end surface, extends from the first end surface, and is disposed to cover the first main surface, the second main surface, the first side surface, and the second side surface;
A second external electrode covering the second end surface and extending from the second end surface and arranged to cover the first main surface, the second main surface, the first side surface and the second side surface. ,
The plurality of internal electrodes have a first internal electrode connected to the first external electrode and a second internal electrode connected to the second external electrode,
When viewed in respective cross sections including the first external electrode and the second external electrode formed on the first main surface, the second main surface, the first side surface and the second side surface,
The stacking direction from the internal electrode disposed closest to the first main surface to the surface of the external electrode disposed on the first main surface side of the first internal electrode and the second internal electrode in the stacking direction Of the external electrode disposed on the second main surface side from the internal electrode disposed at the position closest to the second main surface among the first internal electrode and the second internal electrode in the dimension along the stacking direction and the stacking direction The longest dimension among the dimensions along the stacking direction to the surface is 40 μm or less, and
Of the first internal electrode and the second internal electrode in the width direction, the first internal electrode disposed at a position closest to the first side surface or the surface of the second internal electrode is disposed on the first side surface side. The first internal electrode or the second internal electrode disposed at a position closest to the second side surface of the first internal electrode or the second internal electrode in the width direction or the dimension along the width direction to the surface of the external electrode. The mounting substrate is characterized in that the longest dimension among the dimensions along the width direction from the surface of the internal electrode to the surface of the external electrode disposed on the second side surface side is 40 μm or less.
Further, the mounting substrate according to the present invention includes an output electrode that outputs a signal including a frequency region of 10 GHz or more, an input electrode that inputs a signal including a frequency region of 10 GHz or more, and a stacked layer connected to the output electrode and the input electrode. A mounting board comprising a ceramic capacitor,
A multilayer ceramic capacitor comprises a rectangular parallelepiped laminate,
The multilayer body includes a plurality of dielectric layers and a plurality of internal electrodes that are stacked, and further, a first main surface and a second main surface that are opposed to the stacking direction, and a width direction orthogonal to the stacking direction. A first side surface and a second side surface facing each other, and a first end surface and a second end surface facing each other in a length direction orthogonal to the stacking direction and the width direction;
Multilayer ceramic capacitors
A first external electrode that covers the first end surface, extends from the first end surface, and is disposed to cover the first main surface, the second main surface, the first side surface, and the second side surface;
A second external electrode covering the second end surface and extending from the second end surface and arranged to cover the first main surface, the second main surface, the first side surface and the second side surface. ,
The plurality of internal electrodes have a first internal electrode connected to the first external electrode and a second internal electrode connected to the second external electrode,
When viewed in respective cross sections including the first external electrode and the second external electrode formed on the first main surface, the second main surface, the first side surface and the second side surface,
The stacking direction from the internal electrode disposed closest to the first main surface to the surface of the external electrode disposed on the first main surface side of the first internal electrode and the second internal electrode in the stacking direction Of the external electrode disposed on the second main surface side from the internal electrode disposed at the position closest to the second main surface among the first internal electrode and the second internal electrode in the dimension along the stacking direction and the stacking direction The longest dimension among the dimensions along the stacking direction to the surface is 40 μm or less, and
Of the first internal electrode and the second internal electrode in the width direction, the first internal electrode disposed at a position closest to the first side surface or the surface of the second internal electrode is disposed on the first side surface side. The first internal electrode or the second internal electrode disposed at a position closest to the second side surface of the first internal electrode or the second internal electrode in the width direction or the dimension along the width direction to the surface of the external electrode. The longest dimension among the dimensions along the width direction from the surface of the internal electrode to the surface of the external electrode disposed on the second side surface is 40 μm or less,
The multilayer ceramic capacitor provided on the mounting board is
A multilayer ceramic capacitor mounted such that a plurality of internal electrodes of the multilayer ceramic capacitor are parallel to the mounting surface;
A mounting substrate comprising: a multilayer ceramic capacitor mounted so that a plurality of internal electrodes of the multilayer ceramic capacitor are perpendicular to the mounting surface.
In the mounting substrate according to the present invention, the first internal electrode and the second internal electrode in the stacking direction are arranged on the first main surface side from the internal electrode arranged at a position closest to the first main surface. The dimension along the stacking direction to the surface of the external electrode and the second main surface from the internal electrode disposed at the position closest to the second main surface among the first internal electrode and the second internal electrode in the stacking direction The longest dimension among the dimensions along the stacking direction to the surface of the external electrode arranged on the side,
Of the first internal electrode and the second internal electrode in the width direction, the first internal electrode disposed at a position closest to the first side surface or the surface of the second internal electrode is disposed on the first side surface side. The first internal electrode or the second internal electrode disposed at a position closest to the second side surface of the first internal electrode or the second internal electrode in the width direction or the dimension along the width direction to the surface of the external electrode. The difference from the longest dimension among the dimensions along the width direction from the surface of the internal electrode to the surface of the external electrode disposed on the second side surface side is preferably 10 μm or less.
In the mounting board according to the present invention, a plurality of first internal electrodes and second internal electrodes are provided,
The dimension along the lamination direction of the first internal electrode and the second internal electrode is 0.3 μm or more and 1.0 μm or less, and the total number of the first internal electrode and the second internal electrode is 150 or more. The number is preferably 350 or less.
In the mounting substrate according to the present invention, the length of the multilayer ceramic capacitor in the length direction is preferably 0.2 mm or more and 0.7 mm or less.
In the mounting substrate according to the present invention, each of the first external electrode and the second external electrode has a base electrode disposed immediately above the laminate, and a plating layer disposed on the base electrode. The layer is preferably made of Au.
In the mounting substrate according to the present invention, the internal electrode is preferably an internal electrode containing Cu.
In the mounting substrate according to the present invention, the internal electrode is preferably an internal electrode containing Ni.

  In the mounting substrate according to the present invention, the first internal electrode and the second internal electrode in the stacking direction are arranged on the first main surface side from the internal electrode arranged at a position closest to the first main surface. The dimension along the stacking direction to the surface of the external electrode and the second main surface from the internal electrode disposed at the position closest to the second main surface among the first internal electrode and the second internal electrode in the stacking direction The longest dimension among the dimensions along the stacking direction to the surface of the external electrode arranged on the side is 40 μm or less, and further, the first side surface of the first internal electrode and the second internal electrode in the width direction In the dimension or width direction along the width direction from the surface of the first internal electrode or the second internal electrode disposed closest to the surface to the surface of the external electrode disposed on the first side surface side. Internal electrode or second Along the width direction from the surface of the first internal electrode or the second internal electrode arranged closest to the second side surface of the internal electrodes to the surface of the external electrode arranged on the second side surface side The longest dimension is 40 μm or less.

  According to the present invention, it is possible to obtain a mounting board on which a multilayer ceramic capacitor having a small change in insertion loss characteristics due to a difference in mounting posture is mounted.

  The above-described object, other objects, features, and advantages of the present invention will become more apparent from the following description of embodiments for carrying out the invention with reference to the drawings.

It is a perspective view which shows an example of the multilayer ceramic capacitor used for the mounting substrate concerning this invention. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along line II-II. FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 1. FIG. 2 is an illustrative view showing one process for manufacturing the multilayer ceramic capacitor shown in FIG. 1. FIG. 8 is an illustrative view showing another process for manufacturing the multilayer ceramic capacitor shown in FIG. 1. It is a perspective view which shows the multilayer chip for manufacturing the multilayer ceramic capacitor shown in FIG. FIG. 10 is a perspective view showing still another process for manufacturing the multilayer ceramic capacitor shown in FIG. 1. FIG. 2 is a cross-sectional view of the mounting substrate when internal electrodes of the multilayer ceramic capacitor shown in FIG. 1 are parallel to the mounting surface. FIG. 2 is a cross-sectional view of the mounting substrate when internal electrodes of the multilayer ceramic capacitor shown in FIG. 1 are perpendicular to the mounting surface. FIG. 10 is a circuit diagram of each mounting board shown in FIGS. 8 and 9. The electron micrograph image of the cross section of an example of the multilayer ceramic capacitor used for the mounting substrate concerning this invention is shown. The electron micrograph image of the cross section of an example of the multilayer ceramic capacitor used for the conventional mounting board | substrate is shown.

  As shown in FIGS. 1, 2, and 3, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped multilayer body 12, for example. The stacked body 12 includes a plurality of stacked dielectric layers 14 and a plurality of internal electrodes 16. Furthermore, the laminate 12 includes a first main surface 12a and a second main surface 12b that are opposed to the lamination direction x, and a first side surface 12c and a second side surface that are opposed to the width direction y orthogonal to the lamination direction x. 12d, and a first end surface 12e and a second end surface 12f that are opposed to a length direction z orthogonal to the stacking direction x and the width direction y. The laminated body 12 is preferably rounded at corners and ridge lines.

As a dielectric material of the dielectric layer 14 of the multilayer body 12, for example, a dielectric ceramic containing a component such as BaTiO ₃ , CaTiO ₃ , SrTiO _3, or CaZrO ₃ can be used. Moreover, you may use what added compounds and rare earth element compounds, such as a Mn compound, Mg compound, Ca compound, Fe compound, Cr compound, Co compound, or Ni compound, to these components, for example. Moreover, it is preferable that the dimension of the lamination direction x of one dielectric material layer 14 is 0.5 micrometer or more and 10 micrometers or less, for example.

As shown in FIGS. 2 and 3, the multilayer body 12 includes, as the plurality of internal electrodes 16, for example, a plurality of first internal electrodes 16 a and a plurality of second internal electrodes 16 b having a substantially rectangular shape. The plurality of first internal electrodes 16 a and the plurality of second internal electrodes 16 b are embedded so as to be alternately arranged at equal intervals along the stacking direction x of the stacked body 12.
One end portion of the first internal electrode 16 a has an exposed surface 18 a exposed at the first end surface 12 e of the multilayer body 12. One end portion of the second internal electrode 16 b has an exposed surface 18 b exposed at the second end surface 12 f of the multilayer body 12. Specifically, the exposed surface 18 a at one end of the first internal electrode 16 a is exposed at the first end surface 12 e of the multilayer body 12. Further, the exposed surface 18 b at one end of the second internal electrode 16 b is exposed at the second end surface 12 f of the multilayer body 12.
Further, the first internal electrode 16a and the second internal electrode 16b are parallel to the first main surface 12a and the second main surface 12b of the multilayer body 12, respectively. Further, the first internal electrode 16 a and the second internal electrode 16 b are opposed to each other with the dielectric layer 14 in the stacking direction x of the stacked body 12.
The dimension along the individual stacking direction x of the first internal electrode 16a and the second internal electrode 16b is preferably, for example, 0.3 μm or more and 1.0 μm or less.
The total number of the first internal electrodes 16a and the second internal electrodes 16b is preferably 150 or more and 350 or less.
The first internal electrode 16a and the second internal electrode 16b are each made of, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy such as an Ag—Pd alloy containing one of these metals. Can be configured. The first internal electrode 16a and the second internal electrode 16b are each preferably an internal electrode containing Cu or an internal electrode containing Ni.
Further, each of the first internal electrode 16 a and the second internal electrode 16 b may further include dielectric particles having the same composition system as the ceramic contained in the dielectric layer 14.
In the multilayer body 12, the first internal electrode is disposed between the first internal electrode 16 a ′ closest to the first main surface 12 a and the first main surface 12 a among the plurality of first internal electrodes 16. Similarly to 16a, an auxiliary electrode 17a exposed on the first end face 12e may be formed. Furthermore, in the multilayer body 12, the second internal electrode is disposed between the second internal electrode 16 b ′ closest to the second main surface 12 b and the second main surface 12 b among the plurality of second internal electrodes 16 b. Similarly to 16b, an auxiliary electrode 17b exposed on the second end face 12f may be formed.

External electrodes 20 are formed on the first end surface 12 e side and the second end surface 12 f side of the multilayer body 12. The external electrode 20 includes a first external electrode 20a and a second external electrode 20b.
A first external electrode 20 a is formed on the first end surface 12 e side of the multilayer body 12. The first external electrode 20a covers the first end surface 12e of the multilayer body 12, extends from the first end surface 12e, and extends from the first main surface 12a, the second main surface 12b, the first side surface 12c, and the first side surface 12c. 2 to cover a part of the side surface 12d. In this case, the first external electrode 20a is electrically connected to the exposed surface 18a of the first internal electrode 16a. Furthermore, when the auxiliary electrode 17a is formed, the first external electrode 20a is also electrically connected to the auxiliary electrode 17a. The external electrode 20a may not be connected to the auxiliary electrode 17a.
A second external electrode 20 b is formed on the second end face 12 f side of the multilayer body 12. The second external electrode 20b covers the second end surface 12f of the multilayer body 12, extends from the second end surface 12f, and extends from the first main surface 12a, the second main surface 12b, the first side surface 12c, and the first side surface 12c. 2 to cover a part of the side surface 12d. In this case, the second external electrode 20b is electrically connected to the exposed surface 18b of the second internal electrode 16b. Furthermore, the second external electrode 20b is also electrically connected to the auxiliary electrode 17b when the auxiliary electrode 17b is formed. The external electrode 20b may not be connected to the auxiliary electrode 17b.

  The first external electrode 20a includes a base electrode 22a and a plating layer 24a in this order from the laminated body 12 side. Similarly, the second external electrode 20b includes a base electrode 22b and a plating layer 24b in this order from the stacked body 12 side.

Each of the base electrodes 22a and 22b includes at least one layer selected from a baking layer and the like.
The baking layer includes glass made of Si, and further includes at least one selected from Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, and the like as a metal. The baking layer may be composed of a plurality of layers. The baking layer is obtained by applying a conductive paste containing glass and metal to the laminated body 12 and baking it. The baking layer may be fired at the same time as the internal electrode 16, or is burned after baking the internal electrode 16. It may be.
Each of the base electrodes 22a and 22b preferably has a thickness of the thickest portion of 25 μm or more and 45 μm or less.

The plating layers 24a and 24b include at least one selected from Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, and the like, for example.
When the plating layers 24a and 24b are made of Au, mounting with a conductive adhesive is possible, and the bondability of wire bonding is improved, which is preferable.
Each of the plating layers 24a and 24b may be formed of a plurality of layers. In this case, each of the plating layers 24a and 24b preferably has a two-layer structure having a Ni plating layer as a lower layer and a Sn plating layer as an upper layer.

  The multilayer ceramic capacitor 10 has, for example, a length L as a dimension in the length direction z of 0.6 mm, a width W as a dimension in the width direction y of 0.3 mm, and a thickness T as a dimension in the stack direction x of 0. .3 mm rectangular parallelepiped. The dimension in the length direction z of the multilayer ceramic capacitor 10 is preferably 0.2 mm or more and 0.7 mm or less. Each dimension includes a dimensional tolerance of ± 0.03 mm.

  In the multilayer ceramic capacitor 10, the first internal electrode 16 a and the second internal electrode 16 b are layered, and the stacking direction connecting the first main surface 12 a and the second main surface 12 b of the multilayer body 12. It is laminated on x.

  Next, an example of a method for manufacturing the above-described multilayer ceramic capacitor 10 will be described.

  First, a ceramic green sheet 30 containing a ceramic material for constituting the dielectric layer 14 of the laminate 12 is prepared.

  Next, as shown in FIG. 4, a conductive paste 32 is formed on the ceramic green sheet 30 by printing a conductive paste to form internal electrodes and auxiliary electrodes in a strip shape at regular intervals. In addition, the printing method of an electrically conductive paste can be performed by various printing methods, such as a screen printing method and a gravure printing method, for example.

  First, a plurality of ceramic green sheets 30 on which the conductive pattern 32 is not formed are stacked. Next, as shown in FIGS. 5A and 5B, the plurality of ceramic green sheets 30 on which the conductive patterns 32 are formed are formed on the plurality of ceramic green sheets 30 on which the conductive patterns 32 serving as internal electrodes are formed. 30 are stacked at a constant pitch. Finally, a plurality of ceramic green sheets 30 on which the conductive pattern 32 is not formed are stacked, and pressed in the stacking direction by means such as isostatic pressing to produce a stacked block. Note that the ceramic green sheet 30 on which the conductive pattern 32 serving as the auxiliary electrode is formed and the ceramic green sheet 30 on which the conductive pattern 30 serving as the internal electrode immediately inside thereof are laminated without shifting.

  Then, the laminated block is cut along a virtual line 34 shown in FIGS. 5A and 5B to form the raw laminated chip 36 shown in FIG. 6 from the laminated block. The cutting of the laminated block can be performed by dicing or pressing. Here, since the conductive pattern 32 is cut at a position where the surface of the internal electrode 16 is exposed in the width direction y, the end portions in the width direction y of the internal electrode 16 are aligned in the stacking direction x. The surfaces exposed in the width direction y of the auxiliary electrodes 17a and 17b are also aligned with the surfaces exposed in the width direction y of the internal electrodes 16 in the stacking direction x.

As shown in FIG. 6, conductive patterns 32 serving as internal electrodes and auxiliary electrodes are exposed on both side surfaces of the multilayer chip 36. Therefore, as shown in FIG. 7, both side surfaces of the multilayer chip 36 are covered with ceramic green sheets 38 serving as dielectrics so as to cover the conductive patterns 32 exposed on both side surfaces of the multilayer chip 36. Instead, a ceramic slurry serving as a dielectric may be applied to both side surfaces of the multilayer chip 36. The sheet covering both side surfaces of the multilayer chip 36 may be covered with a sheet that can maintain insulation other than the dielectric, as long as the internal electrodes are not exposed to the atmosphere.
After that, the laminated chip 36 that covers the conductive pattern 32 may be rounded at the corners and the ridge lines by barrel polishing or the like.

  Then, the raw multilayer chip 36 is fired. In this firing step, the dielectric layer 14, the first internal electrode 16a, the second internal electrode 16b, and the auxiliary electrodes 17a and 17b are fired. The firing temperature can be appropriately set depending on the type of ceramic material and conductive paste used. The firing temperature can be, for example, 900 ° C. or higher and 1300 ° C. or lower.

  Then, a conductive paste is applied to both ends of the fired laminated chip, that is, to both ends of the laminated body 12 by a method such as dipping.

  Next, the conductive paste applied to the laminate 12 is dried with hot air, for example, at 60 ° C. or higher and 180 ° C. or lower for 10 minutes.

  Thereafter, the dried conductive paste is baked to form the baking layers for the base electrodes 22a and 22b.

  Then, a plating layer 24a is formed on the base electrode 22a by electrolytic plating, and further, a plating layer 24b is formed on the base electrode 22b.

  The multilayer ceramic capacitor 10 is manufactured as described above.

  Next, the mounting substrate 100A on which the multilayer ceramic capacitor 10 shown in FIG. 1 is mounted will be described.

  FIG. 8 is a cross-sectional view of the mounting substrate 100A when parallel to the mounting surface on which the internal electrodes 16 of the multilayer ceramic capacitor 10 shown in FIG. 1 are mounted.

  A mounting substrate 100 </ b> A illustrated in FIG. 8 includes a base substrate 102. On one main surface of the base substrate 102, the output electrode 104 and the input electrode 106 are formed at substantially the same interval as the interval between the first external electrode 20 a and the second external electrode 20 b of the multilayer ceramic capacitor 10.

  The output electrode 104 is an electrode that outputs a signal including a frequency region of 10 GHz or more. Therefore, for example, an output terminal of a trans-impedance amplifier (not shown) mounted on the base substrate 102 is electrically connected to the output electrode 104 via a via-hole conductor formed on the base substrate 102, for example. Is done. The output from the transimpedance amplifier is 60 GHz or less, and a signal including a frequency in the low frequency region to the high frequency region flows.

  The input electrode 106 is an electrode for inputting a signal having a frequency in the frequency region of 10 GHz or more. Therefore, for example, an input end of an IC (not shown) mounted on the base substrate 102 is electrically connected to the input electrode 106 via, for example, a via hole conductor formed on the base substrate 102.

A multilayer ceramic capacitor 10 as a coupling capacitor is connected to the output electrode 104 and the input electrode 106 in order to input a signal output from the trans-impedance amplifier to the IC. In this case, the second external electrode 20 b of the multilayer ceramic capacitor 10 is electrically connected to the output electrode 104 by the solder fret 108. Further, the first external electrode 20 a of the multilayer ceramic capacitor 10 is electrically connected to the input electrode 106 by a solder fret 110.
In the mounting substrate 100A shown in FIG. 8, the multilayer ceramic capacitor 10 is mounted so that the internal electrodes 16 are parallel to the mounting surface. In this case, the multilayer ceramic capacitor 10 is mounted such that the second main surface 12 b of the multilayer body 12 faces the mounting surface of the base substrate 102.

  FIG. 9 is a cross-sectional view of the mounting substrate 100B in a case perpendicular to the mounting surface on which the internal electrodes 16 of the multilayer ceramic capacitor 10 shown in FIG. 1 are mounted.

The mounting board 100B shown in FIG. 9 differs from the mounting board 100A shown in FIG. 8 in the mounting direction of the multilayer ceramic capacitor 10.
In the mounting substrate 100B shown in FIG. 9, the multilayer ceramic capacitor 10 is mounted such that the internal electrodes 16 are perpendicular to the mounting surface. In this case, the multilayer ceramic capacitor 10 is mounted such that the second side surface 12 d of the multilayer body 12 faces the mounting surface of the base substrate 102.

  The mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9 each have the circuit shown in FIG.

In the multilayer ceramic capacitor 10 mounted on the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9, the first main surface 12a, the second main surface 12b, the first side surface 12c and the second main surface 12c, respectively. The external electrode 20 formed on the side surface 12d is disposed at a position closest to the first main surface 12a among the plurality of internal electrodes 16 in the stacking direction x when viewed in a cross section including the stacking direction x and the width direction y. The internal electrode 16 is arranged so that the longest dimension among the dimensions along the stacking direction x from the first internal electrode 16a ′ to the surface of the external electrode 20 on the first main surface 12a side is 40 μm or less. Has been.
Similarly, in the stacking direction x, from the second internal electrode 16b ′ disposed closest to the second main surface 12b among the plurality of internal electrodes 16, to the surface of the external electrode 20 on the second main surface 12b side. The internal electrodes 16 are arranged so that the longest dimension among the dimensions along the stacking direction x is 40 μm or less. In addition, the width direction y from the surface of the internal electrode 16 disposed closest to the first side surface 12c among the plurality of internal electrodes 16 in the width direction y to the surface of the external electrode 20 on the first side surface 12c side. The internal electrode 16 is arranged so that the longest dimension among the dimensions along the line is 40 μm or less. Similarly, the width direction y from the surface of the internal electrode 16 disposed at a position closest to the second side surface 12d among the plurality of internal electrodes 16 in the width direction y to the surface of the external electrode 20 on the second side surface 12d side. The internal electrodes 16 are arranged so that the longest dimension among the dimensions along the line is 40 μm or less.
That is, as shown in FIG. 8, for example, the internal electrode 16 is arranged so that the dimension H1 along the stacking direction x between the internal electrode 16 and the surface of the external electrode 20 is 40 μm or less. As shown in FIG. 9, for example, the internal electrode 16 is arranged so that the dimension H2 along the width direction y between the internal electrode 16 and the surface of the external electrode 20 is 40 μm or less. In addition, when the auxiliary electrode is formed, it is set as the distance from the auxiliary electrode.
Thus, the path through which signals from the output electrode 104 and the multilayer ceramic capacitor 10 arranged on the mounting board 100A or the mounting board 100B flow and the path through which signals from the multilayer ceramic capacitor 10 to the input electrode 106 flow can be shortened. Therefore, the equivalent series inductance can be lowered. This appears remarkably when the frequency of the signal is 10 GHz or higher, and becomes more remarkable when the frequency is 20 GHz or higher.
Here, the external electrode 20 may include a base electrode and a plating layer disposed on the base electrode, but the dimension and distance to the surface of the external electrode 20 may be Sn plating layers that are melted by solder. Is not included.
In order to obtain the dimensions and distances as described above, the thickness of the ceramic green sheets 30 on which the internal electrodes are not formed, the number of stacked layers, the thickness of the ceramic green sheets 38, and the like may be adjusted.
Therefore, the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9 are each a mounting substrate on which the multilayer ceramic capacitor 10 with little change in insertion loss characteristics is mounted.

Here, an example of the multilayer ceramic capacitor used for the mounting substrate according to the present invention will be compared with an example of the multilayer ceramic capacitor used for the conventional mounting substrate.
FIG. 11 shows a photographic image of a cross section of an example of a multilayer ceramic capacitor used in the mounting substrate according to the present invention, and FIG. 12 shows an optical microscope of a cross section of an example of the multilayer ceramic capacitor used in the conventional mounting substrate. Shows a photographic image.
11 and 12, the outermost white portion indicates the external electrode, the white portion inside the external electrode indicates the outer shell of the laminate, and the multilayer white portion inside the laminate indicates the internal electrode. The other gray part represents the dielectric layer.
As is clear from FIGS. 11 and 12, the example of the multilayer ceramic capacitor used for the mounting board according to the present invention has the internal electrode as the external electrode than the example of the multilayer ceramic capacitor used for the conventional mounting board. It turns out that it forms closely.

In the mounting substrate 100A shown in FIG. 8, the flowing signal has a wide frequency up to 60 GHz. In particular, the effect of the present invention is achieved at 10 GHz or higher, and the higher effect is achieved at 20 GHz or higher. In FIG. 8, arrows indicate the flow of signals. The effect of the present invention is achieved when the signal is 10 GHz or higher, but becomes more prominent at 20 GHz or higher.
In the mounting substrate 100A shown in FIG. 8, in particular, the total value of the thickness of the external electrode 20 on the second main surface 12b side and the distance between the internal electrode 16 and the external electrode 20 on the second main surface 12b side is Since it is 40 micrometers or less, an equivalent series inductance can be suppressed.

Also in the mounting substrate 100B shown in FIG. 9, like the mounting substrate 100A shown in FIG. 8, the flowing signal has a wide frequency up to 60 GHz, particularly the effects of the present invention at 10 GHz or more, and even higher effects at 20 GHz or more. Play. In FIG. 9, arrows indicate the flow of signals. The effect of the present invention is achieved when the signal is 10 GHz or higher, but becomes more prominent at 20 GHz or higher.
In the mounting substrate 100B shown in FIG. 9, in particular, the total value of the thickness of the external electrode 20 on the second side surface 12d side and the distance between the end of the internal electrode 16 on the second side surface 12d side and the external electrode 20 is the most. Therefore, the equivalent series inductance can be suppressed.

Furthermore, in the mounting substrate 100B shown in FIG. 9, the surface in the width direction y of the internal electrode 16 has a thickness of 0 μm or more and 2 μm or less from the side surface of the multilayer body 12 when the portion of the dielectric layer 14 made of the ceramic green sheet 38 is removed. The surface of the internal electrode 16 in the width direction y is substantially aligned in the stacking direction x. In order to adjust the distance from the surface in the width direction y of the internal electrode 16 and the side surface of the multilayer body 12, the thickness of the ceramic green sheet 38 and the like may be adjusted.
Therefore, as shown in FIG. 9, when the internal electrode 16 is arranged perpendicular to the mounting surface, the signal in the high frequency region passes mainly near the surface in the width direction y of the internal electrode 16, but in the stacking direction x. Since they are almost uniform, variation in equivalent series inductance between the multilayer ceramic capacitors 10 can be suppressed. Therefore, variations in insertion loss characteristics can be suppressed.
That is, in the conventional mounting substrate, a general multilayer ceramic capacitor is used, but in such a general multilayer ceramic capacitor, displacement occurs during stacking, and therefore the position of the surface in the width direction of the internal electrode is , And varies in the stacking direction x. The variation is difficult to control between the multilayer ceramic capacitors, and the equivalent series inductance differs between the multilayer ceramic capacitors. That is, if the surface in the width direction of the internal electrode varies in the stacking direction, the distance between the end portion in the width direction of the internal electrode through which a signal in the high frequency region passes and the mounting surface varies, and the equivalent series inductance is It will vary. Therefore, the insertion loss characteristic varies.
On the other hand, in the mounting substrate 100B shown in FIG. 9, since the end portions in the width direction y of the internal electrodes 12 are aligned in the stacking direction x, the equivalent series inductance is less likely to vary and the insertion loss characteristic is less likely to vary. This appears remarkably when the frequency of the signal is 10 GHz or higher, and becomes more remarkable when the frequency is 20 GHz or higher.

  11 and 12 again, the example of the multilayer ceramic capacitor used in the mounting substrate according to the present invention is larger in width of the internal electrode than the example of the multilayer ceramic capacitor used in the conventional mounting substrate. It can be seen that the ends in the direction are aligned in the stacking direction.

In the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9, the first internal electrode 16a ′ and the external electrode 20 on the first main surface 12a side when the multilayer ceramic capacitor is mounted parallel to the mounting surface. The longest dimension among the dimensions along the stacking direction x up to the surface of the first electrode, and the longest dimension among the dimensions along the stacking direction x from the second internal electrode 16b 'to the surface of the external electrode 20 on the second main surface 12b side. Long dimension, dimension along the width direction y from the surface of the internal electrode 16 disposed closest to the first side face 12c to the surface of the external electrode 20 on the first side face 12c side among the plurality of internal electrodes 16 The longest dimension and the longest dimension among the dimensions along the width direction y from the surface of the internal electrode 16 disposed closest to the second side surface 12d to the surface of the external electrode 20 on the second side surface 12d side Dimensions Since the dimensional difference is 10 μm or less, the equivalent series inductance can be lowered regardless of the direction in which the multilayer ceramic capacitor 10 is mounted, and a stable insertion loss characteristic can be obtained in a higher frequency region. Can do. This appears remarkably when the frequency of the signal is 10 GHz or higher, and becomes more remarkable when the frequency is 20 GHz or higher. Therefore, the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9 are each a mounting substrate on which the multilayer ceramic capacitor 10 with little change in insertion loss characteristics is mounted.
Here, the external electrode 20 may include a base electrode and a plating layer disposed on the base electrode, but the dimension up to the surface of the external electrode 20 includes a Sn plating layer that is melted by solder. Not.
In order to obtain the difference between the dimensions as described above, the thickness of the ceramic green sheets 30, the number of stacked layers, the thickness of the ceramic green sheets 38, and the like may be adjusted.

In the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9, the dimension of each of the plurality of internal electrodes 16 along the individual stacking direction x is 0.3 μm or more and 1.0 μm or less. The total number of 16 is preferably 150 or more and 350 or less.
When the dimension along the stacking direction x of the internal electrodes 16 is larger than 1.0 μm, it is necessary to reduce the total number of the internal electrodes 16 in order to suppress the increase in the size of the multilayer ceramic capacitor 10, and the capacitance decreases. . When the capacitance decreases, it becomes difficult for high-frequency signals to pass through. On the contrary, the fact that the dimension along the stacking direction x of the internal electrode 16 is smaller than 0.3 μm means that the area covering the dielectric layer 14 of the internal electrode 16 is small, and there is a path through which high-frequency signals pass. That is, the equivalent series resistance increases. When the equivalent series resistance increases, it becomes difficult for signals in the high frequency region to pass.
Further, if the total number of internal electrodes 16 exceeds 350, an increase in the size of the multilayer ceramic capacitor 10 cannot be suppressed. On the contrary, when the total number of the internal electrodes 16 is less than 150, the electrostatic capacity is lowered, and high-frequency signals are difficult to pass.
In the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9, the insertion loss is determined by a composite factor mainly including an equivalent series inductance and an equivalent series resistance. For this reason, the dimension along the individual stacking direction x of the plurality of internal electrodes 16 is set to 0.3 μm or more and 1.0 μm or less, and the total number of the plurality of internal electrodes 16 is set to 150 or more and 350 or less. It can suppress that resistance becomes high. In the high frequency region, the equivalent series resistance affects the insertion loss, and a reduction in insertion loss can be suppressed by keeping the equivalent series resistance in the high frequency region low.

In the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9, the length L which is the dimension in the length direction z of the multilayer ceramic capacitor 10 affects the insertion loss. As the dimension in the length direction z of the multilayer ceramic capacitor 10 becomes shorter, the equivalent series inductance decreases, and therefore the insertion loss tends to decrease. Therefore, the dimension in the length direction z of the multilayer ceramic capacitor 10 is preferably 0.6 mm or less. If this dimension exceeds 0.6 mm, the path through which the signal passes becomes longer and the equivalent series inductance increases.
In the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9, when the dimension in the longitudinal direction z of the multilayer ceramic capacitor 10 is 0.2 mm or more and 0.7 mm or less, a smaller size and a wider bandwidth are obtained. A ceramic capacitor 10 can be mounted.
The dimension of the multilayer ceramic capacitor 10 in the length direction z includes the thickness of the external electrode 20.

  In the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9, the first external electrode 20a is disposed immediately above the stacked body 12, and the plating layer 24a is disposed on the underlying electrode 22a. Have The second external electrode 20b has a base electrode 22b disposed immediately above the laminate 12 and a plating layer 24b disposed on the base electrode 22b. When the plating layers 24a and 24b are made of Au, the multilayer ceramic capacitor 10 can be mounted with a conductive adhesive and can also be mounted with wire bonding.

  In the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9, when the internal electrode 16 is an internal electrode containing Cu, the insertion loss can be reduced and the frequency characteristics are good in the high frequency region. .

  In the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9, when the internal electrode 16 is an internal electrode containing Ni, since Ni has a high melting point, when the multilayer chip is fired, The degree of freedom in selecting the dielectric material is increased.

In the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9, the dimensions of the internal electrodes 16 in the stacking direction x are substantially uniform in the width direction y. Specifically, if the portion from the end in the width direction y of the internal electrode 16 to the portion inside the 5 μm width direction y is the end portion 16c of the internal electrode 16 (see FIG. 3), the end of the internal electrode 16 In the portion 16c, the difference between the dimension in the stacking direction x inside the width direction y and the dimension in the stacking direction x of the central portion 16d (see FIG. 3) of the internal electrode 16 in the width direction y is the stacking direction x of the central portion 16d. It is within ± 5% based on the dimension at.
As described above, when the internal electrode 16 is disposed in a direction perpendicular to the mounting surface, the high frequency component passes through the end portion 16 c of the internal electrode 16.
In general, in a multilayer ceramic capacitor, the ratio of covering the dielectric layer of the internal electrode at the center in the width direction of the internal electrode is higher than that of the end portion in the width direction of the internal electrode.
However, the thickness of the internal electrode 16 is substantially uniform as in the multilayer ceramic capacitor 10 used for the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. The ratio of covering the dielectric layer 14 is substantially constant, and the ratio of covering the dielectric layer 14 of the internal electrode 16 also at the end portion 16c is high. That is, the equivalent series resistance is reduced at the end portion 16c through which a signal in the high frequency region easily passes, and a reduction in insertion loss in the high frequency region can be suppressed.
When the total number of internal electrodes 16 is less than 150, especially when the internal electrodes 16 are arranged in the vertical direction, the number of internal electrodes 16 through which signals in the high frequency region can pass is reduced, and insertion in the high frequency region is performed. Loss increases.

  The capacitance of the multilayer ceramic capacitor 10 used for the mounting substrate 100A shown in FIG. 8 and the mounting substrate 100B shown in FIG. 9 is preferably 0.1 μF or more. When the capacitance of the multilayer ceramic capacitor 10 is less than 0.1 μF, it becomes difficult for signals in the low frequency region to pass through. Note that when the capacitance of the multilayer ceramic capacitor 10 is larger than 1 μF, the number of internal electrodes is increased, so that the equivalent series resistance can be further reduced, and since the capacitance is large, the low frequency Since it becomes easy to pass a signal in a region and it is easy to apply to a wide band, it is more preferable than 0.1 μF or more. The capacitance is the capacitance at a temperature of 25 ° C. according to the EIA standard.

The number of the internal electrodes 16 and the dimension in the stacking direction x in the above are polished so that the cross section including the width direction y and the stacking direction x is exposed at the center in the length direction z of the stacked body 12. Is exposed and measured with an optical microscope.
In the measurement, the surface treatment is performed so that the internal electrode 16 is not polished. Further, when measuring the dimension of the internal electrode 16 in the stacking direction x, a portion where the internal electrode 16 is missing is excluded from the measurement. Here, the dimension of the internal electrode 16 in the stacking direction x means that five measurement points are uniformly extracted in the width direction y and five layers are extracted from each layer in the stacking direction x, and the average value thereof is calculated. The dimension in the stacking direction x.
The number of internal electrodes 16 is determined by measuring the number of internal electrodes 16 exposed in the cross section. Note that the upper and lower auxiliary electrodes 17 a and 17 b are not included in the number of internal electrodes 16.
Other dimensions and distances can be confirmed by polishing the mounted multilayer ceramic capacitor 10 and the base substrate 102 together and observing the cross section with an optical microscope.

(Experimental example)
The mounting board of Example, the mounting board of Comparative Example 1, the mounting board of Comparative Example 2, and the mounting board of Comparative Example 3 were respectively prepared.
In the embodiment, as shown in FIG. 8, a mounting substrate in which the internal electrodes of the multilayer ceramic capacitor are arranged in parallel to the mounting surface, and the internal electrodes of the multilayer ceramic capacitor as shown in FIG. 9 are perpendicular to the mounting surface. The mounted substrate was arranged.
In Comparative Example 1, a mounting substrate in which the internal electrodes of the multilayer ceramic capacitor were arranged in parallel to the mounting surface was created.
In Comparative Example 2, a mounting substrate in which the internal electrodes of the multilayer ceramic capacitor were arranged perpendicular to the mounting surface was created.
In Comparative Example 3, a mounting substrate in which the internal electrodes of the multilayer ceramic capacitor were arranged in parallel to the mounting surface and a mounting substrate in which the internal electrodes of the multilayer ceramic capacitor were disposed perpendicular to the mounting surface were prepared.
Table 1 shows the size, capacitance, dimension in the width direction, and dimension in the stacking direction of each multilayer ceramic capacitor used in each mounting substrate of the example, comparative example 1, comparative example 2, and comparative example 3.

Here, the dimension in the width direction represents the distance from the end in the width direction of the internal electrode closest to the electrode formed on the base substrate to the surface of the external electrode in the width direction of the multilayer ceramic capacitor. The internal electrode does not include an auxiliary electrode. The distance to the surface of the external electrode refers to the distance to the surface of the base electrode of the external electrode and does not include the plating layer.
The dimension in the stacking direction represents the distance from the internal electrode closest to the electrode formed on the base substrate to the surface of the external electrode in the stacking direction of the multilayer ceramic capacitor. Again, the internal electrodes do not include auxiliary electrodes. The distance to the surface of the external electrode refers to the distance to the surface of the base electrode of the external electrode and does not include the plating layer.

And about each mounting board | substrate, the insertion loss characteristic with respect to a signal frequency was measured using the high frequency probe and the network analyzer. In this case, gain (dB) at each frequency of 10 GHz, 20 GHz, 30 GHz, and 35 GHz was measured as insertion loss characteristics. Table 1 also shows these measurement results. In addition, as a measurement result of an Example, the measurement result of the smaller one of the measurement results of two types of mounting substrates in which the arrangement of the internal electrodes is different is shown. Moreover, as a measurement result of the comparative example 3, the measurement result of the larger one of the measurement results of two types of mounting boards having different arrangements of internal electrodes is shown.
Regarding the evaluation of the measurement results shown in Table 1, “x” indicates that the insertion loss characteristic is greater than 0.5 dB, regardless of whether the internal electrode is perpendicular to or parallel to the mounting surface, and 0.5 dB or less. The case of “で” is indicated by “◯”. The determination criterion of 0.5 dB depends on the usage status of the mounting board.
From the measurement results and evaluation shown in Table 1, any of the mounting boards of Comparative Example 1, Comparative Example 2 and Comparative Example 3 has an insertion loss characteristic of 0.5 dB or less at all frequencies of 10 GHz, 20 GHz, 30 GHz and 35 GHz. Although not obtained, it can be seen that the mounting loss characteristics of 0.5 dB or less can be obtained at all frequencies of 10 GHz, 20 GHz, 30 GHz, and 35 GHz in the mounting substrate of the example.

  In the mounting substrates 100A and 100B described above, the multilayer ceramic capacitor 10 is mounted such that the second main surface 12b or the second side surface 12d of the multilayer body 12 faces the mounting surface of the base substrate 102. The multilayer ceramic capacitor 10 may be mounted such that the first main surface 12 a or the first side surface 12 c of the body 12 faces the mounting surface of the base substrate 102.

  In the mounting substrates 100A and 100B described above, the first external electrode 20a of the multilayer ceramic capacitor 10 is connected to the input electrode 106, and the second external electrode 20b is connected to the output electrode 104. The ten first external electrodes 20 a may be connected to the output electrode 104, and the second external electrode 20 b may be connected to the input electrode 106.

  Furthermore, in the above-described mounting boards 100A and 100B, one first internal electrode 16a and one second internal electrode 16b are disposed outside in the stacking direction x of the multilayer body 12 of the multilayer ceramic capacitor 10. However, the two first internal electrodes 16a may be arranged on the outside, or the two second internal electrodes 16b may be arranged on the outside.

  In the above-described embodiment, the mounting substrate on which the multilayer ceramic capacitor having a specific configuration is mounted has been described as an example. However, the configuration of the mounting substrate on which the multilayer ceramic capacitor according to the present invention is mounted is described in the claims. It may be arbitrarily changed within the scope of the configuration defined by.

  The mounting substrate according to the present invention is particularly preferably used as a mounting substrate on which a multilayer ceramic capacitor as a coupling capacitor is mounted.

DESCRIPTION OF SYMBOLS 10 Multilayer ceramic capacitor 12 Laminated body 12a 1st main surface 12b 2nd main surface 12c 1st side surface 12d 2nd side surface 12e 1st end surface 12f 2nd end surface 14 Dielectric layer 16 Internal electrode 16a 1st Internal electrode 16b Second internal electrode 16c End portion 16d Central portion 18a, 18b Exposed surface 20 External electrode 20a First external electrode 20b Second external electrode 22a, 22b Base electrode 24a, 24b Plating layer 30 Ceramic green sheet 32 Conductive Pattern 34 Virtual line 36 Multilayer chip 38 Ceramic green sheet 100A, 100B Mounting substrate 102 Base substrate 104 Output electrode 106 Input electrode 108, 110 Solder fillet H1 A dimension along the stacking direction between the internal electrode and the surface of the external electrode H2 Internal Between the electrode and the surface of the external electrode Dimension along the width direction

Claims (8)

Mounting board comprising: an output electrode that outputs a signal including a frequency region of 10 GHz or higher; an input electrode that inputs a signal including a frequency region of 10 GHz or higher; and the output ceramic electrode and a multilayer ceramic capacitor connected to the input electrode Because
The multilayer ceramic capacitor includes a rectangular parallelepiped laminate,
The stacked body includes a plurality of stacked dielectric layers and a plurality of internal electrodes, and further has a first main surface and a second main surface facing the stacking direction, and a width orthogonal to the stacking direction. A first side surface and a second side surface facing the direction, and a first end surface and a second end surface facing the length direction perpendicular to the laminating direction and the width direction,
The multilayer ceramic capacitor further includes:
A first covering the first end surface and extending from the first end surface and covering the first main surface, the second main surface, the first side surface and the second side surface External electrodes,
A second end surface covering the second end surface and extending from the second end surface and covering the first main surface, the second main surface, the first side surface and the second side surface; With external electrodes,
The plurality of internal electrodes have a first internal electrode connected to the first external electrode and a second internal electrode connected to the second external electrode,
When viewed in respective cross sections including the first external electrode and the second external electrode formed on the first main surface, the second main surface, the first side surface, and the second side surface ,
The external electrode disposed on the first main surface side from the internal electrode disposed closest to the first main surface among the first internal electrode and the second internal electrode in the stacking direction. From the internal electrode disposed at a position closest to the second main surface among the first internal electrode and the second internal electrode in the stacking direction. The longest dimension among the dimensions along the stacking direction to the surface of the external electrode disposed on the main surface side of 2 is 40 μm or less, and
From the surface of the first internal electrode or the second internal electrode disposed at a position closest to the first side surface of the first internal electrode and the second internal electrode in the width direction, The dimension along the width direction to the surface of the external electrode disposed on the side surface of the first side, or the closest to the second side surface of the first internal electrode or the second internal electrode in the width direction The longest dimension among the dimensions along the width direction from the surface of the first internal electrode or the second internal electrode arranged at a position to the surface of the external electrode arranged on the second side surface side Is a mounting substrate, characterized by being 40 μm or less. Mounting board comprising: an output electrode that outputs a signal including a frequency region of 10 GHz or higher; an input electrode that inputs a signal including a frequency region of 10 GHz or higher; and the output ceramic electrode and a multilayer ceramic capacitor connected to the input electrode Because
The multilayer ceramic capacitor includes a rectangular parallelepiped laminate,
The stacked body includes a plurality of stacked dielectric layers and a plurality of internal electrodes, and further has a first main surface and a second main surface facing the stacking direction, and a width orthogonal to the stacking direction. A first side surface and a second side surface facing the direction, and a first end surface and a second end surface facing the length direction perpendicular to the laminating direction and the width direction,
The multilayer ceramic capacitor further includes:
A first covering the first end surface and extending from the first end surface and covering the first main surface, the second main surface, the first side surface and the second side surface External electrodes,
A second end surface covering the second end surface and extending from the second end surface and covering the first main surface, the second main surface, the first side surface and the second side surface; With external electrodes,
The plurality of internal electrodes have a first internal electrode connected to the first external electrode and a second internal electrode connected to the second external electrode,
When viewed in respective cross sections including the first external electrode and the second external electrode formed on the first main surface, the second main surface, the first side surface, and the second side surface ,
The external electrode disposed on the first main surface side from the internal electrode disposed closest to the first main surface among the first internal electrode and the second internal electrode in the stacking direction. From the internal electrode disposed at a position closest to the second main surface among the first internal electrode and the second internal electrode in the stacking direction. The longest dimension among the dimensions along the stacking direction to the surface of the external electrode disposed on the main surface side of 2 is 40 μm or less, and
From the surface of the first internal electrode or the second internal electrode disposed at a position closest to the first side surface of the first internal electrode and the second internal electrode in the width direction, The dimension along the width direction to the surface of the external electrode disposed on the side surface of the first side, or the closest to the second side surface of the first internal electrode or the second internal electrode in the width direction The longest dimension among the dimensions along the width direction from the surface of the first internal electrode or the second internal electrode arranged at a position to the surface of the external electrode arranged on the second side surface side Is 40 μm or less,
The multilayer ceramic capacitor provided on the mounting substrate is:
A multilayer ceramic capacitor mounted such that the plurality of internal electrodes of the multilayer ceramic capacitor are parallel to a mounting surface;
A mounting substrate comprising: a multilayer ceramic capacitor mounted so that the plurality of internal electrodes of the multilayer ceramic capacitor are perpendicular to a mounting surface. The external electrode disposed on the first main surface side from the internal electrode disposed closest to the first main surface among the first internal electrode and the second internal electrode in the stacking direction. From the internal electrode disposed at a position closest to the second main surface among the first internal electrode and the second internal electrode in the stacking direction. The longest dimension among the dimensions along the laminating direction to the surface of the external electrode disposed on the main surface side of 2;
From the surface of the first internal electrode or the second internal electrode disposed at a position closest to the first side surface of the first internal electrode and the second internal electrode in the width direction, The dimension along the width direction to the surface of the external electrode disposed on the side surface of the first side, or the closest to the second side surface of the first internal electrode or the second internal electrode in the width direction The longest dimension among the dimensions along the width direction from the surface of the first internal electrode or the second internal electrode arranged at a position to the surface of the external electrode arranged on the second side surface side The mounting substrate according to claim 1, wherein a difference between the mounting board and the mounting board is 10 μm or less. A plurality of the first internal electrodes and the second internal electrodes are provided,
The dimension along the stacking direction of the first internal electrode and the second internal electrode is 0.3 μm or more and 1.0 μm or less, and the total number of the first internal electrode and the second internal electrode The mounting board according to claim 1, wherein the number is from 150 to 350.   The mounting substrate according to any one of claims 1 to 4, wherein a dimension of the multilayer ceramic capacitor in the length direction is 0.2 mm or more and 0.7 mm or less.   Each of the first external electrode and the second external electrode includes a base electrode disposed immediately above the laminate, and a plating layer disposed on the base electrode, and the plating layer includes: The mounting substrate according to claim 1, wherein the mounting substrate is made of Au.   The mounting substrate according to claim 1, wherein the internal electrode is an internal electrode containing Cu.   The mounting substrate according to claim 1, wherein the internal electrode is an internal electrode containing Ni.