JP2004296940A - Laminated capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce voltage fluctuation of the power for CPU by reducing effective inductance of a laminated capacitor to a great extent. <P>SOLUTION: An internal conductor 14 is disposed in a dielectric element, and an internal conductor 16 is disposed on the inner side of the internal conductor 14 beyond a ceramic layer 12A. The side length of the dielectric element along the laminating direction of the ceramic layer 12A is set longer than the side length of the dielectric element along the direction connecting between a pair of terminal electrodes. One terminal electrode is connected to, for example, the electrode of the CPU, while the other terminal electrode is connected to, for example, the ground side, so that each internal conductor 14, 16 acts as an electrode of the capacitor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer capacitor in which the effective inductance is significantly reduced, and is particularly suitable for a multilayer ceramic capacitor capable of reducing voltage fluctuation of a power supply for a CPU.
[0002]
[Prior art]
2. Description of the Related Art In recent years, CPUs (main processing units) used in information processing apparatuses have increased operating frequencies and significantly increased current consumption due to improvements in processing speed and higher integration. Along with this, the operating voltage has tended to decrease due to the reduction in power consumption. Therefore, in a power supply for supplying power to the CPU, a large current fluctuation occurs at a higher speed, and it has become very difficult to suppress a voltage fluctuation caused by the current fluctuation within an allowable value of the power supply.
[0003]
For this reason, as shown in FIG. 7, a multilayer capacitor 100 called a decoupling capacitor is connected to a power supply 102 and is frequently used for stabilizing the power supply. The current is supplied from the multilayer capacitor 100 to the CPU 104 by rapid charging and discharging at the time of high-speed and transient fluctuation of the current, so that the voltage fluctuation of the power supply 102 is suppressed.
[0004]
[Patent Document 1]
JP-A-10-261544 [Patent Document 2]
JP-A-11-288839 [Patent Document 3]
JP 09-148174 A [Patent Document 4]
Japanese Patent Laid-Open Publication No. 08-097070
[Problems to be solved by the invention]
However, as the operating frequency of today's CPUs has been further increased, the current fluctuation has become faster and larger. Therefore, as the equivalent series inductance (ESL) of the multilayer capacitor 100 itself shown in FIG. 7 itself becomes relatively large, the effective inductance becomes large. As a result, this equivalent series inductance is affected by the voltage fluctuation of the power supply. It has a big influence.
[0006]
That is, in the conventional multilayer capacitor 100 used in the power supply circuit of the CPU 104 shown in FIG. 7, since the ESL which is a parasitic component shown in the equivalent circuit in FIG. Thus, the ESL hinders the charging and discharging of the multilayer capacitor 100. For this reason, similarly to the above, the fluctuation of the voltage V of the power supply tends to be large as shown in FIG. 8, and it has become impossible to adapt to the future increase in the speed of the CPU.
[0007]
The reason for this is that the voltage fluctuation at the time of charging and discharging, which is a transition of current, is approximated by the following equation 1, and the level of ESL is related to the magnitude of the voltage fluctuation of the power supply.
dV = ESL · di / dt formula 1
Here, dV is a voltage fluctuation (V) during a transition, i is a current fluctuation amount (A), and t is a fluctuation time (second).
[0008]
Here, the appearance of a conventional capacitor adopting an existing measure for reducing ESL is shown in FIG. 9 and the internal structure is shown in FIG. 10, and the conventional multilayer capacitor 100 will be described below based on these drawings. In other words, the conventional multilayer capacitor 100 shown in FIG. 9 has a pair of ceramic layers 112A provided with two types of internal conductors 114 and 116 shown in FIG. The structure is such that the dielectric element body 112 is formed.
[0009]
In addition, these two types of internal conductors 114 and 116 are drawn out to two mutually facing side surfaces 112B and 112C of the dielectric element 112, and a terminal electrode 118 connected to the internal conductor 114 and an internal conductor Terminal electrodes 120 connected to 116 are provided on mutually facing side surfaces 112B and 112C of the multilayer capacitor 100 shown in FIG.
[0010]
In other words, as an existing measure for reducing the ESL, as shown in FIG. 9, the length of the side of the dielectric element 112 along the direction connecting the pair of terminal electrodes , 120 is considered to adopt a structure in which the length W of the side of the dielectric body 112 along the width direction is increased.
[0011]
This is because the magnitude of the ESL of the multilayer capacitor is based on the self-inductance of the internal conductors 114 and 116. Specifically, as shown in FIG. 10, the internal conductors 114 and 116 are formed wider and shorter, respectively, to reduce the distance from the terminal electrodes 118 and 120, thereby reducing the inductance of the internal conductors 114 and 116. To reduce the ESL.
[0012]
However, as shown in FIG. 11, the multilayer capacitor 100 shown in FIGS. 9 and 10 is mounted in such a manner that the ceramic layers 112A are stacked along the direction perpendicular to the surface of the multilayer substrate 122 (Z-axis direction). Therefore, the surfaces of the internal conductors 114 and 116 are horizontal with the surface of the multilayer substrate 122. For this reason, the distance from the land pattern 124, which is the conductor portion of the multilayer substrate 122, to the internal conductors 114 and 116 in the dielectric element 112 increases, and the area occupied by the current loop E increases. However, there is a disadvantage that the loop inductance increases and the effective inductance also increases accordingly.
[0013]
As described above, the factor that increases the voltage fluctuation of the power supply is not only the ESL of the capacitor itself but also the loop inductance. The sum of these ESL and the loop inductance greatly affects the voltage fluctuation of the power supply as an effective inductance. Needs to be reduced.
[0014]
On the other hand, a mounting structure shown in FIG. 12 was considered as a mounting structure for avoiding an increase in loop inductance. The mounting structure shown in this drawing is mounted so that the laminating direction is different from the structure shown in FIG. 11 by 90 degrees and the ceramic layer 112A is stacked in the Y-axis direction along the surface of the multilayer substrate 122. is there.
[0015]
In other words, the mounting structure is such that the surfaces of the internal conductors 114 and 116 are perpendicular to the surface of the multilayer substrate 122 on which the multilayer capacitor 100 is mounted. As a result, the current loop E is shortened. Is to reduce. However, even when such a mounting structure is used, the loop inductance cannot be sufficiently reduced, and the disadvantage that the effective inductance is large cannot be eliminated. Furthermore, in such a mounting structure, since the multilayer capacitor 100 is mounted in an unstable posture, reliable mounting is difficult.
The present invention has been made in view of the above circumstances, and has as its object to provide a multilayer capacitor capable of significantly reducing the effective inductance and reducing the voltage fluctuation of a power supply for a CPU.
[0016]
[Means for Solving the Problems]
A multilayer capacitor according to claim 1, wherein a dielectric element is formed in a rectangular parallelepiped shape by laminating dielectric layers;
Two types of internal conductors each arranged in a dielectric body while being separated by a dielectric layer,
A pair of terminal electrodes provided on two mutually facing side surfaces of the dielectric body and connected to any of the two types of internal conductors,
A multilayer capacitor having
The length of the side of the dielectric element along the stacking direction of the dielectric layer is longer than the length of the side of the dielectric element along the direction connecting a pair of terminal electrodes crossing the side along the stacking direction. It is also characterized by having been lengthened.
[0017]
According to the multilayer capacitor according to the first aspect, two types of internal conductors are arranged in the dielectric body formed by laminating the dielectric layers into a rectangular parallelepiped shape while being separated by the dielectric layers. A pair of terminal electrodes provided on two mutually facing side surfaces of the body body are respectively connected to any of the two types of internal conductors. For this reason, these two types of internal conductors, which are respectively connected to the terminal electrodes, are used as electrodes of the capacitors arranged in parallel while facing each other. Further, the length of the side of the dielectric element along the stacking direction of the dielectric layer is the length of the side of the dielectric element along the direction connecting a pair of terminal electrodes intersecting the side along the stacking direction. It is longer than the length.
[0018]
Therefore, the length of the side of the dielectric element along the stacking direction of the dielectric layers is longer than the length of the side of the dielectric element along the direction connecting the pair of terminal electrodes. When mounting the multilayer capacitor of the present invention on a substrate, the multilayer capacitor can be easily mounted in a form in which dielectric layers are stacked along the surface of the substrate. That is, it is easy to make the structure in which the surface of the internal conductor is perpendicular to the surface of the substrate on which the multilayer capacitor is mounted. As a result, the current loop is shortened, and as a result, the loop inductance is reduced.
[0019]
As described above, in the multilayer capacitor according to the present invention, the loop inductance is reduced, and the effective inductance is greatly reduced. As a result, according to the present invention, the oscillation of the voltage of the power supply can be reliably suppressed, and a multilayer capacitor optimal for the power supply of the CPU can be obtained.
[0020]
According to the multilayer capacitor according to the second aspect, in addition to the same configuration as the multilayer capacitor according to the first aspect, two types of internal conductors are provided with a lead portion that is drawn toward two mutually facing side surfaces of the dielectric body. Respectively, and one of the two types of internal conductors and one of the terminal electrodes are connected, and the other of the two types of internal conductors and the other one of the terminal electrodes are connected through these lead portions. It has a configuration of:
[0021]
Therefore, since the two types of internal conductors have the lead portions drawn out toward the two opposing side surfaces of the dielectric body, the internal conductors are respectively connected to the pair of terminal electrodes through the lead portions. Be connected. That is, according to the present invention, it is possible to reliably achieve the configuration of claim 1 in which the pair of terminal electrodes are provided on two mutually facing side surfaces of the dielectric element.
[0022]
According to the multilayer capacitor of the third aspect, in addition to the same configuration as the multilayer capacitor of the first and second aspects, there is a configuration in which two types of internal conductors are arranged in a plurality in the dielectric body. are doing. Therefore, by arranging a plurality of these two types of internal conductors in the dielectric body, respectively, the capacitance of the multilayer capacitor according to the present invention is increased.
[0023]
According to the multilayer capacitor of the fourth aspect, in addition to the same configuration as the multilayer capacitor of the first to third aspects, the length of the side of the dielectric element along the lamination direction of the dielectric layers is W. When the length of the side of the dielectric element along the direction connecting the pair of terminal electrodes is L, the L / W ratio is in the range of 0.5 to 0.8 and the surface of the circuit board is On the other hand, it has a configuration in which the surface of the internal conductor is arranged vertically. That is, from the measured values, the ESL value was reduced by disposing the inner conductor perpendicular to the substrate and setting the L / W ratio in the range of 0.5 to 0.8.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the multilayer capacitor according to the present invention will be described below with reference to the drawings. FIGS. 1 to 4 show a multilayer ceramic capacitor (hereinafter simply referred to as a multilayer capacitor) 10 which is a multilayer capacitor according to the present embodiment. As shown in these figures, a dielectric element 12 which is a rectangular parallelepiped sintered body obtained by firing a laminate obtained by laminating a plurality of ceramic green sheets which are dielectric sheets is used as a main part. A multilayer capacitor 10 is configured.
[0025]
As shown in FIG. 1, a planar internal conductor 14 is disposed at a predetermined position in the dielectric body 12, and a ceramic layer 12A serving as a dielectric layer in the dielectric body 12 On the inner side of the separated internal conductor 14, a similarly planar internal conductor 16 is arranged. Therefore, the inner conductor 14 and the inner conductor 16 are arranged in the dielectric body 12 so as to face each other while being separated by the ceramic layer 12A.
[0026]
That is, in the present embodiment, the internal conductors 14 and the internal conductors 16 are sequentially arranged in the dielectric element body 12 while the ceramic layer 12A, which is the fired dielectric sheet, is sandwiched between them. As shown in FIG. 1 and FIG. 3, these two layers of electrodes are repeated in the same order as described above, and about 100 sets of these sets are arranged on the inner side of the inner conductor 16.
[0027]
The centers of the internal conductors 14 and 16 are arranged at substantially the same position as the center of the dielectric body 12, and the vertical and horizontal dimensions of the internal conductors 14 and 16 are The length is smaller than the length of the side of the body 12. In addition, as the material of the internal conductors 14 and 16 each formed in a substantially rectangular shape, not only nickel, nickel alloy, copper, or copper alloy which is a base metal material can be considered, but also a material mainly containing these metals. Can be considered.
[0028]
Further, as shown in FIGS. 1 and 3, a lead portion 14B is drawn from the left side portion of the internal conductor 14 toward the left side surface 12C of the dielectric element body 12 over the entire width of the ceramic layer 12A. A lead portion 16B is drawn out from the right side portion of the internal conductor 16 toward the right side surface 12C of the dielectric body 12 with the entire width of the ceramic layer 12A.
[0029]
That is, the two types of internal conductors 14 and 16 have the lead portions 14B and 16B that are drawn out toward the two side surfaces 12C of the dielectric body 12 facing each other. As shown in FIG. 2, a terminal electrode 24 connected to the internal conductor 14 via a lead portion 14B is arranged on a left side surface 12C of the two opposing side surfaces 12C. On the right side surface 12C, a terminal electrode 26 connected to the internal conductor 16 via the lead portion 16B is arranged.
As described above, in the multilayer capacitor 10 of the present embodiment, the terminal electrodes 24 and 26 are respectively provided on the left and right two side surfaces 12C of the four side surfaces 12B and 12C of the dielectric element body 12 having a rectangular parallelepiped hexahedron shape. Will be placed.
[0030]
On the other hand, as shown in FIG. 2, the length W of the side of the dielectric body 12 along the laminating direction (Y-axis direction) of the ceramic layer 12A is a pair of terminal electrodes intersecting with the side along the laminating direction. The length is longer than the length L of the side of the dielectric element body 12 along the direction (X-axis direction) connecting the first and second 24 and 26. For example, in the present embodiment, the length L is 1.25 mm, and the length W is 2.0 mm.
[0031]
The terminal electrode 24 is connected to, for example, a CPU electrode, and the terminal electrode 26 is connected to, for example, a ground side so that each of the internal conductors 14 and 16 becomes an electrode of a capacitor. Matching terminal electrodes are used with opposite polarities. Specifically, the multilayer capacitor 10 is soldered while the internal conductors 14 and 16 are arranged vertically with respect to the multilayer substrate 122 shown in FIG. 4, and the land pattern 124 of the multilayer substrate 122 and these terminal electrodes 24 and 26 are formed. It is connected.
[0032]
Next, the operation of the multilayer capacitor 10 according to the present embodiment will be described.
According to the multilayer capacitor 10 according to the present embodiment, a plurality of dielectric sheets each serving as a ceramic layer 12A are laminated and sandwiched between the ceramic layers 12A in the dielectric element body 12 formed in a rectangular parallelepiped shape. It has a configuration in which two types of internal conductors 14 and 16 are arranged in the form. For this reason, these two types of internal conductors 14 and 16 are used as electrodes of capacitors arranged in parallel while facing each other.
[0033]
Further, the two types of internal conductors 14 and 16 have lead portions 14A and 16A, respectively, which are drawn out toward two opposing side surfaces 12C of the dielectric body 12, and the lead portions 14A and 16A are provided through these lead portions 14A and 16A. A pair of terminal electrodes 24 and 26 respectively connected to either of the two types of internal conductors 14 and 16 are provided on two mutually facing side surfaces 12C of the dielectric body 12.
[0034]
Further, a pair of terminal electrodes along a direction in which the length W of the side of the dielectric element body 12 along the laminating direction of the ceramic layer 12A (the Y-axis direction in FIG. 2) intersects the side along the laminating direction. The length is longer than the length L of the side of the dielectric body 12 along the direction (X-axis direction in FIG. 2) connecting between 24 and 26.
[0035]
Therefore, the length W of the side of the ceramic layer 12A along the stacking direction is longer than the length L of the side along the direction connecting the pair of terminal electrodes 24 and 26. When mounting the multilayer capacitor 10 on the multilayer substrate 122 shown in FIG. 4, the multilayer capacitor 10 is easily mounted in a form in which the ceramic layers 12A are stacked along the surface of the multilayer substrate 122. That is, in the present embodiment, the structure is such that the surfaces of the internal conductors 14 and 16 are perpendicular to the surface of the multilayer substrate 122 on which the multilayer capacitor 10 is mounted. As a result, the current loop is shortened, and as a result, the loop inductance is reduced.
[0036]
As described above, in the multilayer capacitor 10 according to the present embodiment, the loop inductance is reduced, and the effective inductance is significantly reduced. As a result, according to the present embodiment, the oscillation of the voltage of the power supply can be reliably suppressed, and the multilayer capacitor 10 optimal for the power supply of the CPU can be obtained. Further, in the present embodiment, since two types of internal conductors 14 and 16 are arranged in the dielectric element 12 in plural numbers, the capacitance of the multilayer capacitor 10 can be increased.
[0037]
Next, S21 characteristics of the following S parameters of each sample were measured using a network analyzer, and the attenuation characteristics of each sample were obtained. First, the contents of each sample will be described. That is, the multilayer capacitor shown in FIG. 9 is a conventional example, and the multilayer capacitor according to the embodiment shown in FIG. 2 is an example.
[0038]
Here, the constant of the equivalent circuit was calculated such that the measured value of the attenuation characteristic matched the attenuation of the equivalent circuit in the multilayer capacitor 100 shown in FIG. FIG. 5 shows a graph obtained by converting the parameters of S21 into impedance parameters. As a result, it can be seen from the impedance characteristic data of each sample that the impedance of the embodiment in the high frequency band of about 5 MHz or more is smaller than that of the conventional example. Therefore, it can be understood that this data shows that the high-frequency characteristics are improved in the embodiment. On the other hand, the calculated ESL was also significantly reduced to 215 pH in the example as compared with 474 pH in the conventional example, and it was confirmed that the effects of the present invention were also demonstrated by these values.
[0039]
Regarding the dimensions of each sample used here, the length W and the length L shown in FIGS. 9 and 2 were L = 1.25 mm and W = 2.0 mm in both the conventional example and the example. The capacitance of each sample used in the test was 9.2 F in the conventional example and 9.6 F in the example.
[0040]
Next, each sample was prepared by changing the value of the L / W ratio, which is the dimensional ratio between the length L and the length W, and the ESL value of each sample was obtained. The relationship between the value and the ESL value is shown in the graph of FIG. From the graph in this figure, it is conceivable that the internal conductors 14 and 16 are arranged perpendicular to the substrate and the value of the dimensional ratio L / W having a low ESL value is in the range of 0.5 to 0.8. .
[0041]
Although the multilayer capacitor 10 according to the above embodiment has a structure having two types of internal conductors, the number of layers is not limited to the number shown in the embodiment and may be larger.
[0042]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the multilayer capacitor which can reduce the voltage fluctuation of the power supply for CPUs greatly by reducing effective inductance significantly.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view of a multilayer capacitor according to an embodiment of the present invention.
FIG. 2 is a perspective view showing a multilayer capacitor according to one embodiment of the present invention.
FIG. 3 is a sectional view taken along line 3-3 of FIG. 2;
FIG. 4 is a cross-sectional view showing a mounting structure of the multilayer capacitor according to one embodiment of the present invention.
FIG. 5 is a diagram showing a graph representing impedance characteristics of each sample.
FIG. 6 is a graph showing a relationship between a value of L / W and a value of ESL.
FIG. 7 is a circuit diagram employing a conventional multilayer capacitor.
FIG. 8 is a graph showing a relationship between a current variation and a voltage variation in a circuit employing a conventional multilayer capacitor.
FIG. 9 is a perspective view showing a multilayer capacitor according to a conventional example.
FIG. 10 is an exploded perspective view showing a portion of an internal conductor of a multilayer capacitor according to a conventional example.
FIG. 11 is a sectional view showing a first mounting structure of a multilayer capacitor according to a conventional example.
FIG. 12 is a sectional view showing a second mounting structure of a multilayer capacitor according to a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Multilayer capacitor 12 Dielectric body 12B Side surface 12C Side surface 14 Internal conductor 16 Internal conductor 24 Terminal electrode 26 Terminal electrode

Claims (4)

A dielectric element formed by laminating dielectric layers into a rectangular parallelepiped shape, and two types of internal conductors respectively arranged in the dielectric element while being separated by the dielectric layer,
A pair of terminal electrodes provided on two mutually facing side surfaces of the dielectric body and connected to any of the two types of internal conductors,
A multilayer capacitor having
The length of the side of the dielectric element along the stacking direction of the dielectric layer is longer than the length of the side of the dielectric element along the direction connecting a pair of terminal electrodes crossing the side along the stacking direction. A multilayer capacitor characterized in that it has also been lengthened. Each of the two types of internal conductors has a lead portion that is drawn toward two mutually facing side surfaces of the dielectric element body,
Through these lead portions, one of the two types of internal conductors and one of the terminal electrodes are connected, and the other of the two types of internal conductors and the other one of the terminal electrodes are connected. The multilayer capacitor according to claim 1. The multilayer capacitor according to claim 1 or 2, wherein a plurality of two types of internal conductors are arranged in the dielectric body. When the length of the side of the dielectric element along the stacking direction of the dielectric layers is W, and the length of the side of the dielectric element along the direction connecting the pair of terminal electrodes is L, L / L The W ratio is set in a range of 0.5 to 0.8, and the surface of the internal conductor is arranged perpendicular to the surface of the circuit board. Multilayer capacitors.

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