KR100867503B1 - Multilayer Chip Capacitor - Google Patents

Abstract

 The stacked chip capacitor of the present invention is formed by stacking a plurality of dielectric layers and has first to fourth side surfaces parallel to the stacking direction, wherein the first side and the second side face each other, and the third side and the fourth side face each other. Opposing capacitor bodies; A plurality of first and second internal electrodes alternately stacked by a dielectric layer in the capacitor body; And first and second external electrodes of different polarities formed on the first and second sides, respectively. The first internal electrode has one first lead portion drawn out to the first and third side surfaces, the second internal electrode has one second lead portion drawn out to the second and fourth side surfaces, and the first external portion. The electrode is connected to the first internal electrode in contact with the first lead-out portion at the first and third side surfaces, and the second external electrode is connected to the second internal electrode in contact with the second lead-out portion at the second and fourth sides.

Stacked Chip Capacitors, Equivalent Inductance, ESL

Description

Multilayer Chip Capacitors

1A to 1C are perspective views and equivalent circuit diagrams of the external shape of a conventional multilayer chip capacitor.

2A to 2C are planar cross-sectional views illustrating a plan view of a conventional stacked chip capacitor and its internal structure.

3 to 7 are plan views, perspective views, and planar cross-sectional views illustrating an external structure of a stacked chip capacitor according to various embodiments of the present disclosure.

FIG. 8 is a graph illustrating attenuation characteristics according to frequencies of stacked chip capacitors according to an exemplary embodiment and a comparative example. FIG.

9 is a graph illustrating attenuation characteristics according to frequencies of stacked chip capacitors according to another exemplary embodiment and a comparative example of the present invention.

<Description of the symbols for the main parts of the drawings>

100, 200, 300, 400, 500: Stacked Chip Capacitors

101, 201, 301, 401, 501: capacitor body

103, 104, 203, 204, 303, 304, 403, 403 ', 404, 404', 503, 503 ', 504, 504': external electrode

103b, 104b, 203b, 204b, 303b, 304b, 403b, 404b, 503b, 504b: dielectric layer

103a, 104a, 203a, 204a, 303a, 304a, 403a, 404a, 503a, 504a: internal electrode

103c, 104c, 203c, 204c, 303c, 304c, 403c, 403c ', 404c, 404c' 503c, 503c ', 504c, 504c': withdrawal part

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to stacked chip capacitors, and more particularly to stacked chip capacitors having reduced equivalent series inductance (ESL) and exhibiting good high frequency attenuation characteristics.

In recent years, with the trend of miniaturization of electronic products and mounting density of electronic or electrical components, a large number of electromagnetic interference waves occur due to electromagnetic interference. In addition, as electric and electronic devices and information processing devices become multifunctional and high speed, an electromagnetic interference (EMI) problem due to unnecessary electromagnetic noise is inevitably generated. Electromagnetic interference can cause problems such as communication failure and malfunction of digital devices.

As a method for eliminating this unintended electromagnetic interference, a method of embedding or mounting an EMI filter in an electronic device is effectively used. An EMI filter is a filter for removing noise generated at an electromagnetic interface, and generally has a structure of a stacked chip capacitor. As EMI filters having excellent attenuation characteristics at high frequencies are required, low inductance chip capacitors and three-terminal through capacitors are used instead of the conventional two-terminal capacitors.

However, the actual capacitor not only forms capacitance C, but also includes parasitic inductance, or ESL. As a result, resonance occurs due to C and ESL, and the behavior as a capacitor is weakened above this resonance frequency (SRF). As a result, an attenuation waveform is formed at a specific frequency band, and the resonance frequency SRF is lowered as the ESL increases.

1A to 1C are perspective views and equivalent circuit diagrams of a conventional stacked chip capacitor. In particular, these figures show a state in which a capacitor is connected to a signal line such as a circuit board for use as an EMI filter. 2A-2C are plan and cross-sectional views, respectively, of the capacitor of FIGS. 1A-1C.

1A and 2A, a typical two-terminal stacked chip capacitor 10 includes a capacitor body 11 and external electrodes 13 and 14. In the main body 11, the plurality of first internal electrodes 13a and the second internal electrodes 14a are separated by the dielectric layers 13b and 14b and alternately stacked. The capacitor body 11 is formed by alternately stacking a plurality of dielectric layers 13b and 14b on which internal electrodes are formed. The first and second internal electrodes 13a and 14a are connected to the first external electrodes 13 and 14 having different polarities through the lead portions 13c and 14c, respectively (see FIG. 2A). Referring to FIG. 1A, the first external electrode 13 is connected to the signal line 53 and the second external electrode 14 is connected to the ground pattern 54 so that high frequency noise is input to the input portion IN of the signal line 53. To the ground pattern 54 through the EMI filter capacitor (10). However, as in the equivalent circuit diagram of FIG. 1A (resistance components are omitted for convenience), the capacitance 10 includes a parasitic inductance (ESL) of considerable magnitude, so that the removal of high frequency noise is not sufficient. In particular, the current path in the capacitor 10 (see arrow in FIG. 2A) has a significant length resulting in a high parasitic inductance value.

1B and 2B, the two-terminal stacked chip capacitor 20 is a low inductance chip capacitor (LICC). According to the capacitor 20, the signal line 63 and the ground pattern ( The length of the current path between 64 (see the arrow in FIG. 2B) is halved compared to the stacked chip capacitor 10, and the contact area between the inner and outer electrodes is doubled, that is, the distance between both sides of the outer electrode is coated ( A) is shorter than the length B of the side on which the external electrode is applied (see FIG. 1B), the contact area between the first internal electrode 23a and the first external electrode 23 and the second internal electrode 24a and The contact area between the second external electrodes 24 is larger (see Fig. 2b), thereby reducing the ESL and improving the high frequency attenuation characteristics than the conventional capacitor 10. In Fig. 2b, reference numeral 21 denotes a capacitor body, 23b and 24b denote dielectric layers, and reference numerals 23c and 24c denote lead-out of the internal electrodes 23a and 24a. It represents an.

1C and 2C, the stacked chip capacitor 30 is a three-terminal feed through capacitor. External electrodes 33 and 33 'of the same polarity applied to both sides of the main body 31 are connected to the input unit IN 73 and the output unit 73' of the signal line, respectively, and the main body 31 External electrodes 34 and 34 'of the other polarity applied to the middle portion of are connected to the ground pattern 74. The monopolar first inner electrode 33a extends through the entire length of the dielectric layer 33b to connect with the monopolar outer electrodes 33 and 33 ', and the inner electrode of the negative polarity is formed of the dielectric layer 34b. It extends through the entire width and is connected to the external electrodes 34 and 34 'at both ends. The high frequency noise passes through the capacitor 30 from the input portion 73 of the signal line to the ground pattern 74. According to this capacitor 30, the current path is shorter than the stacked chip capacitor 10 (see the arrow in FIG. 2C), and the inductance components by the current path are connected in parallel with each other (see the equivalent circuit diagram in FIG. 1C). Accordingly, it is possible to exhibit improved high frequency attenuation characteristics than the capacitor 20. In FIG. 2C, reference numerals 33c, 33c ', 34c, and 34c' denote lead-out portions of the internal electrodes.

However, to realize a circuit having sufficient high frequency attenuation characteristics, a high performance stacked chip capacitor having a lower ESL and a higher resonance frequency is required. These low ESL and high resonant frequency characteristics are required not only in EMI filters but also in decoupling capacitors for stabilizing the power circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a high performance stacked chip capacitor having improved high frequency attenuation characteristics.

In order to achieve the above technical problem, the stacked chip capacitor according to the first aspect of the present invention is a two-terminal capacitor,

A capacitor body formed by stacking a plurality of dielectric layers and having first to fourth side surfaces parallel to the stacking direction, the first side and the second side facing each other, and the third side and the fourth side facing each other; A plurality of first and second internal electrodes alternately stacked by a dielectric layer in the capacitor body; And first and second external electrodes of different polarities formed on the first and second sides, respectively,

The first internal electrode has one first lead portion drawn out to the first and third side surfaces, the second internal electrode has one second lead portion drawn out to the second and fourth side surfaces, and the first external portion. The electrode is connected to the first internal electrode in contact with the first lead-out portion at the first and third side surfaces, and the second external electrode is connected to the second internal electrode in contact with the second lead-out portion at the second and fourth sides.

According to an embodiment of the present invention, each of the first and second internal electrodes has a rectangular electrode pattern, and the first external electrode is integrally applied on the first side and the third side to form the first internal electrode. In contact with two sides, the second external electrode is integrally applied to the second side and the fourth side to contact the two sides of the second inner electrode. In particular, the first outer electrode is in contact with one long side of the first inner electrode over the entire length of the long side of the first inner electrode, and the second outer electrode is one long side of the second inner electrode over the full length of the second inner electrode. It can be contacted.

According to another embodiment of the invention, the first lead-out portion is in contact with the first side over the entire length of the first side, and in contact with the third and fourth side over some length of the third and fourth side. The second lead-out portion is also in contact with the second side over the entire length of the second side, and with the third and fourth side over some length of the third and fourth side. The first external electrode partially extends to the third and fourth side surfaces to contact the first lead portion at the first, third and fourth side surfaces. The second external electrode partially extends to the third and fourth side surfaces to contact the second lead portion at the second, third and fourth side surfaces. In this case, the distance between the first and second sides may be greater than the distance between the third and fourth sides. Conversely, the distance between the first and second sides may be smaller than the distance between the third and fourth sides. The latter is advantageous over the former in terms of the ESL reduction effect.

The stacked chip capacitor according to the second aspect of the present invention is a three-terminal through capacitor,

A capacitor body formed by stacking a plurality of dielectric layers and having first to fourth side surfaces parallel to the stacking direction, the first side and the second side facing each other, and the third side and the fourth side facing each other; A plurality of first and second internal electrodes alternately stacked by a dielectric layer in the capacitor body; And a stripe-like structure surrounding the outer surface of the capacitor body in the intermediate region between the first and second side surfaces and the first and second external electrodes formed on the first and second side surfaces, respectively. Including a third external electrode,

The first internal electrode has a first lead portion drawn to the first side with the full width of the dielectric layer, and a second lead portion drawn to the second side with the full width of the dielectric layer, and the second internal electrode has a third side and a second lead portion. Having third and fourth lead portions respectively drawn out to the sides,

The first external electrode contacts the first lead-out portion at the first, third and fourth sides, and the second external electrode contacts the second lead-out portion at the second, third and fourth sides, respectively, and connects with the first internal electrode. The third external electrode is connected to the second internal electrode in contact with the third and fourth lead portions.

According to an embodiment of the invention, the distance between the first side and the second side is longer than the distance between the third side and the fourth side.

The stacked chip capacitor according to the third aspect of the present invention,

A capacitor body formed by stacking a plurality of dielectric layers and having first to fourth side surfaces parallel to the stacking direction, the first side and the second side facing each other, and the third side and the fourth side facing each other; A plurality of first and second internal electrodes alternately stacked by a dielectric layer in the capacitor body; And monopolar first and second external electrodes formed on the first and second sides, respectively, and third and fourth external electrodes formed on the third and fourth sides, respectively,

The capacitor body has the same length of each side and has a square top surface, the first internal electrode has first and second lead portions drawn out to the first and second side surfaces, respectively, and the second internal electrode has a third and The first and second external electrodes are respectively connected to the first internal electrode in contact with the first and second lead-out parts, respectively, and the third and fourth external electrodes are respectively drawn out to the fourth side. The third and fourth lead portions respectively contact the second internal electrodes.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings are the same elements.

3 is a plan view showing a plan view, a perspective view, and an internal structure of a stacked chip capacitor according to an embodiment of the present invention. Referring to FIG. 3, the capacitor 100 is a two-terminal capacitor and includes a capacitor body 101 formed by stacking a plurality of dielectric layers 103b and 104b and first and second external electrodes having different polarities formed on side surfaces of the body. 103, 104). The capacitor body 101 has a rectangular parallelepiped shape and has first and second side surfaces S1 and S2 facing each other and the remaining third and fourth side surfaces S3 and S4 facing each other.

In the capacitor body 101, a plurality of first and second internal electrodes 103a and 104a are formed on the dielectric layers 103b and 104b. The first and second internal electrodes 103a and 104a are separated by a dielectric layer and alternately stacked alternately with each other. The first and second internal electrodes 103a and 104a are connected to the first and second external electrodes 103 and 104 through the first and second lead portions 103c and 104c, respectively, to have different polarities. . The first and second internal electrodes 103a and 104a having different polarities are disposed to face each other with a dielectric layer interposed therebetween to realize capacitance. For convenience, the boundary between the main electrode portion of the inner electrode (the portion of the inner electrode which substantially contributes to capacitance formation and the portion where the first and second inner electrodes overlap each other) and the lead portion is indicated by a dotted line.

In particular, according to this embodiment, each of the first and second internal electrodes 103a and 104a has a rectangular electrode pattern, and two sides of the first internal electrode 103a are formed of the first side surface S1 and the first side. The two sides of the second internal electrode 104a are drawn out to the third side surface S3, and the two side surfaces of the second internal electrode 104a are drawn out to the second side surface S2 and the fourth side surface S4. The first lead portion 103c of the first internal electrode 103a is in contact with the first and third side surfaces S1 and S3, and the second lead portion 104c of the second internal electrode 104a is the second and the second 4 is in contact with the side surfaces (S2, S4) (see the cross-sectional view of Figure 3).

In addition, the first external electrode 103 is integrally coated on the first side surface S1 and the third side surface S3 to be in contact with the first lead-out portion 103c, thereby forming two of the first internal electrodes 103. It comes in contact with the side. The second external electrode 104 is integrally applied on the second side surface S2 and the fourth side surface S4 to be in contact with the second lead-out portion 104c, and thus, the second external electrode 104 is formed on two sides of the second internal electrode 104. You will come across.

As such, the inner electrodes 103a and 104a and the outer electrodes 103 and 104 come into contact with a large area across two sides of the inner electrode, thereby increasing the contact area between the inner and outer electrodes, thereby increasing the contact area from the lead portion to the inner electrode (or to the inner electrode). The resistance Rdc of the current flowing from the inside of the internal electrode to the lead portion is reduced, and the value of the parasitic inductance generated from this current is also reduced.

In addition, as shown in FIG. 3, the first and second external electrodes 103 and 104 may be formed by the respective second internal electrodes 103a and the second lengths of the long sides of the first and second internal electrodes 103a and 104a, respectively. By contacting one long side of 104a), the contact area between the inner and outer electrodes is greatly increased. Furthermore, as shown in the plan view of FIG. 3, the current path between the heterogeneous polarities (see arrow) is reduced in length, and the effect of reducing parasitic inductance is further increased. This reduction in the length of the current path, in particular when the capacitor 100 is used for the EMI filter and connected to the signal line and the ground pattern, reduces the length of the current path between the signal line and the ground pattern, thereby further improving the high frequency noise canceling effect. . As a result, the overall ESL of the capacitor 100 is reduced, and the high frequency attenuation characteristic and the resonance frequency (SRF) characteristic are greatly improved. In addition, impedance reduction, including ESR (resistance component), reduces high-frequency power losses, making it easier to construct power-saving circuits.

4 is a diagram illustrating a two-terminal stacked chip capacitor 200 according to another embodiment of the present invention. According to the present embodiment, the lead portion 203c of the first internal electrode 203a is in contact with the first side surface S1 over the entire length of the first side surface S1, and the third and fourth side surfaces S3 and S4. Contact the third and fourth sides S3, S4 over a portion of the length). In addition, the second lead-out portion 204c of the second internal electrode 204a is in contact with the second side surface S2 over the entire length of the second side surface S2, and is part of the third and fourth side surfaces S3 and S4. It is in contact with the third and fourth sides S3 and S4 over the length.

In addition, the first external electrode 203 having the polarity is not only applied to the entire first side surface S1 but also partially extended to the third and fourth side surfaces S3 and S4 so that the first, third, and fourth electrodes are extended. The side surfaces S1, S3, and S4 are in contact with the first lead-out portion 203c of the first internal electrode 203a. The second external electrode 204 having the polarity is not only applied to the entire second side surface S2, but also partially extended to the third and fourth side surfaces S3 and S4, so that the second, third and fourth side surfaces are provided. In S2, S3, and S4, the second lead part 204c of the second internal electrode 204a is contacted.

Accordingly, the inner electrodes 203a and 204a and the outer electrodes 203 and 204 come into contact with each other over a very large contact area over three surfaces, and thus the resistance component Rdc and the parasitic inductance caused by the current between the contact portion and the inner electrode inside. The components are greatly reduced. As a result, the capacitor 200 exhibits a significantly reduced ESL value compared to the prior art, and when used for an EMI filter, the high frequency noise canceling effect is improved and excellent high frequency attenuation characteristics and resonance frequency (SRF) characteristics in various frequency ranges are achieved. Will be displayed. In addition, impedance reduction reduces high-frequency power loss, making it easier to construct power-saving circuits. In Fig. 4, reference numeral 201 denotes a capacitor body, and 203b and 204b denote a dielectric layer.

5 is a diagram illustrating a two-terminal stacked chip capacitor 300 according to still another embodiment of the present invention. Also in this embodiment, like the embodiment of FIG. 4, the first and second lead portions 303c and 304c of the first and second internal electrodes 303a and 304a have three side surfaces S1, S3, and S4 ( It extends over S2, S3, S4 and contacts the external electrodes 303, 304 at the three sides.

However, in the embodiment of FIG. 5, unlike the embodiment of FIG. 4, the distance between the two side surfaces S1 and S2 to which the external electrodes 303 and 304 are entirely applied is greater than the distance between the other opposing side surfaces S3 and S4. . Thus, the current path between heterogeneous polarities (the current path between the signal line and the ground pattern when used for the EMI filter) is shorter than in the embodiment of FIG. 4 and the inner and outer contact areas become larger (FIGS. 4 and 5). Comparison of cross-sectional views of.

Therefore, according to the embodiment of FIG. 5, the ESL is further reduced than in the embodiment of FIG. 4, whereby the high frequency attenuation characteristic and the resonance frequency characteristic are further improved, and the effect of reducing the high frequency power loss is more remarkably. do. In Fig. 5, reference numeral 301 denotes a capacitor body, and 303b and 304b denote a dielectric layer.

6 illustrates a stacked chip capacitor 400 according to another embodiment of the present invention. This capacitor 400 corresponds to a three-terminal feed through capacitor that can be particularly useful for EMI filters.

Referring to FIG. 6, the first and second external electrodes 403 and 403 ′ having the same polarity are coated on the first and second side surfaces S1 and S2 of the capacitor body 401, respectively. In the middle region of S2), a third external electrode 404 having a polarity is formed around the outer surface of the capacitor body 401 in a band shape.

In the embodiment of FIG. 6, in particular, the first and second lead portions 403c and 403c are led out to the first side surface S1 and the second side surface S2, 'to the full width' of the dielectric layer 403b, respectively. Meanwhile, the third and fourth lead portions 404c and 404c 'are led to the third side surface S3 and the fourth side surface S4, respectively. In addition, the first external electrode 403 is in contact with the first lead-out portion 403c at the first, third, and fourth side surfaces S1, S3, and S4, and the second external electrode 403 ′ is formed in the second, third, and third directions. The fourth side surfaces S2, S3, and S4 contact the second lead portions 403c ′, and are respectively connected to the first internal electrodes 403a. Meanwhile, the third external electrode contacts the third and fourth lead portions and is connected to the second internal electrode 404a.

According to the embodiment of FIG. 6, by contacting the inner electrode and the outer electrode with a wide contact area over three sides, not only the resistance component Rdc of the inner electrode is lowered but also the ESL is greatly reduced. As a result, the high frequency attenuation characteristic and the resonant frequency characteristic are greatly improved, and the high frequency power loss is further reduced. By making the distance between the first side surface S1 and the second side surface S2 longer than the distance between the third side surface S3 and the fourth side surface S4, the application process of the external electrode can be facilitated.

7 is a diagram illustrating a stacked chip capacitor 500 according to still another embodiment of the present invention. Referring to FIG. 7, the capacitor 500 may be used as a four-terminal capacitor, but connects the first and second external electrodes 503 and 503 'of the same polarity to the input terminal and the output terminal of the signal line, respectively. By connecting the third and fourth external electrodes 504 and 504 'to the ground terminal, the third and fourth external electrodes 504 and 504' can be used as a kind of three-terminal through capacitor.

Referring to FIG. 7, the first and second lead portions 503c and 503c ′ of the first internal electrode 503a may have the same polarity as the first and second external electrodes at the first and second side surfaces S1 and S2. 503 and 503 ', respectively, and the third and fourth lead portions 504c and 504c' of the second internal electrode 504a have a third polarity at the third and fourth side surfaces S3 and S4. And fourth external electrodes 504 and 504 '.

In the three-terminal through capacitor of FIG. 7, in particular, the lengths of the respective side surfaces S1 to S4 are substantially the same, so that the capacitor body 501 has a square top surface. As a result, at the same area (or the same capacitance), the current path between heterogeneous polarities is shortened, thereby reducing parasitic inductance components and resistance components. Therefore, the ESL is lowered, the high frequency attenuation characteristic and the resonant frequency characteristic are improved, and the high frequency power loss is reduced.

8 and 9 are graphs comparing frequency versus attenuation waveforms of the Examples and Comparative Examples. In FIG. 8, the two-terminal capacitor of FIG. 3 is used as an example (Example 1), and the conventional conventional two-terminal capacitors of FIGS. 1A and 2A are used as comparative examples. As shown in FIG. 8, it can be seen that Example 1 exhibits a higher resonance frequency (corresponding to a minimum point in the attenuation waveform) than in Comparative Example 1, and thus has a further reduced ESL.

In FIG. 9, the three-terminal through capacitor of FIG. 6 was used as an example (Example 2), and the three-terminal through capacitors of FIGS. 1C and 2C were used as a comparative example (Comparative Example 2). Also in Example 2, it can be seen that it shows more improved resonant frequency characteristics, less ESL and more improved high frequency attenuation characteristics than Comparative Example 2.

The present invention is not limited by the above-described embodiment and the accompanying drawings, but is intended to be limited by the appended claims, and various forms of substitution, modification, and within the scope not departing from the technical spirit of the present invention described in the claims. It will be apparent to those skilled in the art that changes are possible.

As described above, according to the present invention, the contact area between the internal and external electrodes is wide, and the length of the current path is reduced, so that lower ESL can be realized, and further improved high frequency attenuation characteristics and resonant frequency characteristics can be realized. It is possible to expand the scope of use. In addition, the ESR (resistance component) is reduced, further reducing power loss at high frequencies.

Claims (9)

A capacitor body formed by stacking a plurality of dielectric layers and having first to fourth side surfaces parallel to the stacking direction, the first side and the second side facing each other, and the third side and the fourth side facing each other; A plurality of first and second internal electrodes alternately stacked by a dielectric layer in the capacitor body; And Including first and second external electrodes of different polarities formed on the first and second sides, respectively, The first internal electrode has one first lead portion drawn out to the first and third side surfaces, the second internal electrode has one second lead portion drawn out to the second and fourth side surfaces, and the first external portion. The electrode is connected to the first inner electrode in contact with the first lead-out portion in the first and third side, the second outer electrode is in contact with the second inner electrode in contact with the second lead-out portion in the second and fourth side Stacked chip capacitors. The method of claim 1, Each of the first and second internal electrodes has a rectangular electrode pattern, and the first external electrode is integrally coated on the first side and the third side to contact the two sides of the first internal electrode, and the second The external electrode is integrally applied to the second side and the fourth side, the stacked chip capacitor, characterized in that the contact with the two sides of the second internal electrode. The method of claim 2, And the first external electrode contacts a long side of one of the opposing long sides of the first internal electrode, and the second external electrode contacts a long side of one of the opposing long sides of the second internal electrode. The method of claim 1, The first lead-out portion is in contact with the first side over the entire length of the first side, and in contact with the third and fourth side over some length of the third and fourth side, The second lead-out portion abuts the second side over the entire length of the second side, abuts the third and fourth side over some length of the third and fourth side, The first external electrode partially extends to the third and fourth side surfaces to contact the first lead-out portion at the first, third and fourth side surfaces, and the second external electrode partially extends to the third and fourth side surfaces to the second portion. And a third chip contact with the second lead-out portion in a third and fourth side. The method of claim 4, wherein And the distance between the first and second sides is greater than the distance between the third and fourth sides. The method of claim 4, wherein And the distance between the first and second side is smaller than the distance between the third and fourth side. A capacitor body formed by stacking a plurality of dielectric layers and having first to fourth side surfaces parallel to the stacking direction, the first side and the second side facing each other, and the third side and the fourth side facing each other; A plurality of first and second internal electrodes alternately stacked by a dielectric layer in the capacitor body; And A first polarity of the first and second external electrodes formed on the first and second side surfaces, and a third external electrode of the third polarity that surrounds the capacitor body outer surface of the intermediate region between the first and second side surfaces in a band shape. Including, The first internal electrode has a first lead portion drawn to the first side with the full width of the dielectric layer, and a second lead portion drawn to the second side with the full width of the dielectric layer, and the second internal electrode has a third side and a second lead portion. Having third and fourth lead portions respectively drawn out to the sides, The first external electrode contacts the first lead-out portion at the first, third and fourth sides, and the second external electrode contacts the second lead-out portion at the second, third and fourth sides, respectively, and connects with the first internal electrode. And the third external electrode is connected to the second internal electrode in contact with the third and fourth lead-out portions. The method of claim 7, wherein And the distance between the first side and the second side is longer than the distance between the third side and the fourth side. A capacitor body formed by stacking a plurality of dielectric layers and having first to fourth side surfaces parallel to the stacking direction, the first side and the second side facing each other, and the third side and the fourth side facing each other; A plurality of first and second internal electrodes alternately stacked by a dielectric layer in the capacitor body; And A first polarity of the first and second external electrodes formed on the first and second side surfaces, and a third polarity and a fourth external electrode formed on the third and fourth sides, respectively, The capacitor body has the same length of each side and has a square top surface, the first internal electrode has first and second lead portions drawn out to the first and second side surfaces, respectively, and the second internal electrode has a third and The first and second external electrodes are respectively connected to the first internal electrode in contact with the first and second lead-out parts, respectively, and the third and fourth external electrodes are respectively drawn out to the fourth side. The stacked chip capacitor of claim 3, wherein the stacked chip capacitor is connected to the second internal electrode in contact with the third and fourth lead portions, respectively.

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