JP3821790B2 - Multilayer capacitor - Google Patents

Multilayer capacitor Download PDF

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Publication number
JP3821790B2
JP3821790B2 JP2003106145A JP2003106145A JP3821790B2 JP 3821790 B2 JP3821790 B2 JP 3821790B2 JP 2003106145 A JP2003106145 A JP 2003106145A JP 2003106145 A JP2003106145 A JP 2003106145A JP 3821790 B2 JP3821790 B2 JP 3821790B2
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arranged
portions
multilayer capacitor
types
conductors
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JP2004311859A (en
Inventor
一郎 今井
正明 富樫
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Tdk株式会社
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Priority to JP2003106145A priority Critical patent/JP3821790B2/en
Priority claimed from TW93106290A external-priority patent/TWI229878B/en
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Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer capacitor having a significantly reduced equivalent series inductance (ESL), and is particularly suitable for a multilayer ceramic capacitor that can reduce voltage fluctuation of a power supply for a CPU.
[0002]
[Prior art]
In recent years, a CPU (main processing unit) used in an information processing apparatus has an increased operating frequency and a significant increase in current consumption due to improvement in processing speed and higher integration. Along with this, the operating voltage tends to decrease due to the reduction in power consumption. Therefore, a large current fluctuation occurs at a higher speed in the power source for supplying power to the CPU, and it is very difficult to suppress the voltage fluctuation accompanying the current fluctuation within the allowable value of the power source.
[0003]
For this reason, as shown in FIG. 7, a multilayer capacitor 100 called a decoupling capacitor is connected to a power source 102 and is frequently used as a countermeasure for stabilizing the power source. Then, current is supplied from the multilayer capacitor 100 to the CPU 104 by quick charge / discharge when the current fluctuates at a high speed, thereby suppressing the voltage fluctuation of the power source 102.
[0004]
[Patent Document 1]
JP 2002-164256 A
[Patent Document 2]
JP 2002-231559 A
[Patent Document 3]
JP-A-11-144996
[Patent Document 4]
JP 2002-151349 A
[Patent Document 5]
JP 2001-284171 A
[0005]
[Problems to be solved by the invention]
However, with the further increase in the operating frequency of today's CPUs, current fluctuations have become faster and larger. For this reason, as a result of the relatively large equivalent series inductance (ESL) of the multilayer capacitor 100 itself shown in FIG. 7, this equivalent series inductance greatly affects the voltage fluctuation of the power supply.
[0006]
That is, in the conventional multilayer capacitor 100 used in the power supply circuit of the CPU 104 shown in FIG. 7, since the ESL which is a parasitic component shown in the equivalent circuit in FIG. 7 is high, the current I shown in FIG. Thus, this ESL inhibits charging / discharging of the multilayer capacitor 100. For this reason, similarly to the above, the fluctuation of the voltage V of the power supply tends to become large as shown in FIG. 8, and it has become impossible to adapt to future CPU speedup.
[0007]
This is because the voltage fluctuation at the time of charging and discharging, which is a current transient, is approximated by the following formula 1, and the level of ESL is related to the magnitude of the voltage fluctuation of the power supply.
dV = ESL · di / dt Equation 1
Here, dV is a voltage fluctuation (V) at the time of transition, i is a current fluctuation amount (A), and t is a fluctuation time (second).
[0008]
On the other hand, the external appearance of this conventional capacitor is shown in FIG. 9 and the internal structure is shown in FIG. 10, and the conventional multilayer capacitor 100 will be described below based on these drawings. That is, in order to obtain capacitance, the conventional multilayer capacitor 100 shown in FIG. 9 has a pair of ceramic layers 112A each provided with two types of internal conductors 114 and 116 shown in FIG. The dielectric element body 112 is formed.
[0009]
These two types of inner conductors 114 and 116 are respectively drawn out to the two opposite side surfaces 112B and 112C of the dielectric body 112, and are connected to the inner conductor 114 and the terminal electrode 118 and the inner conductor. The terminal electrode 120 connected to 116 is installed on the side surfaces 112B and 112C facing each other of the multilayer capacitor 100 shown in FIG.
In view of the above facts, an object of the present invention is to provide a multilayer capacitor that can significantly reduce the equivalent series inductance and reduce the voltage fluctuation of the power supply for the CPU.
[0010]
[Means for Solving the Problems]
  The multilayer capacitor according to claim 1 is a dielectric body formed in a rectangular parallelepiped shape by laminating dielectric layers;
  Eight types of internal conductors arranged on the same plane and arranged sequentially in the dielectric body with the layers being separated by a dielectric layer, each having a single lead portion,
  Eight terminal electrodes disposed on two long side surfaces of the four side surfaces forming the dielectric body and connected to the eight kinds of internal conductors through the lead portions;
  A multilayer capacitor having
  Two types of internal conductors arranged on the same surface are arranged opposite to each of the two types of internal conductors arranged on the other surface, so that two sets of capacitors are built in,
  In order to make the polarities of the adjacent terminal electrodes different from each other, each of the lead portions is drawn four by four toward the two long side surfaces of the four side surfaces of the dielectric element body. Connected to each terminal electrode,
  A cut portion is formed in each of the eight types of internal conductors, and portions around the cut portions of these internal conductors are respectively flow channel portions through which current can flow.
  These flow paths are respectively arranged in such a way that current flows in the opposite direction between the flow paths of the adjacent internal conductors via the dielectric layer.It is characterized by that.
[0011]
According to the multilayer capacitor of the first aspect, the dielectric body is formed in such a manner that two types of inner conductors are arranged on the same plane in a dielectric body formed by stacking dielectric layers into a rectangular parallelepiped shape. The eight terminal electrodes are arranged on each of two long side surfaces of the four side surfaces forming the dielectric element body.
[0012]
  AndTwo types of internal conductors arranged on the same surface are arranged opposite to each of the two types of internal conductors arranged on the other surface, so that not only two sets of capacitors are built-in. ,A total of eight lead portions each drawn from each of the eight types of inner conductors are drawn four by two toward the two long side surfaces of the four side surfaces of the dielectric body, The adjacent terminal electrodes are connected to the eight terminal electrodes so that the polarities of the adjacent terminal electrodes are different from each other. In other words, as these eight types of inner conductors are stacked on the same surface, two types of them are laminated on the same plane,as mentioned aboveTwo sets of capacitors are formed in which the inner conductors are arranged in parallel while facing each other.
[0013]
As a result, for example, the lead portions of two inner conductors that are adjacent to each other through the dielectric layer are connected to two terminal electrodes that are adjacent to the side surface of the dielectric element body, respectively. For example, when the multilayer capacitor according to the present invention is energized, the current flows in such a manner that the polarities of the adjacent terminal electrodes are different from each other and alternately turn to the positive and negative electrodes. Along with this, the magnetic fluxes generated at the respective lead portions cancel each other out by the currents flowing in the lead portions in opposite directions, and the effect of reducing the equivalent series inductance is produced.
[0014]
As described above, in the multilayer capacitor according to the present claim, the ESL is further reduced, and the effective inductance is greatly reduced. As a result, according to the present invention, the oscillation of the voltage of the power supply can be reliably suppressed, and an optimum multilayer capacitor can be obtained for the power supply of the CPU.
[0015]
Further, according to the present invention, since the eight kinds of internal conductors are arranged in the form of two kinds arranged on the same plane, a capacitor array composed of two sets of capacitors is formed. It becomes possible to achieve higher functionality. In addition, the four side electrodes formed on the two long side surfaces of the four side surfaces of the dielectric body have four terminal electrodes connected to the lead portions of the internal conductors, so that the long side surfaces are effectively used. As it can be used, it has become possible to reduce the size of multilayer capacitors.
[0016]
  On the other hand, this claimAccording to the multilayer capacitor, 8Notches are formed in each type of inner conductor, and the inner conductors adjacent to each other through a dielectric layer are formed around the notches of these inner conductors as flow paths through which current can flow. These flow paths are respectively arranged in such a way that currents flow in opposite directions between the flow paths.ing.
[0017]
Accordingly, in the present claim, these eight types of internal conductors each have a cut portion, and the portion of the internal conductor around the cut portion constitutes a flow path portion. The flow path portions are respectively arranged in such a manner that currents flow in opposite directions with respect to the flow path portions of other internal conductors that are adjacent to each other via the dielectric layer.
[0018]
Therefore, when the multilayer capacitor is energized, current flows in opposite directions between the upper and lower flow path portions adjacent to each other through the dielectric layer. Along with this, the magnetic fluxes generated by the high-frequency current flowing through the internal conductor are canceled out so as to cancel each other, and the parasitic inductance of the multilayer capacitor itself is reduced, thereby reducing the equivalent series inductance (ESL). Further, even in the same internal conductor, the direction of current flow is reversed between the portions of the flow path portion located across the notch, so that the equivalent series inductance is further reduced.
[0019]
  From the above, according to the multilayer capacitor of the present claim,the aboveIn addition, the ESL is further reduced, and the effective inductance is further greatly reduced.
[0020]
  Claim2According to the multilayer capacitor according to claim1'sIn addition to the configuration similar to that of the multilayer capacitor, there are configurations in which a plurality of eight types of internal conductors are arranged in the dielectric body.
  That is, by arranging a plurality of these eight types of inner conductors in the dielectric body, not only the capacitance of the multilayer capacitor according to the present invention is increased, but also the action of canceling out the magnetic field is further increased, and the inductance is increased. Is significantly reduced and ESL is further reduced.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a multilayer capacitor according to the present invention will be described with reference to the drawings. A multilayer ceramic capacitor (hereinafter simply referred to as a multilayer capacitor) 10 which is a multilayer capacitor according to the present embodiment is shown in FIGS. As shown in these figures, the main part is a dielectric body 12 which is a rectangular parallelepiped sintered body obtained by firing a laminated body in which a plurality of ceramic green sheets as dielectric sheets are laminated. A multilayer capacitor 10 is configured.
[0022]
As shown in FIGS. 1 and 3, planar inner conductors 21 and 25 are arranged side by side at a predetermined height in the dielectric element body 12 with a gap between them. Similarly, the planar inner conductors 22 and 26 have a gap between them below the inner conductors 21 and 25 across the ceramic layer 12A as the dielectric layer in the dielectric body 12. However, they are arranged side by side.
[0023]
Similarly, planar internal conductors 23 and 27 are arranged below the inner conductors 22 and 26 across the ceramic layer 12A in the dielectric body 12, with a gap between them. Similarly, planar inner conductors 24 and 28 are arranged side by side on the lower side of the inner conductors 23 and 27 separating the ceramic layer 12A in the dielectric body 12 with a gap between them. Has been.
[0024]
As described above, the four types of inner conductors from the inner conductor 21 to the inner conductor 24 are arranged to face each other while being separated by the ceramic layer 12A in the portion on the left side in the dielectric body 12. In addition, the four types of internal conductors from the internal conductor 25 to the internal conductor 28 are arranged to face each other while being separated by the ceramic layer 12A in the portion on the right side in the dielectric body 12. become.
[0025]
That is, in the present embodiment, the ceramic layer 12A, which is a fired dielectric sheet, is sandwiched between the four types of internal conductors from the internal conductor 21 to the internal conductor 24, and the internal conductor 25 to the internal conductor. The four types of internal conductors up to 28 are arranged in the dielectric body 12 in order, so that a total of eight types of internal conductors 21 to 28 are arranged in the dielectric body 12. . Further, under the inner conductors 24 and 28, as shown in FIG. 3, the two inner conductors, which are four layers of electrodes, are repeatedly arranged in the same order as described above. There are about 10 sets of counts (three sets are shown in the figure).
[0026]
And the shape which has a substantially uniform clearance gap between each inner conductor 21-28 arrange | positioned in total four layers in the same layer in the dielectric body 12 and the outer peripheral end of 12 A of ceramic layers. These internal conductors 21 to 28 are each formed in a quadrangular shape. In addition, as a material of these inner conductors 21 to 28 formed in a quadrangular shape, not only nickel, nickel alloy, copper, or copper alloy, which are base metal materials, can be considered, but materials mainly composed of these metals can be used. Conceivable.
[0027]
On the other hand, as shown in FIG. 1, the inner conductor 21 is formed with a lead portion 21 </ b> A so as to be drawn from the near left side portion of the inner conductor 21 toward the near side. In addition, a lead portion 22 </ b> A is formed in the internal conductor 22 by pulling out the conductor from the near right side portion of the internal conductor 22 toward the near side. Further, the inner conductor 23 is formed with a lead-out portion 23A so as to be drawn out from the inner right side of the inner conductor 23 toward the rear side. In addition, a lead portion 24 </ b> A is formed in the internal conductor 24 by drawing the conductor from the back left side portion of the internal conductor 24 toward the back side direction.
[0028]
On the other hand, the inner conductor 25 arranged adjacent to the inner conductor 21 is formed with a lead portion 25 </ b> A so as to be drawn from the inner right side portion of the inner conductor 25 toward the inner side. In addition, a lead portion 26 </ b> A is formed in the internal conductor 26 by pulling out the conductor from the inner left side portion of the inner conductor 26 arranged adjacent to the inner conductor 22 toward the rear side.
[0029]
Furthermore, a lead portion 27A is formed in the inner conductor 27 arranged adjacent to the inner conductor 23 so as to be drawn from the near left side portion of the inner conductor 27 toward the near side. In addition, a lead portion 28 </ b> A is formed in the internal conductor 28 by pulling out the conductor from the front right side portion of the internal conductor 28 disposed adjacent to the internal conductor 24 toward the front side.
[0030]
As described above, the four lead portions 21A, 22A, 27A, and 28A are drawn to the front side surface 12B of the dielectric element body 12 shown in FIG. 2, and the four lead portions 23A, 24A, 25A, and 26A are drawn. Is drawn out to the back side surface 12D of the dielectric body 12. That is, each of the lead portions 21A to 28A is pulled out by four toward the two long side surfaces 12B and 12D of the four side surfaces 12B to 12E of the dielectric body 12 shown in FIG. ing. In the present embodiment, the length W of the side surfaces 12C and 12E is 1.25 mm, for example, whereas the length L of the two side surfaces 12B and 12D from which the drawer portions 21A to 28A are pulled out is 2 for example. 0.0 mm.
[0031]
As shown in FIG. 2, on the front side surface 12 </ b> B of the dielectric element body 12, a terminal electrode 31 connected to the lead portion 21 </ b> A of the inner conductor 21 and a terminal electrode 32 connected to the lead portion 22 </ b> A of the inner conductor 22. The terminal electrode 37 connected to the lead portion 27A of the internal conductor 27 and the terminal electrode 38 connected to the lead portion 28A of the internal conductor 28 are arranged in this order from the left.
[0032]
Similarly, as shown in FIG. 2, a terminal electrode 34 connected to the lead portion 24 </ b> A of the internal conductor 24 and a terminal connected to the lead portion 23 </ b> A of the internal conductor 23 are provided on the side surface 12 </ b> D on the back side of the dielectric body 12. The electrode 33, the terminal electrode 36 connected to the lead portion 26A of the internal conductor 26, and the terminal electrode 35 connected to the lead portion 25A of the internal conductor 25 are arranged in this order from the left.
[0033]
As described above, in the present embodiment, there are four terminal electrodes 31 to 38 on the two long side surfaces 12B and 12D among the four side surfaces 12B to 12E of the dielectric body 12 having a hexahedron shape which is a rectangular parallelepiped. The eight internal conductors 21 to 28 and the terminal electrodes 31 to 38 are connected to each other through the lead portions 21A to 28A.
[0034]
On the other hand, the central portions of the inner conductors 21 and 27 are provided with cut portions 29A which are cuts extending in the left-right direction in FIG. 1, and the left end portion of the cut portions 29A is bent. , Extending to the right side of the lead portions 21A and 27A in the near side direction. Accordingly, due to the presence of the cut portion 29A, the flow path portion 21B that becomes the flow path of the current of the internal conductor 21 and the flow path portion 27B that becomes the flow path of the current of the internal conductor 27 are formed in a bent shape. ing.
[0035]
Further, the inner conductors 22 and 28 are provided with cut portions 29B which are cuts extending in the left-right direction from the middle of the right end side in FIG. 1 of the inner conductors 22 and 28, respectively. Therefore, due to the presence of the cut portion 29B, the flow path portion 22B serving as the current flow path of the internal conductor 22 and the flow path portion 28B serving as the current flow path of the internal conductor 28 are formed in a bent shape. ing.
[0036]
Further, in the central portions of the inner conductors 23 and 25, a cut portion 29C which is a cut extending in the left-right direction in FIG. 1 is provided, and the right end portion of the cut portion 29C is bent. , Extending to the left side of the lead-out portions 23A and 25A in the back side direction. Therefore, due to the presence of the cut portion 29C, the flow path portion 23B that becomes the flow path of the current of the internal conductor 23 and the flow path portion 25B that becomes the flow path of the current of the internal conductor 25 are formed in a bent shape. ing.
[0037]
Further, the inner conductors 24 and 26 are provided with cut portions 29D which are cuts extending in the left-right direction from the middle of the left end side in FIG. 1 of the inner conductors 24 and 26, respectively. Therefore, due to the presence of the cut portion 29D, the flow path portion 24B serving as the current flow path of the internal conductor 24 and the flow path portion 26B serving as the current flow path of the internal conductor 26 are formed in a bent shape. ing.
[0038]
Therefore, in the present embodiment, due to the presence of the notches 29A to 29D, each of the inner conductors 21 to 28 includes the channel portions 21B to 28B that have a plurality of portions that are bent at right angles and portions that are folded back to form a belt shape. Will have.
[0039]
On the other hand, the multilayer capacitor 10 according to the present embodiment has two built-in capacitors, and a use example such as the circuit diagram shown in FIG. 5 is conceivable. Specifically, the terminal electrodes 31, 32, 33, 34 on the left side are connected to the left power supply 41 and the CPU 43. That is, the terminal electrodes 31 and 33 are connected between one end side of the CPU 43 and the power supply 41, and the terminal electrodes 32 and 34 are connected to the other end side of the CPU 43 and grounded.
[0040]
Further, the terminal electrodes 35, 36, 37, 38 on the right side are connected to the right power source 42 and the CPU 44. That is, the terminal electrodes 35 and 37 are connected between one end side of the CPU 44 and the power source 42, and the terminal electrodes 36 and 38 are connected to the other end side of the CPU 44 and grounded.
[0041]
Accordingly, as shown in the equivalent circuit shown in FIG. 4, the terminal electrodes 31, 33, 35, and 37 and the terminal electrodes 32, 34, 36, and 38 are used in opposite polarities. For example, as shown in FIGS. 2 and 4, every other terminal electrode 31, 37 on the front side surface 12B becomes a positive pole, and every other terminal electrode 32, 38 becomes a negative pole, and the rear side. The alternate terminal electrodes 33 and 35 on the side surface 12D of the side surface 12D may become a positive pole and the alternate terminal electrodes 34 and 36 may become a negative pole. At this time, the current direction indicated by the arrow in FIG. Current will flow.
[0042]
That is, current flows along the clockwise direction in the flow passage portions 21B, 23B, 25B, and 27B of the inner conductors 21, 23, 25, and 27 that are connected to the terminal electrodes 31, 33, 35, and 37, respectively. , 34, 36, and 38, currents flow in the counterclockwise direction in the flow path portions 22B, 24B, 26B, and 28B of the inner conductors 22, 24, 26, and 28, respectively.
[0043]
As described above, in the portion on the left side of the dielectric body 12, currents flow in opposite directions between the flow path portions 21 </ b> B and 22 </ b> B of the adjacent internal conductors 21 and 22 through the ceramic layer 12 </ b> A. In form, the flow path portions 21B and 22B are disposed on the inner conductors 21 and 22, respectively. Similarly, between the flow path portion 22B and the flow path portion 23B of the adjacent internal conductors 22 and 23 via the ceramic layer 12A, the flow path portions 22B and 23B are respectively formed in such a manner that currents flow in opposite directions. The conductors 22 and 23 are arranged.
[0044]
Similarly, between the flow path portion 23B and the flow path portion 24B of the internal conductors 23 and 24 adjacent via the ceramic layer 12A, and between the flow path portion 24B and the flow path portion 21B of the internal conductors 24 and 21, respectively. Thus, the flow path portions 23B and 24B are disposed on the inner conductors 23 and 24, respectively, in such a manner that current flows in the opposite direction.
[0045]
On the other hand, in the portion on the right side of the dielectric body 12, the flow path portions 25 </ b> B to 27 </ b> B are respectively connected to the inner conductors 25 to 28 adjacent to each other via the ceramic layer 12 </ b> A so that currents flow in opposite directions. The conductors 25 to 28 are arranged.
[0046]
Next, the operation of the multilayer capacitor 10 according to the present embodiment will be described.
According to the multilayer capacitor 10 in accordance with the present embodiment, eight types of internal conductors 21 to 28 are provided in the dielectric body 12 formed in a rectangular parallelepiped shape by laminating a plurality of dielectric sheets each serving as the ceramic layer 12A. However, the ceramic layers 12A are arranged in such a manner that they are arranged in two on the same plane, with the ceramic layers 12A being separated from each other. Furthermore, a total of eight lead portions 21 </ b> A to 28 </ b> A each drawn from the eight types of inner conductors 21 to 28 are formed long in the four side surfaces 12 </ b> B to 12 </ b> E of the dielectric body 12. Four are pulled out toward the two side surfaces 12B and 12D.
[0047]
Also, eight terminal electrodes 31 to 38 are arranged four by two on the two side surfaces 12B and 12D that are also formed to be long, and the polarities of the terminal electrodes adjacent to each other on the same side surface among these terminal electrodes 31 to 38 are arranged. Are connected to the eight terminal electrodes 31 to 38, respectively, so that the lead portions 21A to 28A of the internal conductors 21 to 28 are connected to the eight terminal electrodes 31 to 38, respectively. That is, as the eight types of inner conductors 21 to 28 connected to the eight terminal electrodes 31 to 38 are stacked on the same surface, two types of inner conductors 21 to 28 are laminated on the same surface. Two sets of capacitors arranged in parallel while facing each other are formed.
[0048]
Specifically, four lead electrodes 31 arranged on the front side surface 12B of the dielectric body 12 shown in FIG. 32, 37, 38 are connected to two adjacent to each other, and four terminal electrodes 33, 34, 35, 36 arranged on the rear side surface 12D are adjacent to each other. I tried to connect the two.
[0049]
As a result, when the multilayer capacitor 10 of the present embodiment is energized, the polarities of the adjacent terminal electrodes on the same side surface of the terminal electrodes 31 to 38 are different from each other and alternately become positive and negative electrodes sequentially. In the form, current will flow. As a result, the magnetic fluxes generated in each of the lead portions 21A to 28A cancel each other out due to the currents flowing in opposite directions between the adjacent lead portions, resulting in an effect of reducing the equivalent series inductance. .
[0050]
Further, in the present embodiment, these eight types of internal conductors 21 to 28 have cut portions 29A to 29D, respectively, and each of the internal conductors 21 to 28 sandwiching the cut portions 29A to 29D. The portions not only constitute the flow path portions 21B to 28B, respectively, but also in such a manner that currents flow in opposite directions between the flow path portions of other internal conductors adjacent to each other via the ceramic layer 12A. Each flow path part 21B-24B and each flow path part 25B-28B are each arrange | positioned.
[0051]
Accordingly, when the multilayer capacitor 10 is energized, the flow path portions 21B to 24B of the internal conductors 21 to 24 adjacent to each other via the ceramic layer 12A and the flow path portions 25B to 28B of the internal conductors 25 to 28 are also provided. Between them, currents flow in opposite directions. Along with this, the magnetic fluxes generated by the high-frequency current flowing in the inner conductor are canceled out so as to cancel each other, and the parasitic inductance of the multilayer capacitor 10 itself is reduced, thereby further reducing the equivalent series inductance (ESL). .
[0052]
Further, even in the same inner conductors 21 to 28, the current flowing directions are opposite to each other between the portions located between the cut portions 29A to 29D of the flow passage portions 21B to 28B. Inductance is further reduced.
[0053]
As described above, the multilayer capacitor 10 according to the present embodiment is greatly reduced in ESL, and the effective inductance is greatly reduced. As a result, according to the present embodiment, the oscillation of the voltage of the power supply can be reliably suppressed, and the multilayer capacitor 10 that is optimal for the power supply of the CPU is obtained.
[0054]
On the other hand, in the present embodiment, as the eight types of inner conductors 21 to 28 are arranged in the form of two types arranged on the same plane, a capacitor array composed of two sets of capacitors is formed. Therefore, it is possible to improve the functionality of the multilayer capacitor 10. And, since there are four terminal electrodes connected to the lead portion of the internal conductor on the two long side surfaces 12B and 12D among the four side surfaces 12B to 12E of the dielectric element body 12, As the long side surfaces 12B and 12D can be effectively used, the multilayer capacitor 10 can be downsized.
[0055]
On the other hand, in the present embodiment, a plurality of the eight types of inner conductors 21 to 28 are arranged in the dielectric body 12, so that not only the capacitance of the multilayer capacitor 10 is increased, but also the magnetic field is canceled. The action is further increased, the inductance is greatly reduced, and the ESL is further reduced.
[0056]
Next, the Sz1 characteristic of the S parameter of each sample below was measured using a network analyzer, and the attenuation characteristic of each sample was obtained. First, the content of each sample will be described. That is, the general multilayer capacitor shown in FIG. 9 is used as a conventional capacitor, and the multilayer capacitor according to the embodiment shown in FIG. 2 is used as an example.
[0057]
Here, the constant of the equivalent circuit was calculated so that the measured value of the attenuation characteristic and the attenuation of the equivalent circuit in the multilayer capacitor 100 shown in FIG. Then, from the data of the attenuation characteristics of each sample shown in FIG. 6, the resonance point is increased to about 43 MHz in the embodiment with respect to about 18 MHz of the conventional example, and the attenuation amount of the embodiment is about 40 MHz or higher in the example. It can be seen that it is about 15 dB larger than the attenuation. For this reason, it can be understood that the improvement of the high-frequency characteristics can be seen in the examples by this data.
[0058]
On the other hand, with respect to the ESL result calculated by measuring with an impedance analyzer, the example is greatly reduced to 135.2 pH compared to 750.5 pH of the conventional example. Regarding the equivalent series resistance (ESR), the conventional example was 20.5 mΩ, while the example was 24.8 mΩ.
[0059]
Regarding the dimensions of the samples used here, the length W and the length L shown in FIGS. 2 and 9 were W = 1.25 mm and L = 2.0 mm in both the conventional example and the example. The capacitance of each sample used in the test was 0.105 μF in the conventional example and 0.102 μF in the example.
[0060]
Although the multilayer capacitor 10 according to the above embodiment has a structure having eight types of internal conductors, the number of layers is not limited to the number shown in the embodiment and may be larger. Further, in the above embodiment, the adjacent terminal electrodes have different polarities. However, in accordance with this, the terminal electrodes facing each other have different polarities. A conductor is arranged.
[0061]
【The invention's effect】
According to the present invention, it is possible to provide a multilayer capacitor that can significantly reduce the equivalent series inductance and reduce the voltage fluctuation of the power supply for the CPU.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view of a multilayer capacitor according to an embodiment of the present invention, and is a view showing an internal conductor portion of the multilayer capacitor.
FIG. 2 is a perspective view showing a multilayer capacitor in accordance with an embodiment of the present invention.
3 is a cross-sectional view showing the multilayer capacitor in accordance with an embodiment of the present invention, and is a cross-sectional view taken along the line 3-3 in FIG.
FIG. 4 is a diagram showing an equivalent circuit of the multilayer capacitor in accordance with one embodiment of the present invention.
FIG. 5 is a circuit diagram in which the multilayer capacitor according to one embodiment of the present invention is used in a form of being connected to two circuits as a capacitor array.
FIG. 6 is a graph showing attenuation characteristics of each sample.
FIG. 7 is a circuit diagram employing a conventional multilayer capacitor.
FIG. 8 is a graph showing a relationship between current fluctuation and voltage fluctuation in a circuit employing a conventional multilayer capacitor.
FIG. 9 is a perspective view showing a multilayer capacitor according to a conventional example.
FIG. 10 is an exploded perspective view showing a portion of an inner conductor of a multilayer capacitor according to a conventional example.
[Explanation of symbols]
10 multilayer capacitors
12 Dielectric body
12B-12E side
21-28 Inner conductor
21A-28A drawer part
21B-28B Channel part
29A-29D cutting part
31-38 Terminal electrode

Claims (2)

  1. A dielectric body formed in a rectangular parallelepiped shape by laminating dielectric layers;
    Eight types of internal conductors arranged on the same plane and arranged sequentially in the dielectric body with the layers being separated by a dielectric layer, each having a single lead portion,
    Eight terminal electrodes disposed on two long side surfaces of the four side surfaces forming the dielectric body and connected to the eight kinds of internal conductors through the lead portions;
    A multilayer capacitor having
    Two types of internal conductors arranged on the same surface are arranged opposite to each of the two types of internal conductors arranged on the other surface, so that two sets of capacitors are built in,
    In order to make the polarities of the adjacent terminal electrodes different from each other, each of the lead portions is drawn four by four toward the two long side surfaces of the four side surfaces of the dielectric element body. Each connected to a terminal electrode ,
    A cut portion is formed in each of the eight types of internal conductors, and portions around the cut portions of these internal conductors are respectively flow channel portions through which current can flow.
    A multilayer capacitor , wherein the flow path portions are respectively arranged in such a manner that current flows in opposite directions between the flow path portions of the internal conductors adjacent to each other through the dielectric layer .
  2. The multilayer capacitor according to claim 1, wherein a plurality of eight types of inner conductors are arranged in the dielectric body .
JP2003106145A 2003-04-10 2003-04-10 Multilayer capacitor Active JP3821790B2 (en)

Priority Applications (1)

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JP2003106145A JP3821790B2 (en) 2003-04-10 2003-04-10 Multilayer capacitor

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JP2003106145A JP3821790B2 (en) 2003-04-10 2003-04-10 Multilayer capacitor
TW93106290A TWI229878B (en) 2003-03-12 2004-03-10 Multilayer capacitor
KR20040016916A KR100571110B1 (en) 2003-03-12 2004-03-12 Multilayer capacitor
US10/798,361 US6914767B2 (en) 2003-03-12 2004-03-12 Multilayer capacitor
CNB2004100287370A CN100385584C (en) 2003-03-12 2004-03-12 Laminated capacitor
HK05101302A HK1069007A1 (en) 2003-03-12 2005-02-16 Overlapping conderser
US11/144,633 US7019957B2 (en) 2003-03-12 2005-06-06 Multilayer capacitor
US11/144,634 US7019958B2 (en) 2003-03-12 2005-06-06 Multilayer capacitor

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US7599166B2 (en) * 2005-11-17 2009-10-06 Samsung Electro-Mechanics Co., Ltd. Multilayer chip capacitor
KR100790708B1 (en) * 2005-11-17 2008-01-02 삼성전기주식회사 Multilayer Chip Capacitor
JP4952779B2 (en) * 2009-12-25 2012-06-13 Tdk株式会社 Multilayer capacitor array

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