JPH0758117A - Vertical semiconductor element - Google Patents

Abstract

PURPOSE:To improve BVEBO of a vertical semiconductor element by removing a thermal oxide film on the surface of a base by etching and also by taking impurities into a re-oxide film by lowering the surface concentration by re- oxidation treatment after the removing even in the vicinity of base surface. CONSTITUTION:Thermal oxide film is removed by performing a base etching process and also etching is performed near the surface of inner and outer base layers 13 and 14. Thereafter, the surfaces of a first region 13 and a second region 14 of second conductivity type are thermally oxidized again and are covered with a re-oxidized film 15 thinner than 50 angstrom, and impurities on the surfaces of the first region 13 and the second region 14 of second conductivity type are taken into a thin re-oxidized film 15 thereby reducing the surface concentration by 1 digit approximately. By doing this, the BVEBO characteristics can be improved.

Description

Detailed Description of the Invention

[0001]

The present invention relates to integrated circuit devices,
In particular, it is suitable for improving the withstand voltage of the BV _{E BO} of the vertical semiconductor device integrated with it.

[0002]

2. Description of the Related Art A vertical NPN transistor will be described as a component of an integrated circuit device with reference to FIG. A thermal oxide film 2 is formed on an N-type or first conductivity type semiconductor substrate 1 and then a selective oxide layer 3 is provided by a selective oxidation method. P ⁺ type, that is, the first region 4 functioning as an external base of the second conductivity type
To form. Further, a second region 5 of P type, that is, the second conductivity type, which partially overlaps with this and operates as an internal base, is also installed.
For this formation, the thermal oxide film 2, that is, the implant (Ion Implanta)
tion) through the buffer thermal oxide film 2. In forming the inner and outer base regions 4 and 5, the first region 4 having a high concentration and the second region 5 having a low concentration are also formed through the ion implantation process and the heat treatment process.

In the low concentration second region 5, an N type or first conductivity type region 6 acting as an emitter region is formed,
For example, Al or Al alloy (Al
-Si, Al-Si-Cu) or the like is deposited by, for example, a sputtering process and electrically connected to provide an electrode.
This is performed by a method of depositing a conductive material such as Al by, for example, sputtering in a window (not shown) provided by using a known photolithography technique.

[0004]

When forming a vertical NPN transistor, that is, a vertical semiconductor element in an integrated circuit element, there is no choice but to improve productivity by performing a common ion implantation step for each element to be integrated. The reality is that there is none.

On the other hand, it is known that lowering the ion implantation concentration is effective for improving the BV _EBO of the vertical semiconductor device, but it is difficult to control h _{FE in addition} to increasing h _FE . This is because the requirement for a single element cannot be satisfied because a common ion implantation process is essential for each element. For example, even if the ion implantation concentration is lowered, the variation of the resistance component that occurs will h _FE Difficult to control.

The guaranteed value of the BV _EBO withstand voltage is determined by the voltage based on the current value that does not deteriorate in the low current region. However, depending on the product in the circuit, a counter electromotive voltage may be applied. Occurs. Also, if the base of the transistor is clamped by BV _EBO , a malfunction occurs in the circuit. Therefore, it is extremely important to improve the BV _EBO breakdown voltage and increase the _margin without changing the characteristics of the transistor.

The present invention has been made under such circumstances, and particularly improves the BV _{E BO} breakdown voltage of a vertical semiconductor element.

[0008]

A semiconductor substrate of the first conductivity type, a selective oxide layer selectively located on the semiconductor substrate, a thermal oxide film exposed between the selective oxide layers, and a single thermal oxide film. A first region of the second conductivity type that extends inward from the oxide film,
A low concentration second conductivity type second region which partially overlaps the second conductivity type first region and goes inward from the thermal oxide film, and surfaces of the second conductivity type second region and first region The vertical semiconductor device according to the present invention is characterized by a re-oxidation film covering the first conductive type region, a first conductive type region located in the second region of the second conductive type, and an electrode electrically connected to each region. is there.

[0009]

To improve the BV _{EB O} without changing the implantation concentration profile of the vertical semiconductor device in the present invention, base -
The thermal oxide film on the surface of the base was removed by etching, and the vicinity of the base surface was also removed, and then the surface concentration was reduced by reoxidation to incorporate impurities into the reoxidized film. The base
Note that the surface concentration needs to be lowered in order to improve the withstand voltage because the withstand voltage is determined by the emitter-base junction on the surface with a high impurity concentration.

[0010]

Embodiments of the present invention will be described with reference to FIGS. As shown in FIG. 2, a thermal oxide film 11 is formed on the surface of the N-type first conductivity type semiconductor substrate 10, and then selective oxide layers 12 are formed at a plurality of locations by a known selective oxidation method using silicon nitride. Although it is described in the drawing on the assumption that a vertical semiconductor device is formed, actually, a plurality of selective oxide layers 12 are provided for an integrated circuit device, and a thermal oxide film 11 exists between them.

Next, as shown in FIG. 2, B ions of the second conductivity type are implanted into a part of the N-type semiconductor substrate 10 by using an implantation mask (not shown), for example, a resist, so that the surface concentration is 5 ×. External base of 10 ¹⁹ to 10 ²⁰ atoms / cm ³ (P
⁺ ) That is, the first region 13 is formed.

After removing the resist, as shown in FIG. 1, B ions of the second conductivity type are implanted through the entire surface of the thermal oxide film 11 to form an internal base having a surface concentration of 10 ¹⁹ atoms / cm ^3.
That is, a part of the second region 14 is formed so as to overlap the first region 13. After both ion implantation steps, a heat treatment step is performed to activate the implanted elements.

Then, a base etching process is performed to remove the thermal oxide film 11 and to etch near the surfaces of the inner and outer base layers 13 and 14. The cross section after this step is shown in FIG.

Thereafter, the surfaces of the first and second regions 13 and 14 of the second conductivity type are again thermally oxidized to cover the reoxidized film 15 having a thickness of 500 angstroms or less, and the second conductivity type of each second conductivity type is covered. Impurities on the surfaces of the first region 13 and the second region 14 are taken into the thin reoxidized film 15 to reduce the surface concentration by about one digit.

P or A is formed in the second region 14 of the second conductivity type.
s a 10 ^{2 1} atoms / cm ³ about spreading to the emitter or first
The conductivity type region 16 is formed.

However, in order to complete it as a vertical semiconductor device, for example, Al or Al alloy (Al-S
i, Al-Si-Cu) or the like is deposited by a sputtering process or a vacuum evaporation method to electrically connect to form an electrode.

The flow chart of this series of steps is shown below. a. Thick oxide layer 12 (LOCOS selective oxide layer),
b. Thin thermal oxide film (500 angstroms or less) 1
1, c. Second conductivity type first region (P ⁺ ) 13 and heat treatment,
d. Second region (P) 14 implantation of the second conductivity type and heat treatment, e. A vertical semiconductor element is formed by the reoxidation step and the respective steps of the f second conductivity type first region 16.

In FIGS. 6 and 7, the B concentration and the base diffusion depth (X _j ) on the horizontal axis are taken and the first region 13 and the second region of the second conductivity type are formed.
It is the figure which compared the surface impurity concentration profile by the presence or absence of the etching process of the area | region 14. The dotted line indicates the position of the semiconductor substrate.

The acceleration voltage at the ion implantation step of B is 3
It is 5 KeV.

From this figure, it is clear that the B concentration after the etching process is lower in FIG. 7 after the etching process.

[0021]

As described above, the vertical semiconductor device according to the present invention does not affect other devices of the integrated circuit device,
Further, the required characteristics of the vertical semiconductor element were satisfied without changing the implantation concentration profile, and the BV _EBO characteristics were improved. Conventional withstand voltage of 5.5v is about 1v, that is, about 20
% Improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a conventional vertical semiconductor device.

FIG. 2 is a cross-sectional view showing a manufacturing process of a vertical semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the vertical semiconductor element, following FIG. 2;

FIG. 4 is a cross-sectional view showing the manufacturing process of the vertical semiconductor element, following FIG. 3;

FIG. 5 is a cross-sectional view showing the manufacturing process of the vertical semiconductor element, following FIG. 4;

FIG. 6 is a diagram showing a B concentration profile on a base surface of a conventional vertical semiconductor device.

FIG. 7 is a diagram showing a B concentration profile on the base surface of the vertical semiconductor element of the present invention.

[Explanation of symbols]

 10: Semiconductor substrate, 11: Thermal oxide film, 12: Selective oxide layer, 13: First region of the second conductivity type, 14: Second region of the second conductivity type, 15: Reoxidation film, 16: First A first region of conductivity type.

Claims (1)

[Claims] 1. A semiconductor substrate of the first conductivity type, a selective oxide layer selectively located on the semiconductor substrate, a thermal oxide film exposed between the selective oxide layers, and a single thermal oxide film inside. To the first region of the second conductivity type, a second region of the second conductivity type of low concentration which partially overlaps the first region of the second conductivity type and goes inward from the thermal oxide film, and the second region of the second conductivity type. Conductive type second
A re-oxidation film covering the surface of the region and the first region, a region of the first conductivity type located in the second region of the second conductivity type, and an electrode electrically connected to each region. Characteristic vertical semiconductor device