JP2976665B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a bipolar transistor and a semiconductor element and a method of manufacturing the same.

2. Description of the Related Art Conventionally, a bipolar transistor and a MOS transistor, particularly a complementary MO, are formed on one semiconductor substrate.
In a so-called BiCMOS semiconductor device in which an S transistor is formed, particularly, the yield of a bipolar transistor greatly affects the yield of a semiconductor device. In particular, insufficient junction reverse breakdown voltage between the high-concentration collector region and the base region of a bipolar transistor is a major factor in lowering the yield.

FIG. 3 is a sectional view showing an example of a conventional BiCMOS semiconductor device. An N @ + -type buried layer 2 is selectively formed in a P-type silicon substrate 1 in a PMOS portion and a bipolar portion. Further, a P + type buried layer 3 is selectively formed in the NMOS portion. Then, an N-type epitaxial layer 4 is grown on the P-type silicon substrate 1. Further, the P-type well region 5 reaching the P + buried layer 3 from the surface of the N-type epitaxial layer 4 is used for the NMOS portion, and the N-type well region 5 reaching the N + buried layer 2
The mold well region 6 is selectively formed in the PMOS portion. or,
In order to electrically isolate the elements from each other and to separate a base region and a collector region, which will be described later, of the bipolar portion, a separation silicon oxide film is formed therebetween by selective oxidation.

Then, a gate silicon oxide film 8 is formed on the surface of each element, a polycrystalline silicon film is deposited on the entire surface of the substrate at 4000 to 6000 A, and the polycrystalline silicon film is selectively etched, A gate polycrystalline silicon film 9 is formed in the PMOS portion and the NMOS portion. Then, a P-type impurity such as boron is ion-implanted using a photoresist film (not shown) covering the base region of the bipolar portion as a mask material to form a P-type base region 12. or,
A photoresist film (not shown) is formed so as to cover the NMOS portion and the bipolar portion other than the collector formation region, and N-type impurity ions such as arsenic are implanted, and an N + type source / drain region 13 is formed in the NMOS portion in the bipolar portion. Simultaneously form an N + type collector region 14. Further, a P + type source / drain region 15 is formed in the PMOS portion and a P + type graft base region 16 is formed in the bipolar portion by selective ion implantation of a P type impurity.

Thereafter, a silicon oxide film 17 is deposited over the entire surface of the substrate, an emitter forming region is opened, an emitter polycrystalline silicon film 18 is formed, and an N-type impurity such as arsenic is formed through the emitter polycrystalline silicon film 17. Is implanted into N +
A mold emitter region 19 is formed. In addition, PS
An aluminum electrode 21 is connected by depositing a G film 20 and opening an electrode extraction portion.

In such a conventional semiconductor device, a P-type base region 12 and an N + type collector region 14 of a bipolar transistor are formed by an isolation silicon oxide film 7A formed by selectively oxidizing the surface of a semiconductor substrate. Thus, the interval between the P-type base region 12 and the N + -type collector region 14 is ensured to prevent the collector-base junction breakdown voltage from deteriorating. The distance between P-type base region 12 and N + -type collector region 14 is determined by the width of isolation silicon oxide film 7A.

However, in this structure, in the selective oxidation step in forming the above-mentioned isolation silicon oxide film 7A, lattice defects due to stress due to oxidation are likely to occur in the collector-base junction, and this defect is caused by the collector-base junction. And causes a new cause of deterioration of the junction breakdown voltage, which causes a problem of lowering the yield and lowering the reliability of the bipolar transistor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which prevent the deterioration of the junction breakdown voltage.

According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device in which a MOS transistor and a bipolar transistor are formed on the same semiconductor substrate, a first conductivity type region provided on a surface of the first conductivity type region of the semiconductor substrate and having a higher concentration than the first conductivity type region And a high-concentration collector region of the bipolar transistor, and a second conductive type impurity region adjacent to the high-concentration collector region .
A semiconductor device having a conductive film on a semiconductor substrate between a base region of a transistor and a distance between the high-concentration collector region and the base region is set by a width dimension of the conductive film.

The conductive film is a polycrystalline silicon film,
Is a high-level material such as W, MO, Ta, etc., instead of a polycrystalline silicon film.
A melting point metal may be used .

Further , a method of manufacturing a semiconductor device according to the present invention
At least a semiconductor device including a bipolar transistor
In the manufacturing method, on the first conductivity type region of the semiconductor substrate,
Is a high concentration collector of the bipolar transistor.
On the boundary between the base region and the base region via an insulating film.
Forming a conductive film, a first photoresist and
Using the conductive film as a mask, the second conductive
Of forming a base region by ion-implanting a mold impurity
And using the second photoresist and the conductive film as a mask.
The impurity of the first conductivity type in the region to be the high concentration collector.
And ion implantation.

First, as shown in FIG. 1A, an N + type buried layer 2 and a P + type buried layer 3 are selectively formed on a P type silicon substrate 1, and an N type epitaxial layer 4 is grown thereon. . Next, a P-type well region 5 reaching the P @ + -type buried layer 3 is formed in a region where an NMOS transistor is formed, and an N-type well reaching to the N @ + -type buried layer 2 is formed in a region where a PMOS transistor and a bipolar transistor are formed. Forming region 6;
Further, an isolation silicon oxide film 7 of 5000 to 15000 A is selectively formed between each transistor to electrically insulate each transistor.

Next, as shown in FIG. 1B, a 100-1000 A gate silicon oxide film 8 is formed on the surface of the silicon substrate 1, and a 4000-6000 A polycrystalline silicon film is deposited on the entire surface of the substrate. By selectively etching the crystalline silicon film, the PMOS portion and the NMO
A gate polycrystalline silicon film 9 is formed in the S portion. At the same time, a collector / base separation polycrystalline silicon film 9A having a width of 0.5 to 10 μm is formed also on the gate silicon oxide film 8 between the collector and the base in the bipolar portion. Thereafter, the polycrystalline silicon film is oxidized to form a silicon oxide film 10 on each surface. Further, as shown in FIG. 1C, a photoresist film 11A is formed in a portion other than the base region of the bipolar portion, and a P-type impurity such as boron is ion-implanted using the photoresist film 11A as a mask material to form a P-type base region 12. . At this time, the P-type base region 12 is formed in a region surrounded by the isolation silicon oxide film 7 and the collector / base isolation polycrystalline silicon film 9A.

Next, as shown in FIG. 1D, a photoresist film 11B is formed in portions other than the NMOS portion and the collector region of the bipolar transistor, and N-type impurities such as arsenic are ion-implanted using the photoresist film 11B as a mask material. A + type source / drain region 13 and an N + type collector region 14 are formed.
At this time, in the bipolar transistor portion, the distance between the P-type base region 12 and the N + -type collector region 14 is determined by the width of the collector / base separation polycrystalline silicon film 9A.

Further, as shown in FIG. 1E, a photoresist film 11C is formed in a portion except for a part of the PMOS portion and the bipolar transistor portion, and this is used as a mask material to form the PMOS film 11C.
P-type impurities such as boron are ion-implanted into the P + -type graft base region of the bipolar transistor and the bipolar transistor to form a P + -type source / drain region 15 and a P + -type graft base region 16.

Then, as shown in FIG. 1F, a silicon oxide film 17 is deposited on the entire surface of the substrate, an emitter formation region is opened, and an emitter polycrystalline silicon film 18 is formed. N-type impurities such as arsenic are ion-implanted through the emitter polycrystalline silicon film 18 to form an N @ + -type emitter region 19. Further, a PSG film 20 is deposited on the entire surface of the substrate.
Connect.

In the semiconductor device formed as described above, the P-type base region 12 of the bipolar transistor and the N +
Separation from the collector 14 is performed, whereby the interval between the P-type base region 12 and the N + -type collector region 14 is ensured to prevent deterioration of the collector-base junction breakdown voltage.
In this case, since the P-type base region 12 and the N + -type collector region 14 can be separated without performing selective oxidation on the silicon substrate, no lattice defect occurs, and the collector-base junction breakdown voltage can be reduced. Factors of deterioration can be eliminated, and a decrease in yield and reliability of the bipolar transistor can be prevented. Thereby, the yield of the semiconductor device is also improved. Incidentally, the wafer yield of the apparatus manufactured according to the prior art was about 45%, but according to the present invention, the wafer yield was about 60%.
The yield improved.

FIG. 2 is a sectional view of a second embodiment of the present invention, in which the same parts as those of the first embodiment are denoted by the same reference numerals.
In this embodiment, when the graft base region 16 and the N @ + type collector region 14 in the bipolar transistor are adjacent to each other, they are separated by a collector / base separation polycrystalline silicon film 9A formed on a silicon substrate. The distance between the two is determined by the width of the base isolation polycrystalline silicon film 9A. As a result, as in the first embodiment, the occurrence of lattice defects due to the selective oxidation is suppressed, the deterioration of the collector-base junction breakdown voltage is eliminated, and the reduction in the yield and reliability of the bipolar transistor can be prevented.

The present invention is not limited to the case where the collector region and the base region are adjacent to each other, and can be applied to the separation between the collector region and all the impurity regions adjacent thereto.
In order to lower the resistance and increase the operation speed of the transistor electrode, a high-melting-point metal film may be integrally formed on the polycrystalline silicon film.

The polycrystalline silicon film may have a floating potential or a ground potential.

As described above, according to the present invention, a polycrystalline silicon film formed on a semiconductor substrate between a collector region of a bipolar transistor and an impurity region adjacent thereto is formed as an isolation film. It is not necessary to selectively oxidize the silicon substrate when forming the isolation film, preventing the occurrence of lattice defects caused by this selective oxidation, and improving the junction breakdown voltage between the collector region and the adjacent impurity region due to the lattice defects. However, there is an effect that it is possible to prevent a decrease in the yield and reliability of the bipolar transistor.

[Brief description of the drawings]

FIG. 1A ~

FIG. 1F is a sectional view showing the first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a sectional view showing a part of a manufacturing process according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

1. 1. P-type silicon substrate N + type buried layer
3. P + type buried layer 4. N-type epitaxial layer 5. P
Mold well region 6. 6. N-type well region 8. Separated silicon oxide film Gate polycrystalline silicon film 9A Collector / base separated polycrystalline silicon film 12. P-type base region 13. 13. N + type source / drain regions N + type collector region 15. P + type source / drain region 16. P + type graft base region 19. N + type emitter region

Claims (5)

(57) [Claims] 1. A semiconductor device having a MOS transistor and a bipolar transistor formed on the same semiconductor substrate, wherein the MOS transistor and the bipolar transistor are provided on a surface of a first conductivity type region of the semiconductor substrate and have a higher concentration than the first conductivity type region. A high-concentration collector region of the bipolar transistor that is a first conductivity type region and a second conductivity type impurity region that is adjacent to the high concentration collector region.
A semiconductor device, wherein a conductive film is provided on a semiconductor substrate between a base region of the bipolar transistor and a distance between the high concentration collector region and the base region is set by a width dimension of the conductive film. Wherein said conductive film is a semiconductor device according to claim 1 Symbol mounting, characterized in that a polycrystalline silicon film formed simultaneously with the gate electrode of the MOS transistor. 3. The semiconductor device according to claim 1, wherein a refractory metal film is formed on an upper layer of said conductive film. 4. A method of manufacturing a semiconductor device including at least a bipolar transistor, wherein an insulating film is formed on a first conductivity type region of a semiconductor substrate and on a boundary between a region serving as a high concentration collector and a region serving as a base of the bipolar transistor. Forming a conductive film via a first photoresist and the conductive film as a mask to form a base region by ion-implanting a second conductivity type impurity into the base region; Ion-implanting a first conductivity type impurity into a region to be the high concentration collector using a photoresist and the conductive film as a mask. 5. The semiconductor device according to claim 1, further comprising a first conductivity type MO.
A semiconductor device including an S transistor, wherein a gate electrode of the first conductivity type MOS transistor is formed simultaneously in the step of forming the conductive film, and the first electrode is simultaneously implanted in the step of ion-implanting the impurity of the first conductivity type. 5. The method according to claim 4 , wherein the impurity of the first conductivity type is ion-implanted into the source and drain of the conductivity type MOS transistor.