JPH07336338A - Clock switching circuit - Google Patents

Abstract

PURPOSE:To guarantee data continuity at the time of approaching transmission and reception clocks by generating first and second changeover control signals for a clock switching part based on the coincidence result of a phase comparator part and the monitored result of a phase fluctuation direction monitoring part. CONSTITUTION:The clock switching part 1 receives reception data by the reception clock and prepares three pieces of data with different phases from the received data by the transmission clock. Then, one of the three pieces of the data with different phases is selected by the first and second changeover control signals. In the phase comparator part 2, the phases of the reception and transmission clocks are compared and the coincidence of both is detected. The phase fluctuation direction monitoring part 3 monitors the phase fluctuation direction of the reception and transmission clocks and a control signal generation part 4 prepares the first and second changeover control signals for the clock switching part 1 by the coincidence result of the comparator part 2 and the monitored result of the monitoring part 3. The switching part 1 is controlled by the changeover control signals and coping is performed so as to guarantee final output data against the approach of the rising edges of both reception and transmission clocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock transfer circuit used in a transmission device. The transmission apparatus has a clock transfer circuit that receives the received data by a reception clock synchronized with the received data, transfers the received data to a transmission clock created in the transmission apparatus, and sends the transmission data as transmission data.

In this data processing, loss of data, double reading of data, and the like lead to a decrease in reliability of data. Therefore, a clock transfer circuit for avoiding these is necessary.

[0003]

2. Description of the Related Art A conventional clock changing circuit will be described below with reference to FIGS. FIG. 8 is a diagram showing the configuration of a conventional example circuit. FIG. 9 is a diagram (No. 1) showing the timing of the embodiment in FIG. 8, which corresponds to the case where the phase variation of the transmission clock (SCK) is delayed with respect to the reception clock (RCK).

FIG. 10 is a diagram (part 2) showing the timing of one embodiment in FIG.
This corresponds to the case where the phase fluctuation of (K) advances in the direction of the reception clock (RCK).

Further, the signal names described in both the time charts of FIG. 9 and FIG. 10 correspond to the signal names described in FIG.
First, FIG. 8 will be described. In FIG. 8, 6 is a clock transfer unit, which is composed of four first FFs (flip-flops) 61, second FFs 62, third FFs 64, fourth FFs 66, one INV (inverter) 63, and one selector 65.

In the clock transfer section 6, the received data (SDTi) synchronized with RCK is S-synchronized with RCK.
It is transferred to CK and transmitted as transmission data (SDTo). Reference numeral 7 denotes a phase comparison unit, which includes a rising edge detection section 71 and a rising edge falling edge detection section 72.

The rising edge detecting section 71 produces a signal a which detects the rising edge of RCK from the master clock (RCM) of RCK. In the rise / fall detection unit 72, S
A signal b that detects the rising edge of SCK from the master clock (SCM) of CK and a signal c corresponding to the first switching control signal that detects the falling edge of SCK from SCK (hereinafter referred to as signal c) are generated. .

Further, RCK is RCM (approximately 8 of RCK).
SCK is a clock that is divided from SCM (having a speed that is approximately 8 to 16 times that of SCK).

Reference numeral 8 is a control signal generator, which is a two NAN.
It consists of D81,82 and one FF83. The NAND 81 obtains the NAND product of the signal a and the signal b, and detects the approach between the rising edge of RCK and the rising edge of SCK.
Signal d (hereinafter, referred to as signal d) which is a switching control signal of the above.

In the NAND 82, the NAN of the signal a and the signal c
The D product is obtained, and a signal e which detects the approach between the rising edge of RCK and the falling edge of SCK is created. The FF 83 uses the signal d as a set (S) signal and the signal e as a reset (R) signal to generate a signal f for switching the selector 65.

In the following, the operation of the clock transfer unit 6 shown in FIG. 8 will be described in the case where the SCK phase fluctuation is delayed and in the case where the SCK phase fluctuation is advanced. At this time, SDTi is a positive / negative alternating signal arranged in the order of “H” data 1, “L” data 2, “H” data 3, ... 1-1 When the phase fluctuation of SCK is delayed (Fig. 9) (a) When the rising edge of RCK approaches the rising edge of SCK Signal a is a pulse signal of "H" between the rising edges of RCK. Yes, signal b is'H 'between rising edges of SCK
Signal c is a pulse signal of'H 'between the falling edges of SCK.

Between the point where signal a and signal c match (not shown) to point X where signal a and signal b match, signal d and signal e are always "H", and signal f is ". It becomes L '. In the 1st FF61, SDTi not described is RCK
Latch at the rising edge of and read out data 1, data 2, and data 3 in this order.

The second FF 62 latches the first FF output at the rising edge of SCK and reads out data 1 and data 2 in this order. In the third FF64, the first FF is generated at the rising edge of the clock (inversion SCK) obtained by inverting SCK with INV63.
The output is latched, and data 1, data 2, and data 3 are read in this order.

When read in this way, the second FF 62 and the third FF 62
The output order of the FF64 is the third FF64 and the second FF62. Further, since the signal f is'L ', the selector 65 selects the second FF output on the 0 side and sends out the data 1 and the data 2 in this order.

Therefore, in the fourth FF 66, the second FF output is latched at the rising edge of SCK and the data 1 delayed by a half SCK cycle from the second FF output is sent as SDTo of the final output. (b) When the rising edge of RCK is separated from the rising edge of SCK The following description will focus on the points different from 1-1.

When reaching the point X, the timings of the signal a and the signal b coincide with each other. At this time, the signal d switches to'L ', the signal e maintains'H', and the signal f detects'H 'of the signal d at the point X and switches to'H'.

When separated from the point X, the signal d maintains "H", and the signals e and f also maintain "H". In the first FF 61, data 4 next to data 3, data 5, data 6, ...
・ Read in order.

In the second FF 62, the phase of the rising edge of RCK, which comes after the X point, becomes more advanced than the phase of the rising edge of SCK, so the data 3 is read at the X point, and the data 4 is skipped next. 5, data 6 ...
Read in order.

The third FF 64 reads data 3, data 4, data 5, ... In this order. Further, in the selector 65, since the signal f is'H ', the 1 side is selected, and the data 3 having the shorter data width, the data 4 having the normal width 4 ...

Therefore, in the fourth FF 66, the data 3 is not read because the data width is short, and the data 4 is read next to the data 2, then the data 5, the data 6 ...

In summary, in the fourth FF 66, the data width of the data 3 output from the selector 65 becomes short, so that the data 3 cannot be latched at the rising edge of SCK, and the data 3 from SDTo is Will be missing. 1-2 In the case where the phase variation of SCK advances (FIG. 10) Hereinafter, the points different from the above 1-1 (a) and (b) will be mainly described. 2-1 When the rising edge of SCK approaches the rising edge of RCK Up to point X, the timings of signal a, signal b and signal c do not match, and signal d and signal e are'H ', Signal f
Is'L '.

The first FF 61 reads out SDTi in the order of data 1, data 2, and data 3. The second FF 62 reads data 1, data 2, and data 3 in this order. The third FF 64 reads out data 1, data 2, and data 3 in this order.

When read in this way, the two reading orders are the second FF output and the third FF output. Further, since the signal f is'L ', the selector 65 selects the 0 side, that is, the second FF output, and the selector 65 outputs data 1, data 2, and data 3 in this order.

Therefore, the fourth FF 66 reads the data 1, data 2 ... Which are delayed by a half SCK cycle from the output of the second FF and sets it as the final output SDTo. 2-2 When the rising edge of SCK is far from the rising edge of RCK When the point X is reached, the timings of the signal a and the signal b match. At this time, the signal d switches to'L ', the signal e maintains'H', and the signal f becomes'H 'of the signal d at the X point.
Is detected and switched to'H '.

When the distance from the point X is increased, the signal d maintains "H", and the signals e and f also maintain "H". The first FF 61 reads data 3, data 4, data 5, ... In this order.

In the second FF 62, the data 3 is read twice at the rising edge of SCK at the point X, and the data 3, the data 4, the data 5, ... Are read in this order. In the third FF 64, data 3, data 4, data 5, ... Are read in this order.

Further, in the selector 65, the signal f is'H '.
Therefore, the 1st side, that is, the 3rd FF output is selected, and the data 3 is first output, the data 3 having the next shortest data width, and then the data 4 having the normal data width, the data 5 ...

Therefore, the fourth FF 66 reads the data 3, data 4, ... In summary, in the fourth FF66, the data width of the output of the selector 65 is S
Since the length can be latched at the rising edge of CK, the continuity of SDTo which is the final output can be guaranteed.

[0029]

Therefore, in the conventional technique, when the phase fluctuation of SCK is delayed relative to RCK, the first rising edge of RCK and SC
There is a problem that data loss occurs when the falling edge of K approaches.

According to the present invention, regardless of whether the phase fluctuation of SCK is delayed or advanced with respect to RCK,
It is an object of the present invention to provide a clock hand-over circuit in which the continuity of data is guaranteed even when the rising edge of RCK and the falling edge of SCK are approached for the first time.

[0031]

In order to achieve the above-mentioned object, in the first invention, as shown in FIG. 1, at least three receiving data are received by a receiving clock, and the receiving data are out of phase with each other by the transmitting clock. Comparing the phases of the reception clock and the transmission clock with the clock transfer unit 1 that creates data and selects one from at least three data having different phases by the first and second switching control signals. , A phase comparison unit 2 that detects the coincidence of the two phases, a phase fluctuation direction monitoring unit 3 that monitors the phase fluctuation direction of the reception clock and the transmission clock, and a matching result and phase fluctuation of the phase comparison unit 2. A control signal generation unit 4 for generating the first and second switching control signals for the clock transfer unit 1 based on the monitoring result of the direction monitoring unit 3.
Is provided to avoid missing of data in the transmission data and double reading.

In the second aspect of the invention, as shown in FIG. 2, the phase comparator 2 includes a rising edge detector 21 for detecting a rising edge of the receive clock and a rising edge for detecting a rising edge or a falling edge of the transmit clock. It is configured to include the falling detection unit 22.

Further, in the third invention, as shown in FIG.
The clock transfer unit 1 includes a first latch unit that captures received data with a receive clock, a second latch unit that captures an output of the first latch unit with a transmit clock, and the first latch unit.
Third latch means for fetching the output of the latch means with the inverted transmission clock, fourth latch means for fetching the output of the third latch means with the transmission clock, and output of the third latch means and output of the fourth latch means. First selecting means for selectively outputting one of the outputs based on the second switching control signal, and one of the output of the second latching means and the output of the first selecting means for the first switching control signal. The control signal generation unit 4 has a second selection means for selectively outputting based on the transmission clock, and a fifth latch means for taking the output of the first selection means with the transmission clock to obtain transmission data. The second switching signal is generated so that the output of the third latch means / the output of the fourth latch means is selected by the first selecting means in accordance with the phase lead / lag. To so that configuration.

[0034]

As shown in FIG. 1, in the first invention, the clock transfer section 1 receives the received data by the received clock and produces at least three data having different phases from the received data by the transmitted clock. , A second switching control signal that causes the phase to differ by at least 3
One is selected from the two data, and the phase comparison unit 2 compares the phases of the reception clock and the transmission clock to detect the coincidence of the two phases.

The phase fluctuation direction monitoring unit 3 monitors the phase fluctuation directions of the reception clock and the transmission clock, and the control signal generation unit 4 monitors the phase fluctuation unit 2.
On the basis of the result of coincidence with the phase change direction monitoring unit 3 and the first and second clock changing units 1
The switching control signal of is generated.

Therefore, by controlling the clock hand-over section 1 by the first and second switching control signals, the first time can be obtained in the case where the phase fluctuation of the transmission clock is delayed and the phase fluctuation thereof is advanced. It is possible to cope with the approach of the rising edge of the reception clock and the rising edge of the transmission clock so that the final output data can be guaranteed.

Furthermore, in the third invention, as shown in FIG. 2, the first latch means provided in the clock transfer section 1 fetches the received data by the received clock, and the second latch means uses the first latch means. Output by the transmission clock, the third latch means captures the output of the first latch means by the inverted transmission clock, and the fourth latch means acquires the third output by the third latch means.
The output of the latch means is taken in by the transmission clock.

Further, the first selecting means selectively outputs either one of the output of the third latch means and the output of the fourth latch means based on the second switching control signal, and the second selecting means performs the output. One of the output of the second latch means and the output of the first selecting means is selectively output based on the first switching control signal, and the fifth latch means obtains the output of the second selecting means by the transmission clock. And send it as transmission data.

Therefore, the output of the fourth latch means is made effective for the phase delay of the transmission clock with respect to the reception clock, and the output of the third latch means is made effective for the phase advance of the transmission clock. By controlling the first selecting unit with the second switching signal, it becomes possible to prevent the loss of data that occurs when the phase of the transmission clock advances / lags with respect to the reception clock.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention will be described below with reference to FIGS. It should be noted that, for those having the same configuration or operation as those of the conventional example shown in FIGS. 1. Description of the First Embodiment: See FIGS. 2 to 4. FIG. 2 is a diagram showing the configuration of an embodiment circuit of the present invention, and FIG. 3 is a diagram (No. 1) showing the timing of the embodiment in FIG. FIG. 4 is a diagram (No. 2) showing the timing of the embodiment in FIG.

Further, FIG. 3 corresponds to the case where the phase fluctuation of the transmission clock (SCK) advances with respect to the reception clock (RCK), and FIG. 4 shows the phase fluctuation of the transmission clock (SCK) to the reception clock (RCK). It corresponds to the case of moving in the direction of.

Further, the signal names described in both the time charts of FIGS. 3 and 4 correspond to the signal names described in FIG.
Hereinafter, the description will be developed in the order of FIGS. 2, 3, and 4. In FIG. 2, reference numeral 1 denotes a clock transfer unit, which includes five first Fs.
F11, 2nd FF12, 3rd FF14, 4th FF15, 5th FF
18, one INV 13, and two first selectors 16,
It comprises a second selector 17.

The clock transfer unit 1 will be described in detail later.
Then, based on the first FF output, three signals of a second FF output, a third FF output and a fourth FF output having different phases are created, and the three signals are switched to make an SCK asynchronous with RCK.
And is sent as normal SDTo.

Each of the circuits 21 and 22 corresponds to the phase comparison unit 2 which detects the coincidence of the rising edge of RCK and the rising edge or falling edge of SCK, 21 is a rising detection unit, and 22 is a rising rising edge. It is a fall detector.

In the rising detection section 21, the RCM to RCK
The output A is generated by detecting the rising edge of. The rising / falling detection unit 22 produces an output B in which the rising edge of SCK is detected from the SCM, and from the SCM to the SC.
The output C is generated by detecting the falling edge of K.

Furthermore, RCK and RCM, SCK and SCM
The speed ratio is about 8 to 16 times, which is the same as the conventional example. Each of the circuits 31 and 32 corresponds to the phase fluctuation direction monitoring unit 3 for monitoring the direction of the phase fluctuation of SCK with respect to RCK, 31 is a phase identification pulse generation unit, and 32 is a phase fluctuation direction determination unit. is there.

In the phase identification pulse generator 31, the SCM and S
Two latch signals (LAT1 and LAT2) which are pulse signals which are synchronized with SCK and have different phases are generated from CK.
In the phase fluctuation direction determination unit 32, the LAT 1 and LA
The phase difference between the output A generated from T2 and RCK is judged and the judgment result signal D and signal E are generated.

The signal D = 'H' detects each level of LAT1 and LAT2 at the rising edge of RCK, and LAT1
= 'H', LAT2 = 'L' to LAT1 = 'H', L
Obtained when AT2 = 'H'.

The signal E = 'H' detects each level of LAT1 and LAT2 at the rising edge of RCK, and LAT1
= 'H', LAT2 = 'H' to LAT1 = 'L', L
AT2 = 'H' Obtained when rolling.

At this time, "H" of the signal D indicates the case where the phase fluctuation of the SCK lags behind RCK, and "H" of the signal E indicates the case where the phase fluctuation of the SCK leads the RCK. Reference numeral 4 is a control signal generation unit, which includes two NAND4s.
It consists of 1, 42, two 6th FF43 and 7th FF44.

In the NAND 41, the NAND product of the output A and the output B is taken, and the rising edge of RCK and SCK
Signal A (negative polarity) that detects the approach of the rising edge of

In the NAND 42, the NAND product of the output A and the output C is taken, and the rising edge of RCK and SCK
Signal B (negative polarity) that detects the approach of the falling edge of

In the sixth FF 43, when the signal A changes from'H 'to'L', the signal C changes from'L 'to'H'. Also, when the signal B changes from'H 'to'L', the signal C changes from'H 'to'L'. The signal C serves as a first switching control signal for the second selector 17.

In the seventh FF 44, when the signal D changes from'H 'to'L', the signal F changes from'L 'to'H'. Further, when the signal E changes from'H 'to'L', the signal F changes from'H 'to'L'. The signal F serves as a second switching control signal for the first selector 16.

Hereinafter, a case where the phase fluctuation of the SCK is delayed will be described with reference to FIG. 3, and a case where the phase fluctuation of the SCK is advanced will be described with reference to FIG. At this time, SDTi
Is a positive / negative alternating signal that follows in order of'H 'data 1,' L 'data 2,' H 'data 3, ...
This is as in the conventional example. 1-1 In the case where the phase fluctuation of SCK is delayed (FIG. 3) Since the sixth FF43 is initially reset, the signal F is always'L ', and the first selector 16 selects the output of the fourth FF15 on the 0 side. is doing. (a) When the rising edge of RCK approaches the rising edge of SCK The rising edge of RCK and the rising edge of SCK match from the point where the rising edge of RCK and the falling edge of SCK match (not shown). Up to point X
Since the signals A and B are both “H”, the signal C is “L”,
The second selector 17 is valid on the 0 side and invalid on the 1 side, and the output of the first selector 16 does not pass through the second selector 17.

At this time, in the fifth FF 18, the second selector 17
Output (output of the second FF12) is latched by SCK, and data 1 delayed by one SCK cycle from the second FF output is used as the final output SDTo. (b) When the rising edge of RCK is more distant from the rising edge of SCK At the point X where the rising edge of RCK and the rising edge of SCK match, the signal C switches from'L 'to'H', and the second selector 17 is the output from the first selector 16 (fourth
Output of FF15) is selected.

At the point Y, the phase fluctuation direction judging unit 32 judges that the phase fluctuation of the SCK is in the direction behind the RCK, and the signal E becomes'L 'by 1 RCK cycle width.
Alternatively, since the signal F remains'L ', the first selector 16 selects the output of the 0th fourth FF 15.

At this time, the data width of the output from the second selector 17 is the data length that can be latched at the rising edge of SCK in the fifth FF 18. 5th after point X
In the FF 18, the output of the first selector 16 (the fourth FF output) is latched by SCK, and the data 2, data 3, ... Delayed by a half SCK cycle from the fourth FF output are used as the final output SDTo.

Further, at the point Y which the phase fluctuation direction judging unit 32 judges that the phase fluctuation of the SCK is delayed,
The signal E becomes “L” only for 1 RCK, but the “L” is invalid for the seventh FF 44, and the description thereof will be omitted.

Summarizing the above, SDTo is data 1,
It becomes normal data that continues with data 2 ... 1-2 When the SCK phase fluctuation advances (FIG. 4) At the Z point where the SCK phase fluctuation direction determination unit 32 determines that the SCK phase fluctuation advances, the falling edge of the signal D is'L '. Is detected, the signal F is switched from'L 'to'H', and the first selector 16 selects the output of the third FF 14 on the first side. (a) When the rising edge of SCK approaches the rising edge of RCK Up to point Z, signal C is'L 'and signal F is'L'.
Is. At this time, the second selector 17 is on the 0 side, that is, the second FF.
Twelve outputs are selected, and the fifth FF 18 outputs data 1 which is delayed by a half SCK cycle from the second FF output. (b) When the rising edge of SCK is separated from the rising edge of RCK The signal F changes from'L 'to'H' at the Z point, but the change of the signal F from'L 'to'H' is the second. It is invalid for the selector 17.

From the Z point to the X point, the signal C is'L '.
Therefore, the second selector 17 selects the output of the second FF12, and the fifth FF18 sends out the data 2 which is a half SCK cycle behind the output of the second FF.

At the point X, when the rising edge of RCK approaches the rising edge of SCK, the signal C becomes'L '.
From "H", the second selector 17 selects the output of the first selector 16 (the output of the third FF 14).

Therefore, the fifth FF 18 sends data 3, data 4, ... Which are delayed by a half SCK cycle from the output of the third FF. Summarizing the above, in the fifth FF 18, the second selector
Since the data width of the output of 17 is the length that can be latched at the rising edge of SCK, the content can be guaranteed, and SDTo becomes normal data such as data 1, data 2 ... 2. Description of Second Embodiment: See FIGS. 5 to 7. FIG. 5 is a diagram showing the configuration of a circuit of another embodiment of the present invention.
6 is a diagram (No. 1) showing the timing of the embodiment in FIG. 5, and FIG. 7 is a diagram (No. 2) showing the timing of the embodiment in FIG.

FIG. 6 corresponds to the case where the phase variation of the transmission clock (SCK) advances with respect to the reception clock (RCK), and FIG. 7 shows the phase variation of the transmission clock (SCK) to the reception clock (RCK). Corresponds to the case of going forward with respect to.

The signal names described in both the time charts of FIG. 6 and FIG. 7 correspond to the signal names described in FIG.
The description of FIG. 5 will be given below with reference to FIGS. 6 and 7. In FIG. 5, reference numeral 1 denotes a clock transfer unit, which includes five first FFs.
11, 2nd FF12, 3rd FF14, 4th FF15, 5th FF18
It is composed of two first selectors 16 and two second selectors 17.
In addition, INV13 is removed as compared with FIG.

In the first FF11, the input SDTi is RC
Latch by K, and the latch output of the first FF11 is branched into three and added to the second FF12, the third FF14, and the fourth FF15, and based on the intermediate signal of the signals K, L, and M described later, SD
Three latch signals (same as SDTi) with different phases are generated from Ti.

The second FF 12 latches the output of the first FF 11 with the signal K and outputs the output of the first FF 11 to the first selector 16
Add to the 0 side of. In the third FF 14, the output of the first FF 11 is latched by the signal L, and the output of the first FF 11 is added to the 1 side of the second selector 17. Furthermore, in the 4th FF15, the 1st FF
The output of 11 is latched by the signal M, and the output of the first FF 11 is applied to the 1 side of the first selector 16.

The first selector 16 uses the signal F as the second switching control signal, and if the signal F is'L ', the second FF
Move to select 12 outputs, 4th if signal F is'H '
Moves to select the output of FF15 and outputs the selection result to the second
Add to the 0 side of selector 17.

The second selector 17 uses the signal C as the first switching control signal, and if the signal C is'L ', it moves so as to select the output of the first selector 16, and if the signal C is'H'. It operates to select the output of the 3rd FF14.

In the fifth FF 18, the signal J output from the second selector 17 is transferred to the asynchronous SCK to obtain the final output SDTo. Hereinafter, in the clock transfer unit 1, a circuit for producing the signal C of the first switching control signal and the signal F of the second switching control signal and the signals K, L and M for processing the received data will be described. .

The circuits 23 and 24 correspond to the phase comparison unit 2,
23 is a trailing edge detector, and 24 is a window pulse generator. The falling edge detection section 23 produces the signal A by detecting the falling edge of RCK from the RCM.

The window pulse generator 24 produces the signal G of the window pulse for masking the vicinity of the falling edge of SCK from SCK and SCM. The comparison unit 25 compares the signal A with the signal G. The comparison result is SC
It becomes'L 'when the phase fluctuation of K is delayed, and becomes'H' when the phase fluctuation of SCK is advanced.

Each of the circuits 31 and 32 corresponds to the phase fluctuation direction monitoring unit 3, 31 is a phase identification pulse generation unit, and 32 is a phase fluctuation direction determination unit. In the phase identification pulse generator 31, S
The signal K, the signal L, and the signal M which are in synchronization with the SCK and have different phases are produced from the CM and the SCK.

The phase fluctuation direction judging unit 32 compares the signal K, the signal L and the signal M with the signal A, and if it is judged that the phase fluctuation of the SCK is delayed relative to the RCK, one of them is judged. When the signal H is set to “H” and it is determined that the phase fluctuation of the SCK is in the direction to advance with respect to the RCK, the other signal I is moved to “L”.

The control signal generator 4 switches the signal C of the first switching control signal for switching the second selector 17 of the clock transfer unit 1 and the first selector 16 based on the comparison result of the comparator 25. Signal F of second switching control signal
To make.

At this time, the signal F becomes "L" when the phase fluctuation of the SCK is delayed, and the signal F becomes "H" when the phase fluctuation of the SCK is advanced. Thus, the second
To switch from the state in which the selector 17 selects the output of the first selector 16 and the first selector 16 selects the output of the second FF 12, the phase fluctuation of SCK is delayed relative to RCK and the forward direction is selected. There are two cases.

Furthermore, RCK and RCM, SCK and SCM
The speed ratio is about 8 to 16 times, which is the same as above. 2-1 In the case where the phase fluctuation of SCK is delayed (FIG. 6) The method of making SDTi, RCK, signal A, SCK, signal G, signal K, signal L, signal M shown in FIG. Omitted because it overlaps.

Since the phase fluctuation direction judging unit 32 judges that the phase fluctuation of the SCK is in the delaying direction, the signal F always remains at "L", and the first selector 16 selects the output of the second FF12. .

Up to the point X, since the rising edge of the signal A is within the'H 'section of the signal G, the signal C is'H' and the second selector 17 selects the output of the third FF14.
The signal J output from the selector 17 becomes the output of the third FF 14 synchronized with the rising edge of the signal L.

Therefore, SDTo is the third signal synchronized with the signal L.
The output of FF14 becomes the transmission signal which is latched by SCK. X
When reaching the point, the rising edge of signal A is'H 'of signal G.
Since it is out of the section, the signal C switches from "H" to "L", and the second selector 17 selects the output of the second FF12.

When the signal C switches from "H" to "L" in this manner, the output of the second selector 17 switches to the output of the second FF 12 synchronized with the rising edge of the signal K. Therefore, SDTo is a signal obtained by latching the output of the second FF 12 synchronized with the signal K with SCK.

Summarizing the above, in the fifth FF 18, the second
The data width of the output from the selector 17 is set so that the signal K, the signal L, and the like can be latched at the rising edge of SCK.
Since the time width of the signal M is set, the contents of SDTo can be guaranteed. 2-2 When the SCK phase fluctuation advances (FIG. 7) Since the SCK phase fluctuation direction determination unit 32 determines that the SCK phase fluctuation advances, the signal F changes from “L” to “H”. ', And the first selector 16 selects the output of the fourth FF15.

Up to point X, since the rising edge of the signal A is within the'H 'section of the signal G, the signal C is'H' and the second selector 17 selects the output of the third FF14.
The signal J output from the selector 17 becomes the output of the third FF 14 synchronized with the rising edge of the signal L.

When reaching the point X, the rising edge of the signal A deviates from the "H" section of the signal G, the signal C switches from "H" to "L", and the second selector 17 selects the output of the fourth FF15. To do.

At this time, the signal J switches to the output of the fourth FF15 latched at the rising edge of the signal M, and the signal J
Becomes a signal synchronized with the rising edge of the signal M, and SD
To is a signal obtained by latching the signal J synchronized with the signal M with SCK.

Summarizing the above, in the fifth FF 18, the second
Since the signals K, L and M are set so that the data width of the output of the selector 17 can be latched at the rising edge of SCK, the contents of SDTo can be guaranteed.

[0087]

As is apparent from the above description, according to the present invention, when the clocks are changed, even if the phase variation of the transmission clock is delayed with respect to the reception clock,
It has the effect of being able to respond flexibly even in the direction of travel,
The first approach of the rising edge of the reception clock and the rising edge of the transmission clock ensures the final transmission data, and has the effect of greatly contributing to the improvement of the reliability of the data of the clock transfer circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing a configuration of an embodiment circuit of the present invention.

FIG. 3 is a diagram showing the timing of one embodiment in FIG. 2 (No. 1)

FIG. 4 is a diagram showing the timing of one embodiment in FIG. 2 (No. 2)

FIG. 5 is a diagram showing a configuration of a circuit according to another embodiment of the present invention.

6 is a diagram showing the timing of one embodiment in FIG. 5 (No. 1)

FIG. 7 is a diagram showing the timing of one embodiment in FIG. 5 (No. 2)

FIG. 8 is a diagram showing a configuration of a conventional example circuit.

FIG. 9 is a diagram showing the timing of one embodiment in FIG. 8 (No. 1).

FIG. 10 is a diagram showing the timing of one embodiment in FIG. 8 (No. 2)

[Explanation of symbols]

 1 Clock transfer unit 2 Phase comparison unit 3 Phase fluctuation direction monitoring unit 4 Control signal generation unit 21 Rise detection unit 22 Rise / fall detection unit 23 Fall detection unit 24 Window pulse generation unit

Claims (3)

[Claims] 1. Received data is received by a receive clock, at least three data having different phases are generated from the received data by a transmit clock, and at least three phases are made different by first and second switching control signals. Three
A clock transfer unit (1) that selects one from two data, and compares the phases of the reception clock and the transmission clock,
The phase comparison unit (2) for detecting the coincidence of the two phases, the phase fluctuation direction monitoring unit (3) for monitoring the phase fluctuation directions of the reception clock and the transmission clock, and the phase comparison unit (2) Matching result and phase fluctuation direction monitoring unit
Based on the monitoring result of (3), the clock switching unit (1)
The clock transfer circuit is characterized in that a control signal generator (4) for generating the first and second switching control signals is provided to avoid data loss and double reading in transmission data. 2. The phase comparing section (2) includes a rising edge detecting section (21) for detecting a rising edge of a reception clock and a rising edge falling edge section (22) for detecting a rising edge or a falling edge of a transmission clock. 2. The clock transfer circuit according to claim 1, wherein the clock transfer circuit comprises: 3. The clock transfer unit (1) comprises a first latch means for receiving the received data at the receive clock, and a second latch means for taking the output of the first latch means at the transmit clock.
Latch means, third latch means for fetching the output of the first latch means with an inverted transmission clock, and fourth latch means for fetching the output of the third latch means with the transmission clock
Latch means, first selecting means for selectively outputting one of the output of the third latch means and the output of the fourth latch means based on the second switching control signal, and the output of the second latch means Second selection means for selectively outputting any one of the outputs of the first selection means based on the first switching control signal, and a fifth latch for taking the output of the first selection means by a transmission clock and making it transmission data. The control signal generation section (4) is configured such that the output of the third latch means / the output of the fourth latch means corresponds to the phase lead / lag of the transmission clock with respect to the reception clock. A clock handoff circuit as claimed in claim 1, characterized in that it is arranged to generate the second switching signal so that it is selected by means.