JP4244468B2 - Clock generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock generator that matches the phase of an input clock with the phase of a reference signal such as a horizontal synchronizing signal.
[0002]
[Prior art]
Conventionally, this type of oscillating circuit is generally configured as shown in Japanese Patent Laid-Open Nos. 1-91519 and 10-41796. The configuration will be described below with reference to the drawings.
[0003]
FIG. 3 is a block diagram of a conventional clock generator disclosed in Japanese Unexamined Patent Publication No. 1-91519. In FIG. 3, a clock CK before phase control is input, and inverters 201 to 216 perform inversion and delay processing. The inverters 217 to 220 are for making all the fanouts of the inverters 201 to 208 equal. The outputs of the inverters 209 to 212 that have been inverted and delayed with respect to the clock CK are simultaneously latched by the periodic pulse E in the latches 221 to 225, respectively. FIG. 4 is a waveform diagram of each part in FIG. When E changes with a falling edge as shown in FIG. 4, the output NQ of the latch 223 becomes the H level, the output Q of the latch 224 becomes the H level, and the edge almost coincides with the falling edge of the synchronization pulse E. The output of the inverter 211 (D (data) input of the latch 224) is selected as the clock. Generally, when the output NQ of the n-1 stage latch and the output Q of the n stage latch simultaneously become H level, a signal obtained by inverting the D (data) input of the n stage is a synchronization pulse E. Is selected as a clock having an edge almost simultaneously with the falling edge.
[0004]
In FIG. 3, the inverters 201 to 220, the latches 222 to 225, the AND gates 226 to 233, and the NOR gates 234 to 237 have four stages, but the number of stages is 180 with respect to the input clock CK by the inverters 201 to 208. It is necessary to make a clock delayed by more than ° and set the phase control range to be more than 180 °. For this reason, when the number of inverter stages is set so that the phase control range is 180 ° or more even when a low-frequency clock is input, a plurality of inverters are detected by the detection circuit when a high-frequency clock is input. Output is selected. Therefore, a delay difference occurs between the inverter output selected on the first stage side and the inverter output selected on the rear stage side. As a result, the duty of the output clock T obtained by the logical product by the NAND gate 238 is lost, and the circuit operation Becomes unstable.
[0005]
In order to solve the above problem, Japanese Patent Application Laid-Open No. 10-41796 discloses an optimum operation by calculating the total number of inverter outputs detected by the detection circuit as shown in FIG. 5 and feeding back the calculation result at the next detection. A method of selecting the inverter output only has been proposed.
[0006]
[Problems to be solved by the invention]
However, in the circuit disclosed in Japanese Patent Application Laid-Open No. 10-41796, the circuit scale is increased by using an arithmetic circuit. Furthermore, since the amount of delay in each inverter becomes smaller with the miniaturization of the semiconductor manufacturing process, it is necessary to increase the number of inverter stages. Therefore, the scale of the arithmetic circuit increases accordingly, and the circuit scale itself increases. It is impractical to make a semiconductor circuit. At the same time, an arithmetic circuit is used to select an optimal inverter output. However, the optimal inverter output cannot be determined until a calculation result is obtained, and real-time processing is impossible.
[0007]
The present invention solves the above-mentioned conventional problems, and an object thereof is to provide a method for realizing real-time processing by only selecting an optimum inverter output without using an arithmetic unit having a large circuit scale.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problem, a clock generation circuit according to claim 1 of the present invention includes a plurality of inverters connected in series, each having a substantially constant frequency and a continuous clock supplied to the input of the first stage;
A plurality of latches for latching each output of the inverter with one synchronization pulse;
An inverter output selection circuit that selects an output of the inverter that is a clock having an edge having substantially the same timing as an edge of the synchronization pulse from the outputs of the plurality of inverters by the output of the latch;
A control circuit for switching invalidity and validity of the output of the inverter selected by the inverter output selection circuit;
A clock generation circuit for generating a phase-controlled clock from the output of the inverter selected by the inverter output selection circuit and enabled by the control circuit; and after the output edge of the inverter selected by the inverter output selection circuit A mask signal generation circuit that generates a signal whose level does not change,
Based on the mask signal from the mask signal generation circuit, the control circuit switches between invalidity and validity of the output of the inverter.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS.
[0010]
(Embodiment 1)
FIG. 1 is a diagram showing a clock generator according to Embodiment 1 of the present invention. Each function will be described.
[0011]
Inverters 101-120, latches 121-125, AND gates 126-133 and NOR gates 134-137, AND gates 126-133 for selecting a clock having an edge having the same timing as the edge of the synchronization pulse, and NOR gate 142- Reference numeral 145 is the same as the conventional configuration. Subsequently, AND gates 134 to 141 and OR gates 146 to 149 are circuits for detecting a point at which the synchronized clock is selected. For example, when the synchronous clock is selected from the NOR gate 142, the output of the OR gate 143 is also H, and all the outputs of the subsequent NOR gates 144 to 148 are invalidated by the OR gates 151 to 153. Therefore, the synchronous clock is selected as the output T only from the first detection point of the entire circuit. A timing chart for explaining these operations is shown in FIG.
[0012]
Further, by connecting the modules shown in FIG. 1 in series, it is possible to cope with a case where the clock frequency range is widened. In that case, as shown in signals M (n) and M (n + 1), the effects shown in the present invention can be obtained by propagating the mask signal generated in each module to the subsequent stage.
[0013]
【The invention's effect】
With the above configuration, it is possible to use only a clock having an edge having the same timing as the edge of the synchronization pulse, and it is possible to always generate an optimal clock in a fully automatic and real-time manner. However, it is suitable for semiconductor circuit formation.
[Brief description of the drawings]
FIG. 1 is a block diagram of a clock generator according to a first embodiment of the present invention. FIG. 2 is a timing diagram for explaining the operation of the clock generator shown in FIG. FIG. 4 is a timing diagram for explaining the operation of the clock generator shown in FIG. 3. FIG. 5 is a second block diagram of a conventional clock generator.
101 to 120 Clock delay inverters 121 to 125 Synchronous clock detection latches 126 to 133 Synchronous clock selection AND gates 134 to 137 Synchronous clock selection NOR gates 138 to 145 Synchronization point detection AND gates 146 to 149 Synchronization point detection OR Gates 150 to 154 Multiple synchronization clock output invalid processing OR gate 155 Synchronization clock output NAND gate 156 Synchronization clock output OR gates 201 to 220 Clock delay inverters 221 to 225 Synchronization clock detection latches 226 to 233 Synchronization clock selection AND Gates 234 to 237 Synchronous clock selection NOR gate 238 Synchronous clock output NAND gate 239 Synchronous clock output OR gates 401 to 420 Clock delay inverter 421 425 Synchronization clock detection latches 426 to 433 Synchronization clock selection AND gates 434 to 437 Synchronization clock selection NOR gates 438 to 445 Synchronization point detection AND gates 446 to 449 Synchronization point detection NOR gates 450 to 454 Multiple synchronization clock outputs Invalid processing OR gates 455 to 456 Multiple synchronous clock output count OR gate 459 Synchronous clock output NAND gate 459 Synchronous clock output OR gate 460 Synchronous clock number count circuit 461 Inverter output number increase / decrease determination circuit 462 Shift register

Claims (1)

A plurality of inverters connected in series, each having a substantially constant frequency and a continuous clock supplied to the input of the first stage;
A plurality of latches for latching each output of the inverter with one synchronization pulse;
An inverter output selection circuit that selects an output of the inverter that is a clock having an edge having substantially the same timing as an edge of the synchronization pulse from the outputs of the plurality of inverters by the output of the latch;
A control circuit for switching invalidity and validity of the output of the inverter selected by the inverter output selection circuit;
A clock generation circuit that generates a phase-controlled clock from the output of the inverter selected by the inverter output selection circuit and enabled by the control circuit;
A mask signal generation circuit that generates a signal whose level does not change after the edge of the output of the inverter selected by the inverter output selection circuit;
A clock generator configured to switch invalidity and validity of the output of the inverter by the control circuit based on a mask signal of the mask signal generation circuit.

Images