JP3190888B2 - Synchronization method between paths - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for synchronizing paths, and more particularly to a method for synchronizing paths that receives and synchronizes data transmitted from a transmitting device to two paths.

[0002]

2. Description of the Related Art Conventionally, when synchronous transfer is performed on a line whose distance is equal to or longer than the wavelength of a clock,
Since the influence of the clock skew is large, the flip-flop (hereinafter, referred to as FF) of the receiving apparatus without performing the delay adjustment.
It was difficult to satisfy the set-up time and the hold time.

As one example of the delay adjustment, there is an asynchronous signal synchronization circuit disclosed in Japanese Patent Application Laid-Open No. 5-327676, for example. FIG. 14 is a principle configuration diagram showing a synchronization circuit according to this publication. The FF 501 takes in an asynchronous input signal at the falling edge of the internal clock of the receiving apparatus, the inverter 502 inverts the internal clock, and the rising edge of the internal clock. , A selector 504 for selecting one of these outputs, a switching control circuit 505 for performing switching control of the selector 504 based on a phase difference between an output signal of the selector 504 and an asynchronous input signal, and an output signal of the selector 504. FF5 which takes in the rising edge of the internal clock
06.

In such a configuration, the switching control circuit 5
05 monitors the time difference between the rising edge of the output signal of the selector 504 and the rising edge of the asynchronous input signal. When the difference becomes equal to or less than the predetermined time, the switching control circuit 505 sends the switching control signal CN to the selector 504.
T is issued to cause the selector 504 to switch to selectively output the other FF. By applying this synchronization circuit to the synchronous transfer, the setup time and the hold time of the FF of the receiving device can be satisfied without considering the influence of clock skew. As a result, it is possible to prevent the output signal from becoming uncertain when the input signal is captured by the synchronous clock, and to convert the input signal into a synchronized signal without error.

[0005]

However, in the above-mentioned prior art, the number of input signal paths is limited to one, and synchronization between input signal paths divided into two paths is taken into consideration. Not. Therefore, as shown in FIG. 15, the output signal of the transmitting device 601 is distributed to two paths, and after passing through the first relay circuit 602 and the second relay circuit 603, is combined into one signal in the receiving device 604. When a conventional synchronization circuit corresponding to the first and second relay circuits is applied to the input unit of the reception device 604, depending on the value of the clock skew, capture is performed at the same clock edge timing. In some cases, the rising edge of the output signal is shifted between the paths.

Referring to FIG. 16, when the time ts from the time tr to the time t1 of the rising edge of the asynchronous input signal is longer than a predetermined time, the setup time of the FF 501 is satisfied, and the selector 504 sets the FF 501 to the FF.
Since 501 is selected, the time of the rising edge of the output signal of the FF 506 is t2. However, as shown in FIG. 17, the time tr of the rising edge of the asynchronous input signal
Is close to time t1 and ts is shorter than a predetermined time,
Because the setup time of FF501 is not satisfied,
The selector 504 selects the FF 503. Therefore,
The time of the rising edge of the output signal of the FF 506 is t4
Becomes

As shown in FIG. 18, such edge shift is caused by the first transmitting apparatus 701 and the second transmitting apparatus 702.
This signal also occurs in a configuration in which the first crossbar device 703 and the second crossbar device 704 relay the output signal, and the receiving device 705 receives the output signal. If the capture timing is shifted between the first crossbar device 703 and the second crossbar device 704, the first transmission device 701 and the second transmission device 70 will be synchronized unless synchronization is performed by any means.
When the packets from 2 conflict, the arbitration order is shifted in the round-robin arbitration method.

In such a case, when the receiving device 705 receiving signals from these crossbar devices combines packets from the two routes into one, the arrival times of the packets are shifted from each other, so that the waiting However, there is a disadvantage that the longer the packet length, the longer the waiting time. When the crossbar devices are connected in multiple stages, the packet waiting time becomes longer.

According to the present invention, even if the phase relationship between the input signal and the clock of the receiving device when receiving a packet is slightly different between the two paths due to the influence of clock skew,
It is an object of the present invention to provide means for capturing data at the same clock edge timing.

[0010]

SUMMARY OF THE INVENTION A first method of synchronizing between paths according to the present invention is a method of synchronizing between paths for receiving and synchronizing data distributed from a transmitting device to two paths and transmitted. A first input control unit that receives data transmitted from the transmitting device via a first path, a second input control unit that receives data transmitted via a second path,
An inter-path synchronization circuit, wherein the first input control unit and the second input control unit detect a phase difference between a start signal, which is a data transfer timing from the transmission device, and an internal clock, and as phase difference information A phase difference detection circuit that transmits to the inter-path synchronization circuit, a plurality of synchronization circuits that capture the start signal in synchronization with the internal clock and generate different synchronization timings, and a transmission circuit that is transmitted from the inter-path synchronization circuit. A selector for selecting one of the plurality of synchronization circuits based on the selected signal, a buffer circuit for temporarily storing data from the transmitting device, and fetching the data from the buffer circuit by an output signal of the selector. And a flip-flop as an output signal of each input control unit, wherein the inter-path synchronization circuit includes the first input control unit and the flip-flop. And determining, based on the phase difference information from the phase difference detection circuit of the second input control unit, the synchronization timing at which the rising timings of the signals output by the respective input control units are simultaneous, and determining any one of the plurality of synchronization circuits. The first input control unit and the second input control unit
Are transmitted to the selectors of the input control unit.

According to a second method of the present invention, in the first method of the present invention, the plurality of synchronizing circuits transmit the start signal to a falling edge of the internal clock. A first synchronizing circuit that captures the data at a delay of 0.5 clock cycle and outputs the delayed signal, a second synchronization circuit that captures the signal at the rising edge of the internal clock and outputs the signal delayed by one clock cycle, and And a third synchronizing circuit which takes in at the falling edge and outputs the data with a delay of 1.5 clock cycles.

In a third method for synchronizing between paths, the phase difference detecting circuit may be a method for synchronizing signals between the start signal and the internal clock. Detecting the pulse width as a width, converting the detected pulse width into a DC voltage, classifying the converted DC voltage using a plurality of types of reference voltages, and outputting a digitized signal as the phase difference information. I do.

According to a fourth method for synchronizing between paths, in the first method for synchronizing between paths, the internal clocks of the first input control unit and the second input control unit are the same. It is characterized by using a clock.

According to a fifth aspect of the present invention, in the first aspect of the present invention, the inter-path synchronization circuit holds a value when a reset signal is deasserted. And outputting a select signal through a latch.

In a sixth method for synchronizing between paths according to the present invention, in the method for synchronizing between paths according to the first aspect of the present invention, the inter-path synchronization circuit includes the first input control unit and the second input control unit. And the inter-path synchronization circuit transmits a select signal to a selector in the same input control unit.

[0016]

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. A first input control unit 1 for receiving data transmitted from a transmitting device via a first path, It comprises a second input control unit 2 for receiving data transmitted by the second path, and an inter-path synchronization circuit 3. Since the first input control unit 1 and the second input control unit 2 have the same configuration, the following 11 to 11 provided in the input control unit are provided.
The description regarding 17 applies to the first input control unit 1 and the second input control unit 2 in common. It is assumed that the same internal clock is used for the first input control unit 1 and the second input control unit 2.

The phase difference detection circuit 11 observes the phase difference between the start signal and the internal clock, and sends the observed value to the inter-path synchronization circuit 3. Here, the start signal defines the timing of reading from the buffer 16 when valid data is included in the data signal. This signal also
It is physically arranged in equal length in parallel with the data signal, and a time lag from the data signal can be ignored.

The first synchronizing circuit 12, the second synchronizing circuit 13 and the third synchronizing circuit 14 take in the start signal in synchronization with the internal clock of the input control unit 1 or 2, and output its output to the selector. Send to 15.

The output of the selector 15 is sent to the FF 17 and instructs the timing of taking in the output of the buffer 16.

The buffer 16 has a function of taking in the data signal at the edge of the strobe signal, and temporarily stores the data signal before sending it to the FF 17. Here, the strobe signal is a repetitive waveform that defines the reception timing of the data signal, is physically arranged in parallel with the data signal, and has a negligible time lag from the data signal.

The FF 17 is a flip-flop that takes in the data signal by the edge of the output signal of the selector 15.

The inter-path synchronization circuit 3 includes a first input control unit 1
Difference detection circuit 11 of both the first and second input control units 2
The appropriate synchronization timing is determined based on the output signal of
A select signal is sent to the selectors 15 of both the input control unit 1 and the second input control unit 2.

FIG. 2 is a circuit diagram showing a specific example of the phase difference detection circuit 11 of FIG.

The FF 111 captures the start signal at the rising edge of the pulse of the internal clock. FF112
Captures the output of the FF 111 at the rising edge of the internal clock. Inverter 113 inverts the start signal. The AND circuit 114 outputs the logical product of the output of the FF 112 and the output of the inverter 113. AND circuit 1
The rising pulse output by 14 is output from the rising edge of the internal clock to the rising edge of the start signal.

The low-pass filter 115 is an AND circuit 1
The output of 14 is regarded as an analog signal, and the pulse waveform is smoothed. If the start signal has a regular repeating waveform,
Low-pass filter 115 outputs a DC voltage.

The A / D converter 116 digitizes the output of the low-pass filter 115 using the first reference voltage, the second reference voltage, and the third reference voltage, and outputs P0, P
A quaternary signal of 1, P2, and P3 is output.

FIG. 3 is a circuit diagram showing a specific example of the first synchronization circuit 12 of FIG.

The FF 121 takes in a start signal using the internal clock inverted by the inverter 123. The FF 122 captures the output of the FF 121 using an internal clock.

FIG. 4 is a circuit diagram showing a specific example of the second synchronization circuit 13 of FIG.

The FF 131 takes in a start signal using an internal clock. The FF 132 captures the output of the FF 131 using an internal clock.

FIG. 5 is a circuit diagram showing a specific example of the third synchronization circuit 14 of FIG.

The FF 141 takes in a start signal using the internal clock inverted by the inverter 144. The FF 142 captures the output of the FF 141 using an internal clock. The FF 143 captures the output of the FF 142 using an internal clock.

FIG. 6 is a circuit diagram showing a specific example of the inter-path synchronization circuit 3 of FIG.

The phase difference detection circuit 11 of the first input control unit 1
Outputs the phase difference information P0, P1, and P2, and the phase difference information P output from the phase difference detection circuit 11 of the second input control unit 2.
From 0, P1, and P2, using the OR circuit 31, AND circuit 32, OR circuit 33, and AND circuit 34, the select signal S0 of the selector 15 of the first input control unit 1 and the selector 15 of the second input control unit 2 and Generate S1. The phase difference information P3 output from the phase difference detection circuit 11 is not used in this circuit.

FIG. 7 is a diagram showing the operation of the selector 15 of FIG.

As shown in FIG. 7, when the select signal S1 is at the L level and the select signal S0 is at the L level, the selector 15 selects the first synchronous circuit 12, the select signal S1 is at the L level, and the select signal S0. Is at the H level, the second synchronous circuit 13 is selected, and the select signal S
When 1 is at the H level and the select signal S0 is at the L level, the logic selects the third synchronous circuit 14.

Next, the operation of the embodiment of the present invention will be described with reference to the drawings.

First, the operation of the phase difference detection circuit 11 will be described with reference to FIGS. FIG. 8 is a time chart showing the operation of the phase difference detection circuit 11 of FIG.

The cycle of the start signal is equal to 2 of the internal clock.
And the phase difference from the internal clock is arbitrary. The start signal is FF1 at the rising edge of the internal clock.
After being fetched by the FF 11, the FF 112 outputs it at a timing delayed by one clock cycle. The influence of metastable is avoided by forming the FFs in a two-stage cascade connection.

The AND circuit 114 outputs the logical product of the start signal inverted by the inverter 113 and the output signal of the FF 112. The rising pulse width td of the signal output by the AND circuit 114 is equal to the time from the rising timing of the internal clock to the rising timing of the start signal. That is, td represents the phase difference between the internal clock and the start signal. When the rising edge of the start signal is slightly delayed from the rising edge of the internal clock, td is minimized and its width is almost zero. Also, when the rising edge of the start signal is the latest, that is, when it is slightly ahead of the rising edge of the internal clock,
td becomes the maximum and becomes almost half the width of the cycle of the start signal.

The low-pass filter 115 is an AND circuit 1
The output of 14 is regarded as an analog signal, and the pulse waveform is converted to a DC voltage. The low-pass filter 115 is composed of, for example, a resistor and a capacitor, and the cutoff frequency is set sufficiently lower than the frequency of the internal clock.

The A / D converter 116 digitizes the output of the low-pass filter 115 using the first reference voltage, the second reference voltage, and the third reference voltage, and outputs it. The first reference voltage is 1/4 of the maximum output voltage of the low-pass filter 115, the second reference voltage is 2/4, and the third reference voltage is 3/4.
Is set to 3/4. Thus, the phase difference is classified into the following four patterns P0 to P3.

The output terminal P0 of the A / D converter is at the H level when the output of the low-pass filter is lower than the first reference voltage, and the output terminal P1 is that the output of the low-pass filter is higher than the first reference voltage. H if lower than the reference voltage
At the level, the output terminal P2 is at the H level when the output of the low-pass filter is higher than the second reference voltage and lower than the third reference voltage, and at the output terminal P3, the output of the low-pass filter is higher than the third reference voltage. In this case, it is set to be at the H level.

Therefore, if the time when the internal clock rises and the time when the start signal rises are simultaneous, the phase difference is 0 degree, and when the start signal is delayed by one cycle of the internal clock, the phase difference is 360 degrees. , P0 are at the H level, the phase difference is from 0 to 90.
The range of degrees, 90 degrees to 1 when P1 is at the H level
80 degrees, when P2 is at the H level, 180 degrees to 270 degrees, and when P3 is at the H level, 2
It represents a range of 70 degrees to 360 degrees. However, since the phase difference detection circuit 11 cannot distinguish the phase difference of 360 degrees or more, the range from 0 degrees to 90 degrees is from 360 degrees to 45 degrees.
It can also be expressed as 0 degrees.

Next, the operation of the synchronization circuit will be described with reference to FIGS. 3 to 5 and FIGS. 9 to 11.

FIG. 9 is a time chart showing the operation of the first synchronization circuit 12 of FIG.

The rising pulse width of the start signal is twice the rising pulse width of the internal clock. Time t
The start signal that rises in the vicinity of the inverter 12
FF at the rising edge of the internal clock inverted in 3
It is taken in by 121 and output as a signal rising at t8. Further, this signal is captured by the FF 122 and output as a signal rising at t10.

Here, if the setup time and the hold time of the FF 121 are less than 1/4 of the wavelength of the internal clock, when the start signal rises between t5 and t7, the start signal changes at the internal clock. Since it is separated from the falling edge by １ ／ clock cycle or more, the setup time and the hold time are satisfied, and the FF 121 can reliably capture the start signal. That is, when considering the rising edge t2 of the internal clock as a reference, assuming that the phase difference of one cycle of the internal clock is 360 degrees, when the phase delay of the rising edge of the start signal is from 270 degrees to 450 degrees, the first The synchronizing circuit 12 outputs a synchronizing signal rising at t10.

FIG. 10 is a time chart showing the operation of the second synchronization circuit 13 of FIG.

The start signal rising near time t4 is captured by the FF 131 and output as a signal rising at t6. Further, this signal is captured by the FF 132 and output as a signal rising at t10.

Here, if the setup time and the hold time of the FF 131 are less than 1/4 of the wavelength of the internal clock, when the start signal rises from t3 to t5, the start signal changes at the internal clock. Since it is separated from the rising edge by １ ／ clock cycle or more, the setup time and the hold time are satisfied, and the FF 131 can reliably capture the start signal. That is, when considering the rising edge t2 of the internal clock as a reference, when the phase delay of the rising edge of the start signal is from 90 degrees to 270 degrees, the second synchronization circuit 13 outputs a synchronization signal rising at t10.

FIG. 11 is a time chart showing the operation of the third synchronization circuit 14 of FIG.

A start signal rising near time t2 is captured by the FF 141 and output as a signal rising at t4. Further, this signal is captured by the FF 142 and output as a signal that rises at t6. Further, this signal is captured by the FF 143 and output as a signal rising at t10.

Here, if the setup time and the hold time of the FF 141 are less than 1/4 of the wavelength of the internal clock, when the start signal rises between t1 and t3, the start signal changes at the internal clock. Since it is separated from the falling edge by 1/4 clock cycle or more, the setup time and the hold time are satisfied, and the FF 141 can reliably capture the start signal. That is, when considering the rising edge t2 of the internal clock as a reference, when the leading edge of the rising edge of the start signal advances from 90 degrees to 0 degrees or delays from 0 degrees to 90 degrees, the third synchronization circuit 14 Is t1
A sync signal which rises at 0 is output.

From the above, the first synchronization circuit 12
Is that the delay of the phase of the rising edge of the start signal with respect to the rising edge of the internal clock is
When the angle is 50 degrees, the second synchronization circuit 13 outputs a signal when the phase delay is 90 degrees to 270 degrees.
It can be seen that when the phase delay is from 0 degree to 90 degrees, synchronous signals rising at the same time are output.

The start signal gives a timing for reading the data signal from the buffer 16 by its rising edge. By outputting a regular repetitive waveform in an initialization procedure such as when power is turned on, the start signal is output as described above. It can be used as a means for relatively knowing the phase difference between the internal clock and the data signal.

Next, a method of synchronizing the input control units will be described with reference to FIGS. 6, 7 and 12. FIG.
FIG. 7 is a diagram illustrating a truth value of the inter-path synchronization circuit 3 of FIG. 6.

First, a case will be described in which the phase difference detection circuits 11 of both the first input control unit 1 and the second input control unit 2 detect the same phase difference. In this case, the inter-path synchronization circuit 3 may generate a select signal so as to select the same synchronization circuit.

The H level output of the phase difference detection circuit 11 is P
0, that is, when the phase difference of the start signal with respect to the internal clock is in the range of 0 to 90 degrees, the inter-path synchronization circuit 3 sets the first synchronization circuit as shown in item 1 and FIG. 12 is generated.

The H level output of the phase difference detection circuit 11 is P1
Or P2, that is, when the phase difference of the start signal with respect to the internal clock is in the range of 90 degrees to 270 degrees,
The inter-path synchronization circuit 3 generates a select signal for selecting the second synchronization circuit 13 as shown in items 5, 8 and 7 of FIG.

When the H level output of the phase difference detection circuit 11 is P
3, that is, when the phase difference of the start signal with respect to the internal clock is in the range of 270 degrees to 360 degrees, the inter-path synchronization circuit 3 performs the first synchronization circuit operation as shown in section 12 of FIG. 12 is generated.

Next, a case where the phase output from the phase difference detection circuit 11 differs by 90 degrees between the first input control unit 1 and the second input control unit 2 due to the influence of clock skew will be described. I do. In this case, the phase detected P0
Since P3 has a width of 90 degrees, the maximum phase difference is 180 degrees.

In the present embodiment, the phase difference detection circuit 11 detects the phase difference from 0 to 360 degrees as four values of P0 (from 0 to 90 degrees) to P3 (from 270 to 360 degrees). Since the phase difference of 360 degrees or more is not distinguished, it is applied when the phase difference between the paths is up to 180 degrees.

As a first case, the H level output of the phase difference detection circuit 11 of one input control unit is P0, that is, the phase difference of the start signal with respect to the internal clock is in the range of 0 to 90 degrees, and the other is. When the H level output of the phase difference detection circuit 11 of the input control unit is P1, that is, when the phase difference is in the range of 90 degrees to 180 degrees, the synchronization circuit for the former is the third synchronization circuit 14, and the synchronization for the latter is If the conversion circuit is the second synchronization circuit 13, a synchronization signal with the same clock timing can be obtained in both input control units.

For example, as shown in item 2 of FIG.
The H level output of the phase difference detection circuit 11 of the input control unit 1 is P0, and the phase difference detection circuit 1 of the second input control unit 2
When the H level output of the first circuit is P1, the OR circuit 3 of FIG.
1 is at the L level and the output S1 of the AND circuit 32 is at the H level, so that the inter-path synchronization circuit 3 performs the third synchronization with the first input control unit 1 as shown in FIG. Since the output S0 of the OR circuit 33 is at the H level and the output S1 of the AND circuit 34 is at the L level, the second synchronization circuit 1 is supplied to the second input control unit 2.
Select 3.

Conversely, as shown in item 4 of FIG. 12, the H level output of the phase difference detection circuit 11 of the first input control unit 1 is P1, and the phase difference detection of the second input control unit 2 is performed. Circuit 11
When the H level output of P is P0, the inter-path synchronization circuit 3 selects the second synchronization circuit 13 for the first input control unit 1, and selects the second synchronization circuit 13 for the second input control unit 2. 3 is selected.

In the above combination in which the H level output of the phase difference detection circuit 11 of one input control unit is P0 and the H level output of the phase difference detection circuit 11 of the other input control unit is P1, The synchronization circuit 3 determines that the phase difference of the start signal with respect to the internal clock of the input
It is determined that the angle is not in the range of 450 degrees but in the range of 0 to 90 degrees, and the control is performed so that the third synchronization circuit 14 is selected instead of the first synchronization circuit 12. If it is considered that the phase difference of the start signal with respect to the internal clock of the former input control unit is in the range of 360 degrees to 450 degrees,
This is because the phase difference between the start signals of the input control unit 1 and the input control unit 2 is 360 degrees at the maximum and exceeds the target range of 180 degrees at the maximum.

As a second case, the H level output of the phase difference detection circuit 11 of one input control unit is P1, that is, the phase difference is in the range of 90 to 180 degrees, and the phase difference of the other input control unit is When the H level output of the detection circuit 11 is P2, that is, when the phase difference is in the range of 180 degrees to 270 degrees, a synchronization signal with the same clock timing can be obtained by using the second synchronization circuit 13 for both.

At this time, as shown in item 6 or item 7 in FIG. 12, the inter-path synchronization circuit 3 sets the select signal S0 to the H level and S1 to the L level for both input control units. As shown in (2), the second synchronization circuit 13 is selected.

As a third case, the H level output of the phase difference detection circuit 11 of one input control unit is P2, that is, the phase difference is in the range of 180 to 270 degrees, and the phase difference of the other input control unit is The H level output of the detection circuit 11 is P3,
That is, when the phase difference is in the range of 270 degrees to 360 degrees, the synchronization circuit for the former is the second synchronization circuit 13 and the synchronization circuit for the latter is the first synchronization circuit 12
Then, a synchronization signal with the same clock timing can be obtained in both input control units.

At this time, the inter-path synchronization circuit 3 sets the rect signal S0 to the H level and the S1 to the L level with respect to the input control unit in which P2 is at the H level as shown in item 9 or 11 in FIG.
Level, the second synchronizing circuit 13 is selected, and for the input control unit in which P3 is at the H level, FIG.
As shown in FIG.
Since the L level is output for both 0 and S1, the first synchronization circuit 12 is selected.

As a fourth case, the H level output of the phase difference detection circuit 11 of one input control unit is P3, that is, the phase difference is in the range of 270 to 360 degrees, and the phase difference of the other input control unit is The H level output of the detection circuit 11 is P
0, that is, when the phase difference is in the range of 360 degrees to 450 degrees, the first synchronization circuit 1
If 2 is used, synchronization signals with the same clock timing can be obtained.

At this time, the inter-path synchronization circuit 3 sets the select signals S0 and S1 to the L level for both input control units as shown in item 3 or item 10 in FIG.
As shown in FIG. 7, the first synchronization circuit 12 is selected.

In the above combination where the H level output of the phase difference detection circuit 11 of one input control unit is P3 and the H level output of the phase difference detection circuit 11 of the other input control unit is P0, The synchronization circuit 3 determines that the phase difference of the start signal with respect to the internal clock of the latter input control unit is not in the range of 0 to 90 degrees but in the range of 360 to 450 degrees. Instead, the first synchronization circuit 12 is controlled to be selected. If the latter is considered that the phase difference of the start signal with respect to the internal clock of the input control unit is in the range of 0 to 90 degrees, the phase difference between the start signals of the input control unit 1 and the input control unit 2 is maximum. 360 degrees, up to 180
This is because it exceeds the range of degrees.

As described above, the specific example of the inter-path synchronization circuit 3 has been described with reference to the circuit diagram shown in FIG. 6. Next, another configuration of the inter-path synchronization circuit 3 will be described with reference to FIG.

The start signal gives a timing to read a data signal from the buffer 16 by its rising edge. Therefore, when data transfer is interrupted, a regular pulse waveform is not obtained, and the output waveform of the low-pass filter 115 is not necessarily a direct current.

However, the phase difference can be accurately detected by providing a procedure for continuously outputting a regular pulse for a certain period at the time of initialization when the reset signal is asserted at the time of power-on or the like. FIG. 13 shows another configuration example of the inter-path synchronization circuit 3 in this case. FIG. 13 illustrates the inter-path synchronization circuit 3 of FIG.
FIG. 9 is a circuit diagram showing another specific example of the embodiment. FIG. 13 is different from FIG. 6 in that latches 35 to 38 are added.

In FIG. 13, the select signal S0 output from the OR circuit 31 is output through the latch 35. The select signal S1 output from the AND circuit 32 is
Output through 6. The select signal S0 output from the OR circuit 33 is output through the latch 37. The select signal S1 output from the AND circuit 34 is output through the latch 38. The latches 35 to 38 are controlled by a reset signal, and hold a value when the reset signal is deasserted.

Thus, the select signals S0 and S1 output from the inter-path synchronization circuit 3 are maintained in the state at the time of initialization by using the start signal having a regular pulse waveform at the time of initialization. Even if the data transfer is interrupted and the start signal does not become continuous, the reception timing does not change.

In the above description, the first input control unit 1, the second input control unit 2, and the inter-path synchronization circuit 3
Has been described as being provided inside the receiving device, but may be provided outside the receiving device.

The inter-path synchronization circuit 3 is constituted by the OR circuit 31 and the AND circuit 32 shown in FIG.
The first input control unit 1 and the second input control unit 2 may be provided respectively. Also in this case, P1 of each input control unit is input to the OR circuit 31 of its own input control unit and also input to the AND circuits 32 of the other input control units.

[0083]

As described above, according to the present invention, even if the phase of the received signal and the phase of the internal clock are different from each other by up to 180 degrees between the two input control units connected to different paths, the received clock timing can be adjusted. Since the synchronization can be performed, even if this synchronization circuit is used in, for example, a crossbar device, there is an effect that the order of arbitration does not shift.

Further, when transmitting the phase difference information between the received signal and the internal clock, the pulse width is converted into direct current instead of the pulse edge, and a signal obtained by converting the pulse width into a quaternary signal is used. Since the delay of the information itself can be eliminated, there is an effect that it is not necessary to consider the delay even in a configuration in which the input control units are separated from each other.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a phase difference detection circuit 11 of FIG.

FIG. 3 is a circuit diagram showing a specific example of a first synchronization circuit 12 of FIG. 1;

FIG. 4 is a circuit diagram showing a specific example of a second synchronization circuit 13 of FIG.

FIG. 5 is a circuit diagram showing a specific example of a third synchronization circuit 14 of FIG. 1;

FIG. 6 is a circuit diagram showing a specific example of the inter-path synchronization circuit 3 of FIG. 1;

FIG. 7 is a diagram illustrating an operation of the selector 15 of FIG. 1;

FIG. 8 is a time chart illustrating an operation of the phase difference detection circuit 11 of FIG. 2;

FIG. 9 is a time chart illustrating an operation of the first synchronization circuit 12 of FIG. 3;

FIG. 10 is a time chart illustrating an operation of the second synchronization circuit 13 of FIG. 4;

FIG. 11 is a time chart illustrating an operation of the third synchronization circuit 14 of FIG. 5;

FIG. 12 is a diagram showing truth values of the inter-path synchronization circuit 3 of FIG. 6;

FIG. 13 is a circuit diagram showing another specific example of the inter-path synchronization circuit 3 of FIG. 1;

FIG. 14 is a principle configuration diagram showing a conventional synchronization circuit.

FIG. 15 is a relay diagram when there are two transmission paths in the conventional example.

FIG. 16 is a time chart showing the operation of the conventional example.

FIG. 17 is a time chart showing the operation of the conventional example.

FIG. 18 is a relay diagram by a crossbar device in a conventional example.

[Explanation of symbols]

 Reference Signs List 1 first input control section 11 phase difference detection circuit 111, 112 FF 113 inverter 114 AND circuit 115 low-pass filter 116 A / D converter 12 first synchronization circuit 121, 122 FF 123 inverter 13 second synchronization circuit 131 , 132 FF 14 Third synchronization circuit 141-143 FF 144 Inverter 15 Selector 16 Buffer 17 FF 2 Second input control unit 3 Inter-path synchronization circuit 31, 33 OR circuit 32, 34 AND circuit 35-38 Latch

Claims (6)

(57) [Claims] 1. A method of synchronizing paths that receives and synchronizes data transmitted from a transmitting device to two paths, wherein the data transmitted from the transmitting apparatus through a first path is transmitted. A first input control unit for receiving data, a second input control unit for receiving data transmitted via a second path, and an inter-path synchronization circuit, wherein the first input control unit and the second input The control unit detects a phase difference between a start signal, which is a data transfer timing from the transmitting device, and an internal clock, and transmits a phase difference detection circuit to the inter-path synchronization circuit as phase difference information. One of a plurality of synchronization circuits that capture in synchronization with a clock and generate different synchronization timings, and any of the plurality of synchronization circuits based on a select signal transmitted from the inter-path synchronization circuit. A buffer circuit for temporarily storing data from the transmitting device, and a flip-flop that takes in the data from the buffer circuit according to the output signal of the selector and outputs the data from each input control unit. The inter-path synchronization circuit may be configured such that, based on the phase difference information from the phase difference detection circuits of the first input control unit and the second input control unit, the timings at which the signals output from the respective input control units rise simultaneously. And transmitting a select signal for selecting any one of the plurality of synchronization circuits to the selectors of the first input control unit and the second input control unit. Synchronization method between paths. 2. A plurality of synchronization circuits, wherein the first synchronization circuit captures the start signal at a falling edge of the internal clock and outputs the delayed start signal with a delay of 0.5 clock cycle, and a rising edge of the internal clock. The second that captures at the edge and outputs one clock cycle delayed
And a third synchronizing circuit which takes in the falling edge of the internal clock and outputs it with a delay of 1.5 clock cycles. method. 3. The phase difference detection circuit detects a phase difference between the start signal and the internal clock as a pulse width, converts the detected pulse width into a DC voltage, and converts the converted DC voltage into a plurality of types. Classification using the reference voltage of
2. The method according to claim 1, wherein a digitized signal is output as the phase difference information. 4. The method according to claim 1, wherein the internal clocks of the first input control unit and the second input control unit use the same clock. 5. The inter-path synchronization circuit outputs a select signal via a latch that holds a value when a reset signal is deasserted.
Synchronization method between the described paths. 6. The inter-path synchronization circuit is provided in each of the first input control unit and the second input control unit, and each of the inter-path synchronization circuits transmits a select signal to a selector in the same input control unit. 2. The method according to claim 1, wherein the path is synchronized.