JPH04291848A - Synchronizing pattern detection circuit - Google Patents

Abstract

PURPOSE:To reduce number of circuits required for detecting a synchronizing pattern with respect to the synchronizing pattern detection circuit reading a data of a received signal without any error. CONSTITUTION:The detection circuit is provided with a detection section 1 which receives a reception signal and a predetermined synchronizing pattern sent from a base station to a mobile station, extracts an odd number order or an even number order bit pattern in response to a clock pulse of one symbol among plural bit patterns obtained by shifting the bit pattern of the reception signal by one bit each and plural bit patterns of the synchronizing pattern so as to detect coincidence or dissidence, an adder section 2 adding outputs of each coincidence or dissidence detection, a delay section 3 delaying the sum output of the adder section 2 by one bit, an adder section 4 receiving the output of the adder section 2 and the output of the delay section 3 and adding the outputs, and a comparison section 4 comparing the output of the adder section 4 with a predetermined setting number and outputting the output of the synchronizing pattern when the output is larger than the predetermined setting number.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides synchronization for obtaining reliable data by providing a synchronization pattern before a transmitted signal and detecting the timing for reading the received signal as appropriate data. Related to pattern detection circuits.

0002

2. Description of the Related Art FIG. 4 shows a block diagram of a conventional synchronization pattern detection circuit. FIG. 5 shows a block diagram of a bit pattern of a conventional synchronization pattern detection circuit.

To explain the operation of the circuit with reference to FIG. 4, first, the shift register 15 receives a received signal, which is data having a consecutive 28-bit synchronization pattern before the data, and shifts it 1 bit at a time 28 times. data (
(see FIG. 5) and outputs each data bit by bit to one terminal of each of EXNOR circuits 21-1 to 21-28. EXNOR circuits 21-1 to 21-28
Data of a predetermined synchronization pattern is sent bit by bit to the other terminal of the terminal. Each EXNOR circuit 21-1 to 21-2
1-28 compares the bit part of the synchronization pattern of the data from the shift register 15 with a predetermined synchronization pattern bit by bit, and if they match, outputs from each EXNOR circuit 21-1 to 21-28. “1” is adder 1
6, and if there is a mismatch, each EXNOR circuit 2
1-1 to 21-28 output "0" to the adder 16. However, the outputs from the EXNOR circuits 21-1 to 21-28 are sent as signals that also include data. The adder 16 adds the output data from each EXNOR 21 to 48 and outputs the added result (see FIG. 5) to the comparator 20. The comparator 20 compares the data output from the adder 16 (see FIG. 5) with a predetermined allowable number, and if the output data is larger than the allowable number,
It is detected that it is a synchronous pattern, and if the output data is less than the allowable number, it is detected that it is not a synchronous pattern.

0004

In order to detect the synchronization pattern of a received signal, a conventional synchronization pattern detection circuit compares each bit with a predetermined synchronization pattern on a bit by bit basis. For this reason, the synchronization pattern detection circuit has EX
Since an OR circuit and an adder circuit are required, there is a drawback that the circuit configuration becomes complicated.

[0005]

[Means for Solving the Problems] In the present invention, as shown in FIG. 1, when detecting a synchronization pattern of a received signal between a base station and a mobile station, Synchronization pattern detection that detects a match or mismatch between a bit pattern and a predetermined synchronization pattern bit by bit, adds up the number of matches or mismatches, and detects the synchronization pattern by comparing the size with a predetermined allowable number. In the circuit, upon receiving the received signal and the synchronization pattern, a plurality of odd-numbered or even-numbered bit patterns obtained by shifting the bit pattern of the received signal one bit at a time, and the predetermined synchronization pattern A detection unit 1 detects a match or mismatch between odd-numbered bit patterns and even-numbered bit patterns that are alternately extracted according to the symbol clock among a plurality of bit patterns, and adds the outputs of the detected matches or mismatches. a first adder 2; a delay unit 3 that delays the added output of the first adder 2 by one clock of the received signal; the output and the second
an adding section 4, and a comparing section 5 that compares the output of the second adding section 4 with a predetermined set number to detect a synchronization pattern.
and that it was equipped with.

[0006]

[Operation] The present invention is capable of selecting bit patterns of a plurality of odd or even bits obtained by shifting one bit from a shift register and a plurality of predetermined synchronization patterns according to the timing of a symbol clock. Matching or mismatching is detected between the odd-numbered or even-numbered bit patterns extracted alternately.
Logic circuits and addition circuits can be reduced.

[0007]

Embodiment FIG. 2 is a block diagram of a synchronization pattern detection circuit showing an embodiment of the present invention. FIG. 3 shows a bit pattern diagram of the synchronization pattern detection circuit of the present invention.

Objects that are the same as those in FIG. 4 are given the same numbers, and explanations thereof will be omitted. The operation of FIG. 2 will be explained as follows.

The shift register 15 that receives the received signal shown in FIG. 3A shifts the data of the received signal one bit at a time. Shifting them in order results in 28 pieces of data, and among the 28 pieces of data, 14 odd or even pieces of data (see (b) in Figure 3) are output to one terminal of EXNOR circuits 1 to 14. do.

The selector 18 selects a demodulator (not shown) from among the 28-bit data of a predetermined synchronization pattern.
Depending on the timing of polarity reversal of the clock pulse of one symbol, even numbered data or odd numbered data is selected and 14 pieces of data are sent to EXNOR circuits 1 to 14, respectively.
output to the other terminal.

In 4-phase PSK, one symbol corresponds to 2 bits, so whether the synchronization pattern is an odd number or an even number can be determined from the symbol clock. Therefore, EX
The NOR circuits 1 to 14 compare two pieces of data input bit by bit, and if the two bit data match, output "1" to the adder 16, and if they do not match, "1" is output to the adder 16. 0'' to the adder 16.

The adder 16 adds bits output from the EXNOR circuits 1 to 14, and outputs the added data to one of the flip-flop 17 and the adder 19, as shown in FIG. 3(c). do.

The flip-flop 17 converts the added data to the added data (2) based on the coincidence detection output of the odd-numbered bits of the synchronization pattern of the output of the adder 16 shown in the chart (c) of FIG. 3, and the even-numbered bits of the synchronization pattern. The data added by bit match detection output is sent to flip-flop 1.
7 and one of the adder 19. The flip-flop 17 receives the outputs of the adder 16, which are the added data.
is delayed by one bit, and the output of the flip-flop 17 shown in FIG. 3(d) is output to the other side of the adder 19.

The adder 19 only sees 14 bit data by adding the data obtained with a 1-bit delay in FIG. 3(d) and the data in FIG. 3(c). Since one symbol corresponding to one period of the clock pulse is compared alternately, it is equivalent to handling 28 bit data, and 28 pieces of data can be compared as shown in (e) in Figure 3. The result of the addition is output to the comparator 20.

[0015] The comparator 20 compares the input data with a permissible number indicating a preset number of matches, and if it is larger than the permissible number, it detects a synchronization pattern, and if it is smaller than the permissible number, Detects that it is not a synchronization pattern.

[0016]

[Effects of the Invention] With the synchronization pattern detection circuit of the present invention,
When detecting the synchronization pattern of the received signal, one bit of the synchronization pattern is alternately detected for each bit data, so EXNOR circuits and adder circuits, etc. can be reduced.
This greatly contributes to simplifying the circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a block diagram of a synchronization pattern detection circuit showing an embodiment of the present invention.

FIG. 3 is a bit pattern diagram of the synchronization pattern detection circuit of the present invention.

FIG. 4 is a block diagram of a conventional synchronization pattern detection circuit.

FIG. 5 is a bit pattern diagram of a conventional synchronization pattern detection circuit.

[Explanation of symbols]

1 to 14, 21-1 to 21-28, EXNOR circuit 15
, shift registers 16, 19, adder 17, flip-flop 18, selector 20, comparator

Claims (1)

[Claims] Claim 1: When detecting a synchronization pattern of a received signal between a base station and a mobile station, the bit pattern of the received signal sent from the base station to the mobile station and a predetermined synchronization pattern are detected bit by bit. A synchronization pattern detection circuit detects a synchronization pattern by detecting a match or a mismatch between the numbers, adding the number of matches or mismatches, and comparing the result with a predetermined allowable number. , a plurality of odd-numbered or even-numbered bit patterns obtained by shifting the bit pattern of the received signal one bit at a time, and a plurality of bit patterns of the predetermined synchronization pattern alternately according to a symbol clock. a detection unit (1) that detects a match or mismatch between the extracted odd-numbered bit pattern and the even-numbered bit pattern; a first addition unit (2) that adds the outputs of the detected match or mismatch; a delay unit (3) that delays the added output of the first adder (2) by one clock of the received signal; and an output of the first adder (2) and an output of the delay unit (3). a second addition unit (4) that adds
and a comparison section (5) for detecting a synchronization pattern by comparing the output of the second addition section (4) with a predetermined set number.