EP1085672A2

EP1085672A2 - Method and system for minimising crosstalk

Info

Publication number: EP1085672A2
Application number: EP00307257A
Authority: EP
Inventors: Masaya Fujimura
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1999-08-23
Filing date: 2000-08-23
Publication date: 2001-03-21
Anticipated expiration: 2020-08-23
Also published as: EP1085672A3; JP3645751B2; EP1085672B1; CA2316514A1; CA2316514C; US6807236B1; JP2001060977A

Abstract

A crosstalk minimising system allowing a reduced number of cables and the downsizing of the transmission equipment. A sending equipment includes a detector for detecting a possible crosstalk timing in each of the data signals by comparing the phases of the clock signals for transmission to the receiving equipment. A receiving equipment includes a read timing shifter for shifting a read timing of each of the clock signals associated with a corresponding data signal to a no-crosstalk timing determined based on the possible crosstalk timing.

Description

The present invention relates to a crosstalk minimising method and system. The method and system will be described below, by way of example, for use in a transmission system that transmits a plurality of pairs of a data signal and a clock signal.
In the case of a plurality of transmission lines that are close together, crosstalk occurs when magnetic fields or current from nearby transmission lines interrupt electrical currents in a transmission line. Since crosstalk causes data error and transmission error, it is very important effectively to minimise crosstalk in a transmission system.
A simple but effective crosstalk minimising method is to transmit a plurality of pairs of data and clock signals through different cables. By ensuring that the pairs of data and clock signals are properly separated from each other, such a system effectively reduces crosstalk, even in the case in which these data signals are not synchronized.
However, such a transmission system needs as many cables as the pairs of data and clock signals. Therefore, the laying of cables has to be done with caution, in order not to generate crosstalk, resulting in a difficult pattern design. Further, it is difficult to achieve a downsizing of transmission equipment in the case in which there is a large number of pairs of data and clock signals.
Features of arrangements to be described below, by way of example in illustration of the present invention are the provision of a method and a system which allow a reduced number of cables and a downsizing of the transmission equipment, and a stable and reliable transmission system with simplified cabling.
A particular system for eliminating crosstalk among a plurality of data signals traveling from sending equipment to receiving equipment through a transmission cable will be described below, by way of example in illustration of the present invention. Clock signals each associated with the data signals are not synchronized with each other.
The sending equipment to be described includes a detector for detecting a possible crosstalk timing in each of the data signals by comparing the phases of the clock signals for transmission to the receiving equipment. The receiving equipment includes a read timing shifter for shifting a read timing of each of the clock signals associated with a corresponding data signal to a no-crosstalk timing determined on the basis of possible crosstalk timing.
The detector may include a leading edge detector for detecting a leading edge timing of each of the clock signals; a trailing edge detector for detecting a trailing edge timing of the clock signal; and a crosstalk timing detector for detecting the possible crosstalk timing in a corresponding data signal based on the trailing edge timing of the clock signal associated with it and the leading edge timings of all clock signals other than the clock signal.
The receiving equipment may include a first data reading section for reading each of the data signals received from the sending equipment according to the no-crosstalk timing to produce a first data signal; and a second data reading section for reading the first data signal according to the read timing of a corresponding clock signal.
In one arrangement to be described by way of example in illustration of the present invention, the sending equipment may include a phase comparator for comparing the phases of the clock signals to produce a phase shift trigger signal indicating a possible crosstalk timing for each of the data signals, for transmitting the phase shift trigger signal to the receiving equipment. The receiving equipment may include a read timing shifter for receiving the phase shift trigger signal and a corresponding clock signal and shifting a read timing of the corresponding clock signal depending on the phase shift trigger signal producing a shifted read timing signal; and a data reading section for receiving the data signal, the corresponding clock signal, and the shifted read timing signal, and reading the data signal according to the shifter read timing signal to produce a first data signal and thereafter reading the first data signal according to the corresponding clock signal to produce a final data signal.
The phase comparator may include a leading edge detector for detecting the leading edge timing of each of the clock signals; a trailing edge detector for detecting a trailing edge timing or the clock signal; a crosstalk timing detector for detecting the possible crosstalk timing in a corresponding data signal based on the trailing edge timing of the clock signal associated with it and leading edge timings of all clock signals other than the clock signal; and a trigger generator for generating the phase shift trigger signal from the possible crosstalk timing, wherein the phase shift trigger signal has a pulse width having the possible crosstalk timing located therein.
The read timing shifter may include a selector for selecting one of the corresponding clock signal and a fixed signal being a logic high level depending on the phase shift trigger signal wherein the corresponding clock signal is selected when the phase shift trigger signal is at a logic low level and the fixed signal is selected when the phase shift trigger signal is a logic high level signal.
The data reading section may include a first flip-flop circuit for reading the data signal according to the shifted read timing signal to produce the first data signal; and a second flip-flop circuit for reading the first data signal according to the corresponding clock signal.
As described above, in the particular arrangement illustrative of the present invention, crosstalk among a plurality of data signals can effectively be removed, or at least minimised. Therefore, a more reliable and stable transmission system can be achieved. Further, the plurality of data signals can be transmitted as a bundle through a single cable, resulting in a reduced number of cables and a downsizing of the transmission system. This causes the design of cabling to be simplified and its cost to be reduced.
The following description and drawings disclose, by means of examples, the invention which is characterised in the appended claims, whose terms determine the extent of the protection conferred hereby.
In the drawings:-
Fig. 1 is a block schematic diagram showing a transmission system employing a crosstalk minimising system,
Fig. 2 is a block schematic circuit diagram showing a phase comparator used in the circuit of Fig. 1,
Fig. 3 is a time chart for use in describing a first operation of the system,
Fig. 4 is a time chart showing a second operation of the system,
Fig. 5 is a detailed block schematic circuit diagram showing a phase comparator used in the circuit of Fig. 2,
Fig. 6 is a time chart showing an operation of the phase comparator shown in Fig. 5,
Fig. 7 is a detailed block schematic circuit diagram showing phase shifters used in the circuit of Fig. 2,
Fig. 8 is a time chart showing an operation of the phase shifters shown in Fig. 7,
Fig. 9 is a detailed block schematic circuit diagram showing data reading sections used in the circuit of Fig. 2, and
Figs. 10A and 10B are time charts showing respective operations of the data reading sections shown in Fig. 7.
Referring to Fig. 1, it is assumed for simplicity that a transmission system includes a sending system and a receiving system 2, which are connected by a single cable 301. The sending system 1 receives a plurality of pairs of data and clock signals, which are not synchronized to each other.
Here, the sending system 1 includes a transmission section 101, a transmission section 102, and a phase comparator 103. The sending system 1 receives a first pair of a data signal 3 and a clock signal 4 through a first transmission line and a second pair of a data signal 5 and a clock signal 6 through a second transmission line.
The transmission sections 101 and 102 receive the input data signals 3 and 4 and clock signals 11 and 12 that are received from the phase comparator 103, and transmits a pair of a data signal 7 and a clock signal 8 corresponding to the first pair and a pair of a data signal 9 and a clock signal 10 corresponding to the second pair.
The phase comparator 103 compares the clock signals 4 and 6 to produce monostable trigger signals 13 and 14, each indicating possible crosstalk timings, at which crosstalk may be generated at the receiving system 2. More specifically, the trigger signal 13 indicates the timing of possible crosstalk from the data signal 9 to the data signal 7 and the trigger signal 14 indicates the timing of possible crosstalk from the data signal 7 to the data signal 9. The details of the phase comparator 103 will be described later.
The sending system 1 transmits a pair of the data signal 7 and the clock signal 8, a pair of the data signal 9 and the clock signal 10, and the trigger signals 13 and 14 to the receiving system 2 through the cable 301. Here, the clock signals 4 and 6 are not synchronized and both clock frequencies are low. The clock signals 8 and 10 are also not synchronized and both clock frequencies are low.
The receiving system 2 includes data processors 201 and 202, phase shifters 203 and 204, and data reading sections 205 and 206. The phase shifter 203 receives the clock signal 8 and the trigger signal 13 indicating the timing of possible crosstalk from the data signal 9 to the data signal 7. Then the trigger signal 13 is output, the phase shifter 203 shifts the phase of the clock signal 8 to the timing at which no crosstalk could be generated to produce a reading clock signal 15. As described later, the amount of the time shift is determined depending on the pulse width of the trigger signal 13. When the trigger signal 13 is not output, the phase shifter 203 outputs the clock signal 8 as the reading clock signal 15. The data reading section 205 reads a first data signal from the data signal 7 according to the reading clock signal 15 having the timing at which no crosstalk could be generated. Thereafter, the data reading section 205 further reads a second data signal 17 from the first data signal according to the clock signal 8 for synchronization with the clock signal 8.
Similarly, the phase shifter 204 receives the clock signal 10 and the trigger signal 14 indicating the timing of possible crosstalk from the data signal 7 to the data signal 9. When the trigger signal 14 is output, the phase shifter 204 shifts the phase of the clock signal 10 to the timing at which no crosstalk could be generated to produce a reading clock signal 16. As described later, the amount of the time shift is determined depending on the pulse width of the trigger signal 14. When the trigger signal 14 is not output, the phase shifter 204 outputs the clock signal 10 as the reading clock signal 16. The data reading section 206 reads a first data signal from the data signal 9 according to the reading clock signal 16 having the timing at which no crosstalk could be generated. Thereafter, the data reading section 206 further reads a second data signal 18 from the first data signal according to the clock signal 10 for synchronization with the clock signal 10.
The respective data processors 201 and 202 process the data signals 17 and 18 output from the data reading sections 205 and 206.
Referring to Fig. 2, the phase comparator 103 is provided with a trailing edge detector 104 and a leading edge detector 105, which detect the trailing edges and the leading edges of the clock signal 4, respectively, and a trailing edge detector 106 and a leading edge detector 107, which detect the trailing edges and the leading edges of the clock signal 6, respectively. The trailing edge timing of the clock signal 4 detected by the trailing edge detector 104 and the leading edge timing of the clock signal 6 detected by the leading edge detector 107 are output to a crosstalk timing detector 108. The trailing edge timing of the clock signal 6 detected by the trailing edge detector 106 and the leading edge timing of the clock signal 4 detected by the leading edge detector 105 are output to a crosstalk timing detector 109.
In the arrangement being described, a data signal changes in synchronization with the trailing edge timing of its clock signal. Therefore, when one of the clock signals 4 and 6 goes low before and after the other goes high, crosstalk is likely to occur. The crosstalk timing detector 108 detects a possible crosstalk timing in the data signal 7 to produce the trigger signal 13. Similarly, the crosstalk timing detector 109 detects a possible crosstalk timing in the data signal 9 to produce the trigger signal 14.
As described later, each of the trailing edge detectors 104 and 106 and the leading edge detectors 105 and 107 includes a delay circuit for delaying the corresponding input clock signal by a predetermined amount. Therefore, the clock signal 4 is delayed by a delay circuit 110 and the delayed clock signal 11 is output to the transmission section 101. Similarly, the clock signal 6 is delayed by a delay circuit 111 and the delayed clock signal 12 is output to the transmission section 102. Therefore, the delayed clock signals 11 and 12 are transmitted as the clock signals 8 and 10 through the cable 301, respectively.

CROSSTALK MINIMISING OPERATION

A crosstalk minimising operation with the data signal 7 will now be described with reference to Fig. 3.
Referring to Fig. 3. it is assumed that the clock signal 4 goes low and the clock signal 6 goes high at time instant t0. In this case, if no crosstalk minimising were made, then, at the receiving system 2, the data signal 7 would be read at the trailing edge timing t2 of the clock signal 8. However, the trailing edge timing t2 of the clock signal 8 is also the leading edge timing of the clock signal 10 corresponding to the clock signal 6. Therefore, the data signal 9 would interfere with the data signal 7 at the timing t2.
The crosstalk timing detector 108 of the phase comparator 103 detects possible crosstalk timing from the trailing edge timing 19 of the clock signal 4 detected by the trailing edge detector 104 and the leading edge timing 22 of the clock signal 6 detected by the leading edge detector 107. The crosstalk timing detector 108 outputs the trigger signal 13 having a pulse width(t1-t3) having the trailing edge timing t2 of the clock signal 8 located therein.
At the receiving system 2, the phase shifter 203 receives the clock signal 8 and the trigger signal 13. If the trigger signal 13 is in a logic level of "0", then the received clock signal 8 is supplied as a reading clock signal 15 to the data reading section 205 because no crosstalk occurs. If the trigger signal 13 is in a logic level of "1", which means that crosstalk may occur, then the phase shifter 203 shifts the trailing edge of the clock signal 8 to the trailing edge timing of the trigger signal 13 to produce a reading clock signal 15 as shown in (c) through (e) of Fig. 3. The trailing edge timing of the trigger signal 13 is located before the corresponding data signal changes. Therefore, the reading clock signal 15 produced by the phase shifter 203 always has the read timing at which no crosstalk occurs.
The data reading section 205 reads a first data signal indicated by reference symbol "A" from the data signal 7 according to the timing of the reading clock signal 15 as shown at (h) of Fig. 3. Thereafter, the data reading section 205 further reads a second data signal 17 from the first data signal A according to the original timing of the clock signal 8 for synchronization with the clock signal 6 as shown in (i) of Fig. 3.
Next, a crosstalk minimising operation in the data signal 9 will be described with reference to Fig. 4.
Referring to Fig. 4, it is assumed that the clock signal 6 goes low and the clock signal 4 goes high at time instant t4. In this case, if no crosstalk minimising were made, then, at the receiving system 2, the data signal 9 would be read at the trailing edge timing t6 of the clock signal 10. However, the trailing edge timing t6 of the clock signal 10 is also the leading edge timing of the clock signal 8 corresponding to the clock signal 4. Therefore, the data signal 7 would interfere with the data signal 9 at the timing t6.
The crosstalk timing detector 109 of the phase comparator 103 detects possible crosstalk timing from the trailing edge timing 21 of the clock signal 6 detected by the trailing edge detector 106 and the leading edge timing 20 of the clock signal 4 detected by the leading edge detector 105. The crosstalk timing detector 109 outputs the trigger signal 14 having a pulse width (t5-t7) having the trailing edge timing t6 of the clock signal 10 located therein.
At the receiving system 2, the phase shifter 204 receives the clock signal 10 and the trigger signal 14. If the trigger signal 14 is at a logic level of "0". then the received clock signal 10 is supplied as a reading clock signal 16 to the data reading section 206, because no crosstalk occurs. If the trigger signal 14 is at a logic level of "1", which means that crosstalk may occur, then the phase shifter 204 shifts the trailing edge of the clock signal 10 to the trailing edge timing of the trigger signal 14 to produce a reading clock signal 16 as shown in (c) through (e) of Fig. 4. The trailing edge timing of the trigger signal 14 is located before the corresponding data signal changes. Therefore, the reading clock signal 16 produced by the phase shifter 204 always has the timing at which no crosstalk occurs.
The data reading section 206 reads a first data signal indicated by reference symbol "B" from the data signal 9 according to the timing of the reading clock signal 16 as shown at (h) of Fig. 4. Thereafter, the data reading section 206 further reads a second data signal 18 from the first data signal B according to the original timing of the clock signal 10 for synchronization with the clock signal 10 as shown in (i) of Fig. 4.
In this manner, crosstalk can effectively be removed from data signals traveling on the cable 301. Therefore, compared with the previous proposals, a plurality of pairs of data and clock signals can be transmitted through a smaller number of cables.

EXAMPLES

Phase comparator

An example of the phase comparator 103 will be described with reference to Figs. 5 and 6.
Referring to Fig. 5, the phase comparator 103, as described with reference to Fig. 2, is provided with the trailing edge detector 104 and the leading edge detector 105, the trailing edge detector P106, the leading edge detector 107, and the delay circuits 110 and 111.
The trailing edge detector 104 includes an inverter and an AND gate that performs a logical AND operation on the delayed clock signal 11 and a clock signal obtained by the inverter, logically inverting the clock signal 4 to produce the trailing edge timing signal 19 of the clock signal 4. The leading edge detector 105 includes an inverter and an AND gate that performs a logical AND operation on the clock signal 4, and a clock signal obtained by the inverter inverting the delayed clock signal 11 to produce the leading edge timing signal 20 of the clock signal 4.
Similarly, the trailing edge detector 106 includes an inverter and an AND gate that performs a logical AND operation on the delayed clock signal 12 and a clock signal obtained by the inverter, logically inverting the clock signal 6 to produce the trailing edge timing signal 21 of the clock signal 6. The leading edge detector 107 includes an inverter and an AND gate that performs a logical AND operation on the clock signal 6 and a clock signal obtained by the inverter, inverting the delayed clock signal 12 to produce the leading edge timing signal 22 of the clock signal 6.
The crosstalk timing detector 106 includes an AND gate and an integrator. The AND gate performs a logical AND operation on the trailing edge timing signal 19 and the leading edge timing signal 22 to produce an AND output signal 23. The integrator performs the integration of the AND output signal 23 to produce the trigger signal 13 having a sufficient pulse width.
The crosstalk timing detector 109 includes an AND gate and an integrator. The AND gate performs a logical AND operation on the trailing edge timing signal 21 and the leading edge timing signal 20 to produce an AND output signal 24. The integrator performs the integration of the AND output signal 24 to produce the trigger signal 14 having a sufficient pulse width.
As shown in Fig. 6, a data signal 3 changes in synchronization with the trailing edge timing of its clock signal 4. Therefore, when the clock signal 4 goes low (L) Just after the clock signal 6 goes high (H). as indicated by reference numeral 601, crosstalk from the data signal 9 to the data signal 7 is likely to occur. As described before, the crosstalk timing detector 108 detects a possible crosstalk timing (AND output 23) in the data signal 7 to produce the trigger signal 13, which has been widened by the integrator 105 to cover the possible crosstalk timing. Similarly, the crosstalk timing detector 109 detects a possible crosstalk timing (AND output 24) in the data signal 9 to produce the trigger signal 14, which has been widened by the integrator 108 to cover the possible crosstalk timing.

Phase shifter

In the receiving system 2, as described before, the phase shifter 203 receives the clock signal 8 and the trigger signal 13 indicating the timing of possible crosstalk from the data signal 9 to the data signal 7 Similarly, the phase shifter 204 receives the clock signal 10 and the trigger signal 14 indicating the timing of possible crosstalk from the data signal 7 to the data signal 9.
Referring to Fig. 7, each of the phase shifters 203 and 204 includes a selector, which selects one of inputs A and B depending on a selection signal S and outputs a selected one as a reading clock signal.
The selector of the phase shifter 203 inputs the clock signal 8 as input A, a fixed signal being a logic state of 3. (high) as input B and the trigger signal 13 as the selection signal S. When the trigger signal 13 is at a level of 0 (low), the selector selects the clock signal 8 to output it as the reading clock signal 15. When the trigger signal 13 is at a level of 1 (high), the selector selects the fixed signal being a logic state of 1 (high) to output it as the reading clock signal 15.
Similarly, the selector of the phase shifter 204 inputs the clock signal 10 as input A, a fixed signal being a logic state of 1 (high) as input B and the trigger signal 14 as the selection signal S. When the trigger signal 14 is at a level of 0 (low), the selector selects the clock signal 10 to output it as the reading clock signal 16. When the trigger signal 14 is at a level of 1 (high), the selector selects the fixed signal, being in a logic state of 1. (high) to output it as the reading clock signal 16.
As shown in Fig. 8, when the clock signal 8 goes low (L) and the clock signal 10 goes high (H), as indicated by reference numeral 801, crosstalk from the data signal 9 to the data signal 7 is likely to occur. Therefore, the crosstalk timing detector 108 produces the trigger signal 13 having a pulse width during which the possible crosstalk timing 801 is included and outputs it to the receiving system 2 as shown in (c) of Fig. 8.
The phase shifter 203 receives the clock signal B and the trigger signal 13 from the sending system 1. If the trigger signal 13 is at a low level "0", then the phase shifter 203 selects the received clock signal 8 as a reading clock signal 15 to the data reading section 205 because no crosstalk occurs. However, if the trigger signal 13 is at a high level "1", then the phase shifter 203 selects the fixed signal being the logic state of High to shift the trailing edge of the clock signal 8 to the trailing edge timing of the trigger signal 13 to produce the reading clock signal 15 as shown at (e) in Fig. 8. Therefore, the reading clock signal 16 produced by the phase shifter 204 always has the reading timing at which no crosstalk occurs. It is the same with the phase shifter 204.

Data reading section

Referring to Fig. 9, the data reading section 205 includes a first flip-flop circuit 901 and a second flip-flop circuit 902. The first flip-flop circuit 901 inputs the data signal 7 at the input D and a clock signal 25 generated by an inverter inverting the reading clock signal 15. The second flip-flop circuit 902 inputs the output 27 of the first flip-flop circuit 901 and the clock signal 8.
Similarly, the data reading section 206 includes a first flip-flop circuit 903 and a second flip-flop circuit 904. The first flip-flop circuit 903 Inputs the data signal 9 at the input D and a clock signal 26 generated by an inverter inverts the reading clock signal 16. The second flip-flop circuit 904 inputs the output 28 of the first flip-flop circuit 903 and the clock signal 10.
As shown in Fig. 10A, the first flip-flop circuit 901 of the data reading section 205 reads a first data signal 27 from the data signal 7 according to the reading clock signal 15. More specifically, even if a crosstalk noise 1001 is generated by the data signal 9, the reading clock signal 15 has the trailing edge timing 1002 at which no crosstalk could be generated. Therefore, the first data signal 27 has no crosstalk noise. However, the first data signal 27 is not synchronized with the original clock signal 8.
Thereafter, the second flip-flop circuit 902 further reads a second data signal 17 from the first data signal 27 according to the clock signal 8 for synchronization with the clock signal 8. In this way, the data signal 17 having no error can be output to the data processor 201.
As shown in Fig. 10B, the first flip-flop circuit 903 of the data reading section 206 reads a first data signal 28 from the data signal 9 according to the reading clock signal 16. More specifically, even if a crosstalk noise 1003 is generated by the data signal 7, the reading clock signal 16 has the trailing edge timing 1004 at which no crosstalk could be generated. Therefore, the first data signal 25 has no crosstalk noise. However, the first data signal 28 is not synchronized with the original clock signal 10.
Thereafter, the second flip-flop circuit 904 further reads a second data signal 18 from the first data signal 28 according to the clock signal 10 for synchronization with the clock signal 10. In this way, the data signal 18 having no error can be output to the data processor 202.
In the above described arrangements there are two pairs of data and clock signals. However, it is apparent that the present invention can be applied to three or more pairs of data and clock signals.
It will be understood that although particular arrangements, illustrative of the invention have been described, by way of example, variations and modifications thereof, as well as other arrangements may be conceived within the scope of the protection sought by the appended claims.

Claims

A system for use in minimising crosstalk among a plurality of data signals traveling from sending equipment to receiving equipment through a transmission cable, in which clock signals, each associated with the data signals, are not synchronized with each other, characterised in that the sending equipment includes a detector for detecting a possible crosstalk timing in each of the data signals by comparing phases of the clock signals for transmission to the receiving equipment, and the receiving equipment includes a read timing shifter for shifting a read timing of each of the clock signals associated with a corresponding data signal to a no-crosstalk timing determined on the basis of the possible crosstalk timing.
A system as claimed in claim 1, wherein the detector includes a leading edge detector for detecting a leading edge timing of each of the clock signals, a trailing edge detector for detecting the trailing edge timing of the clock signal, and a crosstalk timing detector for detecting the possible crosstalk timing in a corresponding data signal based on the trailing edge timing of the clock signal associated with it and leading edge timings of all clock signals other than the clock signal.
A system as claimed in claim 1, wherein the receiving equipment further includes a first data reading section for reading each of the data signals received from the sending equipment according to the no-crosstalk timing to produce a first data, signal, and a second data reading section for reading the first data signal according to the read timing of a corresponding clock signal.
A system for use in minimising crosstalk among a plurality of data signals traveling from sending equipment to receiving equipment through a transmission cable, in which clock signals, each associated with the data signals, are not synchronized with each other, characterised in that the sending equipment includes a phase comparator for comparing the phases of the clock signals to produce a phase shift trigger signal indicating a possible crosstalk timing for each of the data signals, to transmit the phase shift trigger signal to the receiving equipment, the receiving equipment includes a read timing shifter for receiving the phase shift trigger signal and a corresponding clock signal and shifting a read timing of the corresponding clock signal depending on the phase shift trigger signal to produce a shifted read timing signal, and in which there is a data reading section for receiving the data signal, the corresponding clock signal, and the shifted read timing signal, and reading the data signal according to the shifter read timing signal to produce a first data signal and thereafter reading the first data signal according to the corresponding clock signal to produce a final data signal.
A system as claimed in claim 4, in which the phase comparator includes a leading edge detector for detecting a leading edge timing of each of the clock signals, a trailing edge detector for detecting a trailing edge timing of the clock signal, a crosstalk timing detector for detecting the possible crosstalk timing in a corresponding data signal based on the trailing edge timing of the clock signal associated with it and leading edge timings of all clock signals other than the clock signal, and a trigger generator for generating the phase shift trigger signal from the possible crosstalk timing, wherein the phase shift trigger signal has a pulse width having the possible crosstalk timing located therein.
A system as claimed in claim 4, in which the read timing shifter includes a selector for selecting one of the corresponding clock signal and a fixed signal being a logic high level depending on the phase shift trigger signal, the corresponding clock signal is selected when the phase shift trigger signal is a logic low level and the fixed signal is selected when the phase shift trigger signal is at a logic high level.
A system as claimed in claim 6, in which the data reading section includes a first flip-flop circuit for reading the data signal according to the shifted read timing signal to produce the first data signal, and a second flip-flop circuit for reading the first data signal according to the corresponding clock signal.
A method for minimising crosstalk among a plurality of data signals traveling from sending equipment to receiving equipment through a transmission cable, in which clock signals, each associated with the data signals, are not synchronized with each other, characterised in that it includes the steps at the sending equipment of detecting a possible crosstalk timing in each of the data signals by comparing phases of the clock signals to transmit it to the receiving equipment, and the steps at the receiving equipment of shifting a read timing of each of the clock signals associated with a corresponding data signal to a no-crosstalk timing determined based on the possible crosstalk timing.
A method as claimed in claim 8, wherein the step at the sending equipment includes the steps of detecting a leading edge timing of each of the clock signals, detecting a trailing edge timing of the clock signal, and detecting the possible crosstalk timing in a corresponding data signal based on the trailing edge timing of the clock signal associated with it and leading edge timings of all clock signals other than the clock signal.
A method as claimed in claim 8, including the steps at the receiving equipment of reading each of the data signals received from the sending equipment according to the no-crosstalk timing to produce a first data signal, and reading the first data signal according to the read timing of a corresponding clock signal.
A method for minimising crosstalk among a plurality of data signals traveling from sending equipment to receiving equipment through a transmission cable, in which clock signals, each associated with the data signals, are not synchronized with each other, characterised by the steps of at the sending equipment, comparing the phases of the clock signals to produce a phase shift trigger signal indicating a possible crosstalk timing for each of the data signals, to transmit the phase shift trigger signal to the receiving equipment, and at the receiving equipment, receiving the phase shift trigger signal and a corresponding clock signal, shifting a read timing of the corresponding clock signal depending on the phase shift trigger signal to produce a shifted read timing signal, reading the data signal according to the shifter read timing signal to produce a first data signal, and reading the first data signal according to the corresponding clock signal to produce a final data signal.