JPH07254892A - Phase varying circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale of the phase varying circuit which changes the phase of data synchronized with a clock. CONSTITUTION:Contents of input data 11 are stored in a memory 1 in order in accordance with a write clock 12 and are outputted to a means 15 in the storage order. The output timing accords with a read clock 14. Each delay circuit 2 delays the input signal by a certain time and outputs it. N delay circuits 2 have the same extent of delay S1. A selecting circuit 3 selects one of N delay clocks 21 to 21+N in accordance with the value indicated by a select signal 13 and outputs the selected clock as the read clock 14. The phase of the read clock 14 is changed to change the phase of data outputted to the means 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase fluctuation circuit,
In particular, the present invention relates to a phase changing circuit that changes the phase of data synchronized with a clock.

[0002]

2. Description of the Related Art A conventional phase fluctuation circuit includes a distribution circuit 101 and N (N is a natural number) delay circuits 1 as shown in FIG.
02 and a selection circuit 103.

The distribution circuit 101 is a circuit for distributing the input data 11 of M (M is a natural number) bits into N equal M-bit data and outputting the same, and the N outputs 121 are input to the next circuit. It has a buffering circuit inside so that the level can be maintained sufficiently. Each delay circuit 102
Is a circuit which has M delay lines therein and delays and outputs M-bit input data 11 for a predetermined time. The N delay circuits each have their own delay amounts T1 to TN.
The M-bit data 131 to (130 + N) having the above is sent to the selection circuit 103. The selection circuit 103 uses the selection signal 11
According to the value represented by 1, one of N M-bit data 131 to (130 + N) is selected according to the relationship shown in FIG.

FIG. 6 is a diagram showing a time chart for explaining the operation of this phase fluctuation circuit. Note that, in FIG. 6, for simplification of description, of the N delay circuits 102, the delay due to the delay circuits other than the delay circuit 102 for transmitting the M-bit data 131, 132, 133, 130 + N is ignored.

As shown in the figure, N M-bit data 1
31- (130 + N) have delays T1 to TN with respect to the original input data 11, respectively.
By selecting any one from (130 + N), data with various phase changes with respect to the reference clock can be obtained.

[0006]

However, in the above-mentioned conventional phase fluctuation circuit, since the input data is distributed to N pieces and each of them is individually delayed, one is selected, so that the circuit scale is large. There is a problem that it gets bigger.

Therefore, an object of the present invention is to provide a phase fluctuation circuit for changing the phase of data synchronized with a clock,
It is to provide a phase fluctuation circuit having a small circuit scale.

[0008]

According to the present invention, a memory for receiving input data and sequentially storing the contents of the input data in accordance with the output timing of a first control signal as a writing clock, N delay circuits connected in series (N is a natural number) for delaying one control signal by a predetermined time and sending the delay signals, and N delay signals respectively sent from the N delay circuits. ,
And a selection circuit for transmitting a second control signal as a read clock, wherein the first delay circuit of the N delay circuits receives the first signal and outputs the first delay signal. The remaining N-th delay circuit (N is a natural number equal to or greater than 2) receives the (N-1) -th delay signal sent from the (N-1) -th delay circuit, and receives the N-th delay signal. The selection circuit selects any one of the N delay signals according to the selection signal, sends the selected delay signal as the second control signal, and outputs the selected delay signal to the memory. To output the stored data in synchronization with the second control signal in the order in which they are stored.

Further in accordance with the present invention, the memory is F
A phase variation circuit characterized by being an IFO (First In First Out) type memory can be obtained.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram for explaining an embodiment of the present invention. The phase fluctuation circuit according to the present invention comprises a memory 1, N delay circuits 2 and a selection circuit 3.

The memory 1 is a first-in first-out memory, a so-called FIFO (First In First Out).
This is a memory called type t). The contents of the input data 11 input according to the output timing of the write clock 12 as the first control signal are sequentially stored in the memory 1. N delay circuits 2 (N is a natural number)
Are connected in series with each other. Of the N delay circuits 2,
The first delay circuit 2 receives the write clock 12 and delays the write clock 12 for a predetermined time to generate the first clock.
The th delay signal (hereinafter referred to as a delay clock) 21 is sent to the selection circuit 3. The remaining N-th delay circuit (N is a natural number of 2 or more) receives the (N-1) -th delay clock transmitted from the N-1-th delay circuit connected to the immediately preceding N-th delay circuit, respectively. The Nth delay clock is sent to the selection circuit 3. For example, the third delay circuit 2 receives the second delay clock 22 transmitted from the second delay circuit 2 connected immediately before the third delay circuit 2 and receives the third delay clock 22.
The th delay clock 23 is sent to the selection circuit 3.

The selection circuit 3 receives N delay clocks of the delay clocks 21 to (20 + N) respectively sent from the N delay circuits 2 and receives the delay clocks 21 to (20+).
Any one of the delay clocks N) is selected according to the selection signal 13, and the selected one delay clock is sent to the memory 1 as the read clock 14 as the second control signal.

The phase of the input data 11 stored in the memory 1 changes in synchronization with the selected read clock 14, and the phase-changed data 15 after the phase change is output in the stored order. It The output timing follows the read clock 14.

The delay circuit 2 delays the write clock 12 as an input signal for a predetermined time and outputs it to the selection circuit 3 and the delay circuit 2 connected in series next thereto. The N delay circuits 2 have exactly the same delay amount S1 (see FIG. 3).
According to the value represented by the selection signal 13, the selection circuit 3 has N delayed signals 21 to (2
1 + N) is selected and output as the read clock 14.

Next, the operation of the phase fluctuation circuit according to the present invention will be described with reference to FIG. FIG. 3 is a diagram showing a time chart showing the operation of the present invention. It should be noted that, for simplification of description, delays due to circuits other than the first, second, and third delay circuits 2 are ignored. In addition, both the writing and reading operations of the memory 1 show the case where the rising edges of the clocks for writing 12 and the clock for reading 14 are both set.
The same effects of the present invention can be obtained even in the case of falling.

N delay clocks 21 to (21 + N)
Are delayed by the delay amount S1 with respect to the writing clock 12 in order, so that 21 to (21
By selecting any one from + N), the read clock 14 having various phases changed with respect to the write clock 12 is obtained. In accordance with the read clock 14, input data 11 (in the figure, D1, D2,
Read D3, D4). When the selection circuit 3 selects the delay clock 21 as the read clock 14,
As shown in (1), the reference write clock 12
, The post-phase-change data 15 delayed by the delay amount S1 is obtained. When the selection circuit 3 selects the delay clock 22 as the read clock 14, as shown in (2), the delay amount 2S1 with respect to the reference write clock 12 is used.
Data 15 after delayed phase fluctuation is obtained. When the selection circuit 3 selects the delay clock 23 as the read clock 14, the post-phase-change data 15 delayed by the delay amount 3S1 with respect to the reference write clock 12 is obtained as shown in (3). Therefore, in the phase fluctuation circuit having the structure according to the present invention, the data 1 with various phase changes
5 can be obtained.

[0017]

As described above, according to the present invention,
Since the read clock is selected from the signals obtained by sequentially delaying the write clock by a fixed amount using the FIFO type memory, the clock can be generated without using the distribution circuit as in the conventional case. The phase of the data synchronized with can be changed. Therefore, since the distribution circuit is not used, the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an embodiment of a phase fluctuation circuit according to the present invention.

FIG. 2 is a diagram showing an example of selection conditions of a selection circuit shown in FIG.

FIG. 3 is a diagram showing a time chart for explaining the operation of the phase fluctuation circuit according to the present invention.

FIG. 4 is a block diagram for explaining an example of a conventional phase fluctuation circuit.

5 is a diagram showing an example of selection conditions of the selection circuit of FIG.

FIG. 6 is a diagram showing a time chart for explaining the operation of a conventional phase fluctuation circuit.

[Explanation of symbols]

 1 Memory 2 Delay Circuit 3 Selection Circuit 11 Input Data 12 Write Clock 13 Selection Signal 14 Read Clock 15 Phase-Fluctuated Data 21 to (20 + N) Delay Clock

Claims (2)

[Claims] 1. A memory that receives input data and sequentially stores the contents of the input data in accordance with the output timing of a first control signal as a write clock,
N delay circuits connected in series (N is a natural number) for delaying the first control signal by a predetermined time and sending the delayed signals, and N sent from the N delay circuits, respectively.
The second delay signal, which receives the delay signals
Of the N delay circuits, the first delay circuit receives the first signal and outputs the first delay signal, and the remaining Nth delay circuits. The n-th delay circuit (N is a natural number of 2 or more) receives the (N-1) -th delay signal sent from the (N-1) -th delay circuit, and sends the N-th delay signal, and the selection circuit Selects any one of the N delay signals according to a selection signal, sends the selected delay signal as the second control signal, and the memory stores the stored data. A phase variation circuit characterized by outputting in synchronization with a second control signal in the stored order. 2. The phase fluctuation circuit according to claim 1, wherein
The memory is a FIFO (First In First)
Out) type memory.