JPS63173432A - Clock crossing over circuit - Google Patents

Abstract

PURPOSE:To read a data written from a head without error by reading a synchronizing pulse from a phase comparator means and sending it as a reset pulse to a memory means and as an initializing signal to a counting means when the phase of the synchronizing pulse and the output of the counting means are dissident. CONSTITUTION:A W reset pulse synchronously with a W-CK is used and a synchronizing pulse synchronously with the R-CK is generated from a synchronizing pulse generator 3. The phase of the synchronizing pulse and the phase of the output (carry) from the counter 71 are compared by a phase comparator 81 and when they are dissident, the synchronizing pulse is fed from the comparator as a R-reset pulse and the initializing signal to an elastic storage memory 61 and a counter 71. Then a read address reaches an address '0' and the data is read out of the address '0' by the R-CK in the former and the signal is counted up from '0' while being initialized in the latter. That is, the R-reset pulse is generated immediately from the first W-reset pulse, then the written data is read from the head without error.

Description

[Detailed Description of the Invention] [Summary] In a clock switching circuit, a phase comparing means compares the phases of a synchronizing pulse and an output of a counting means, and a comparison output is sent to a memory means and a counting means, thereby detecting a mismatch. This makes it possible to read data after the first write reset pulse without error.

[Industrial application field]

The present invention relates to an improvement in a clock switching circuit, for example, a clock switching circuit using elastic store memory.

FIG. 4 shows a clock switching circuit connection diagram.

In the figure, when receiving and passing data between a first device and a second device, the two devices use clocks CK of different systems that have the same period but are out of phase with each other due to jitter.
-1, CK-2, the clock switching circuit converts data synchronized with the clock CK-1 of the first device to data synchronized with the clock CK-2 of the second device (this (This is called clock switching) and sends it to the second device.

At this time, it is necessary that the data be correct (convertible (readable)) from the beginning.

[Conventional technology]

FIG. 5 is a block diagram of the conventional example, and FIG. 6 is a time chart of the conventional example. Note that the numbers on the left side of FIG. 6 indicate the waveforms of the portions with the same numbers in FIG.

The operation shown in FIG. 5 will be explained below with reference to FIG.

First, the clock switching circuit receives write data as shown in Figure 6-■, a frame synchronization pulse indicating the beginning of this write data, and a write clock as shown in Figure 6-■ (hereinafter abbreviated as W-CK). enters.

Therefore, the write reset pulse generator 1 uses a frame synchronization pulse to generate a write reset pulse as shown in FIG. Add to the synchronous pulse generator 3 composed of

In the former case, an internal counter (not shown) is reset by this pulse, and write data is written into the FiFo2 from address 0 using W-CK.

In the latter case, the clock of the write reset pulse is changed, and the pulse (hereinafter referred to as ``11-GK'') synchronized with the read clock (hereinafter abbreviated as ll-GK) as shown in Figure 6-0 is performed.
A synchronizing pulse (referred to as a synchronizing pulse) is generated and applied to the phase comparator 5.

Here, for example, the 8-bit counter 4 counts R-CK as shown in FIG.
Send to.

Therefore, the phase comparator 5 compares whether the synchronization pulse and the carry phase match or not, and if they do not match, the phase comparator 5
Since the counter is initialized by sending an initialization signal as shown in the first half of ○, the counting operation starts from 0 as shown in FIG.

Then, as shown in the second half of Figure 6-■, when the carry from the counter is sent to FiFo2 and phase comparator 5, FiFo
The address of o becomes 0, and the counter also returns to O due to carry, allowing synchronization with the frame synchronization pulse.

Incidentally, when the phases of the synchronization pulse and the output of the counter 4 match, the initialization signal is not sent out from the phase comparator 5 as shown in the second half of FIG. 6--.

[Problem that the invention seeks to solve]

Here, the carry of counter 4 is used as an R-reset pulse, but this R-reset pulse can be synchronized with one reset pulse as shown in the second half of Figure 6-■ and ■. This is after the time when one reset pulse is generated, and the data between the first and second scrap reset pulses becomes invalid because the read address is not determined as shown in Figure 6-■. There is a problem that some transferred data may be lost.

Means for Solving Problem C] The above problem is solved by the clock switching circuit shown in FIG.

Reference numeral 8 denotes a phase comparison means that compares the phase of the output of the counting means 7 and the synchronization pulse generated from the write reset pulse, and sends a comparison output to the memory means and the counting means.

[Effect]

The present invention connects the output side of the phase comparison means 8 to the memory means 6 and the counting means 7, and reads out the pulse (generated using the synchronization pulse) and sends it to the memory means 6 as a reset pulse, and at the same time sends the initialization signal to the memory means 6. It is also sent to the counting means 7 as follows.

Therefore, since the read reset pulse can be generated from the first write reset pulse, it is possible to correctly read the write data from the beginning, and invalid data is eliminated.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a time chart of FIG. 2. Note that the numbers on the left side of FIG. 3 are the waveforms of the portions with the same numbers in FIG. 2, and FIG. 3--■ shows the write data. Also, the same reference numerals indicate the same objects throughout the figures.

The operation shown in FIG. 2 will be explained below with reference to FIG.

First, the synchronization pulse generator 3 generates a synchronization pulse synchronized with R-CK using a triset pulse synchronized with W-CK (see FIG. 2--).

Then, a phase comparator 81 compares the phase of this synchronization pulse and the output (carry) from the counter 71, and if they do not match, this comparator outputs the synchronization pulse to the elastic store memory 61 as an R-reset pulse and an initialization signal. and is added to the counter 71 (see Figure 2--■, ■).

Therefore, in the former, the read address becomes address O as shown in the first half of Figure 3-■, and the data is read from address 0 at R-tJ, and in the latter, the data is initialized as shown in the first half of Figure 3-■. Count up from O.

Then, since the next synchronization pulse and the carry match, the phase comparator 81 sends the carry as an R-reset pulse and an initialization signal to the counter and FiFo, so the address becomes O and the count value becomes O. return.

That is, since the R-reset pulse can be generated immediately from the first Wm reset pulse, the written data can be read from the beginning without error.

〔Effect of the invention〕

As described above in detail, the present invention has the advantage that written data can be read from the beginning without error.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a time chart of Fig. 2, Fig. 4 is a clock switching circuit connection diagram, and Fig. 5 is a conventional block diagram. An example block diagram, FIG. 6, shows the time chart of FIG. In the figure, 1 is a write reset pulse generator, 2.61 is an elastic store memory, 3 is a synchronization pulse generator, 4.71 is a counter, 5.81 is a phase comparator, 6 is a memory means, and 7 is a counting means. , 8 indicates phase comparison means. Film+~-to diagram

Claims (1)

[Claims] A memory means (6) in which data is written from a predetermined location using a write reset pulse and a write clock generated using a frame synchronization signal, and the written data is read out using a read clock. , counting means (7) for counting the read clock;
and a phase comparison means (8) for comparing the phase of the output of the counting means and a synchronization pulse generated using the write reset pulse. A clock switching circuit characterized in that the clock is sent to a memory means (6) and a counting means (7).