JP3100907B2 - Analog signal delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for an analog signal delay circuit, and more particularly, for a delay circuit section of a pseudo-multiplex radio wave propagation path having a large delay time and requiring a fine control of the delay time interval. The present invention relates to an analog signal delay circuit.

[0002]

2. Description of the Related Art As a conventional delay circuit of this kind, FIG.
There was a circuit as shown. FIG. 2 is a block diagram schematically showing a configuration of a conventional analog signal delay circuit. In the figure, 1 is an input terminal to which an analog signal is input, and 2 is an A / A that converts the input analog signal into a digital signal.
D converter 3, a dual port RAM 3 for temporarily storing the converted digital signal, 4 a D / A converter for reconverting the digital signal read from RAM 3 into an analog signal, 5 a D / A converter 4 An output terminal for outputting an analog signal, 6 is a clock signal input terminal for inputting a clock signal of frequency Fc, 7 is an address counter, 8 is a register, and 9 is a subtractor.

Next, the operation of the conventional circuit will be described.
The analog signal input from the input terminal 1 is equal to the period of the clock signal input from the clock signal input terminal 6 (1/1).
In Fc), the data is converted into digital data by the A / D converter 2 and written into the dual port RAM 3. Also,
The clock signal is also input to the address counter 7, and the address (write timing) is input from the address counter 7 to the dual port RAM 3. The subtracter 9 calculates the difference between the value (for example, m) set in the register 8 as the delay time and the output of the address counter 7 and inputs the address (read timing) to the dual port RAM 3 at which the data is read. The signal is read and input to the D / A converter 4, converted into the original analog signal by the D / A converter 4 by the clock signal, and output from the output terminal 5. Therefore, the delay time t of this analog signal delay circuit is t = m ×
(1 / Fc).

[0004]

The conventional analog signal delay circuit is constructed as described above, and the delay time is t = m ×
(1 / Fc), that is, the controllable delay time interval depends on the frequency Fc of the clock signal. When it is desired to control the delay time interval minutely (to increase the delay time resolution), it is necessary to increase the frequency Fc of the clock signal. Since it is determined by the access time of the RAM, finer control than these access times cannot be performed. Therefore, it is necessary to set the frequency of the clock signal high by using an A / D, D / A converter and a dual-port RAM capable of high-speed operation. Further, there is a problem that the circuit scale is large and expensive, for example, a large-capacity dual-port RAM is required to obtain a large delay time.

The present invention has been made to solve such a problem, and provides an analog signal delay circuit having a simple and inexpensive configuration, capable of obtaining a large delay time and capable of minutely controlling the time interval. It is intended to be.

[0006]

An analog signal delay circuit according to the present invention is a shift register in which a plurality of flip-flops are arranged in a signal switch so that an arbitrary shift stage can be selected by a set value (L) of the register. And an A / D converter,
When the access time having the longest access time among the memories and the D / A converter is Fc, a clock signal having a frequency of n × Fc and a frequency divider for dividing this clock signal by 1 / n are provided. The operation timing of the A / D converter and the timing of writing to the memory are performed by a clock signal having a frequency Fc divided by the frequency divider, and the frequency Fc is input to the shift register. By operating the shift register with a clock and operating the D / A converter at the clock timing of the output signal from the shift register, the delay time τ (τ = m × (1 /
Fc) + L / (n × Fc)), and by varying the value of L, the delay time τ is varied in units of 1 / (n × Fc). Further, it is provided in a delay circuit of the pseudo multiplex radio wave transmission path.

[0007] The analog signal delay circuit of the present invention has the above-described configuration, so that the A / D converter, the memory, the D / A
Fine control of the delay time interval can be performed irrespective of the access time of the converter, and there is no need to use an A / D converter, a memory, and a D / A converter that operate at high speed, and a large delay time can be obtained. Even when setting, there is no need to use a large-capacity memory.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram for explaining an embodiment of the present invention. In the figure, reference numeral 1 denotes an input terminal to which an analog signal is input, and 2 denotes an A / D converter for converting the input analog signal into digital data. , 3 is a dual port RAM for temporarily storing the converted digital data, 4 is a D / A converter for reconverting the digital signal read from the RAM 3 into an analog signal, and 5 is a D / A converter.
An output terminal for outputting an analog signal from the A converter 4;
Is a clock signal input terminal for inputting a clock (frequency: n × Fc), 7 is an address counter, 8 is a register, 9
Is a subtractor.

Reference numeral 10 denotes a frequency divider (frequency division ratio: n);
Are signal switches, 12a to 12n are flip-flops, 1
Reference numeral 3 denotes a register. The set value (L) of the register 13
The shift register of the shift stage determined by the above is configured.

Next, the operation will be described. A / D converter 2, dual port R
The longest access time of the AM3 and the D / A converter 4 is
In the case of 1 / Fc, a clock signal having a frequency of n × Fc is input. The input clock signal is divided by the frequency divider 10 into 1
/ N, and the frequency-divided clock of the frequency Fc is input to the address counter 7 and the A / D converter 2, and the delayed analog signal input from the input terminal 1 is converted into digital data at this clock timing. The output value of the address counter 7 is increased by one at the period and the rising edge of the converted and divided clock signal, and the address (write timing) is input to the dual port RAM 3.

A subtractor 9 calculates a difference between a value (for example, m) set in a register 8 serving as a delay time and an output of the address counter 7 and inputs an address (readout timing) to the dual port RAM 3. And the data is read out and input to the D / A converter 4.

On the other hand, a clock signal having a divided frequency Fc is input to a D terminal of the flip-flop 12a.
The frequency nx is applied to the clock terminal of the flip-flop 12a.
Since the clock timing of Fc is input, the frequency F
The clock of c is shifted at the timing of 1 / (n × Fc) to the shift stage set by the set value (L) of the register 13, and the D / A is output from the output terminal Y of the signal switch 11.
Output to converter 4. The D / A converter 4 uses this Y
The digital data read from the dual port RAM at the timing of the output clock from is converted to the original analog signal and output from the output terminal 5. Therefore, the delay time τ of the output analog signal is τ = m × (1 / Fc) + L / (n × Fc). Since L is an arbitrary value set in the register 13, A / D,
Regardless of the access time of the D / A converter and the dual port RAM, the delay time is minimized, 1 / (nx Fc)
Fine control can be performed in units. Since the frequency division ratio n and the number of flip-flop stages can be freely set, a large delay time can be set using a memory having a normal capacity, and it is needless to say that minute time intervals can be freely controlled.

[0013]

As described above, the analog signal delay circuit of the present invention does not require an A / D, D / A converter or a dual port RAM which operates at high speed, and uses a large capacity dual port RAM or the like. There is an effect that an inexpensive analog signal delay circuit can be obtained with a simple configuration in which the delay time interval can be minutely controlled with a large delay time without being required.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of the present invention.

FIG. 2 is a block diagram for explaining a conventional analog signal delay circuit of this type.

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 A / D converter 3 dual port RAM 4 D / A converter 5 output terminal 6 clock signal input terminal for inputting frequency n × Fc 7 address counter 8 register 9 subtractor 10 divider (division ratio) : N) 11 signal switchers 12 a to 12 n flip-flop 13 register

Claims (2)

(57) [Claims] An A / D converter for sequentially converting an input analog signal into digital data, a memory for sequentially writing the converted digital data, and a method for sequentially reading the written digital data from the memory to read the original analog signal An analog signal delay circuit comprising: a D / A converter for converting the data into an analog signal; and means for generating a delay time (m × (1 / Fc)) by shifting the timing of writing to the memory and the timing of reading from the memory. A shift register in which a plurality of flip-flops are arranged in a signal switch so that an arbitrary shift stage can be selected by a set value (L) of the register; If the access time with the longest access time is Fc, a clock signal of frequency n × Fc and this clock signal are divided by 1 / And a timing for operating the A / D converter and a timing for writing to the memory are performed by a clock signal having a frequency Fc divided by the frequency divider. Fc is input, the shift register is operated by the clock of the frequency n × Fc, and the D / A converter is operated by the clock timing of the output signal from the shift register, so that the delay time τ (τ = m × (1 / Fc) + L / (n × Fc)), and by changing the value of L, the delay time τ is reduced to 1 / (n
.Times.Fc). An analog signal delay circuit characterized by being variable in units. 2. The analog signal delay circuit according to claim 1, wherein the analog signal delay circuit is provided in a delay circuit of a pseudo multiplex radio wave transmission line.