JPS5857775B2 - Series multi-signal speed conversion receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving device that performs reception processing of serial input signals of information processing devices (for example, text/graphic information receivers, data communication terminals, various management/control control devices) via various transmission paths. Regarding.

Generally, in distributed information terminal devices and receivers that receive information from various transmission paths, information reception input is not limited to a single input point, but multiple reception input points are required. There are many people.

Moreover, the data formats at this reception input point are rarely the same, and it is necessary to receive and process information of various data formats and transmission speeds.

FIGS. 1 and 2 show examples of conventional circuit systems.

In FIG. 1, 11...11...1N are received data signals transmitted through different transmission paths, respectively, and 2
,...21...2N are received data signals 1,
. . 11 . . . 1N to determine its transmission rate, that is, the received data signal 1. . . . 11 . . . 1N clock signal indicating a beat rate; 3 indicates each of the received data signals 11 . . . 11 . . . 1N and the clock signal 21
...21...2N selection switching circuit; 4 is a counter circuit that counts the clock signals 21...21...2N;
5 is the serial received data signal 1. ... 11...1N
9 is an information processing device that reads and stores the received data.

Next, let's examine its movements.

Prior to receiving input data, the information processing device 9 generates received data signals 1111...1N and clock signals 21...2i...2 corresponding to each of the received data signals.
A switching signal 8 for selecting and switching between N and N in accordance with the reception data signal to be received now is output to the selection switching circuit 3.

In response to this switching signal 8, the selection switching circuit 3 selects the received data signals 11...11...1N and the clock signals 21...
1 specified by the information processing device 9 from 2i...2N
A pair of received data signal 1 and clock signal 2 are selected, and the former is supplied to the conversion circuit 5 and the latter to the counter circuit 4 and the conversion circuit 5.

The counter circuit 4 counts the clock signal 2, and every time it counts a certain number of times, the counter circuit 4 counts this number of times, for example, by P (P=
8), then clock signal 2 is set to P
The strobe signal 6 is output to the information processing device 9 every time the number of times is counted.

At the same time, each time the conversion circuit 5 receives the clock signal 2, it shifts and stores the received data signal 1 one by one, that is, one bit at a time, converts the serial received data signal 1 into parallel,
Output as parallel data 7.

Here, the shift operation of the conversion circuit 5, the counting operation of the counter circuit 4, and the output operation of the strobe signal 6 are performed while being synchronized with the clock signal 2.

Each time the information processing device 9 detects the strobe signal 6, the parallel data 7 is read and stored.

Here, parallel data 7 in units of P bits will be read.

The above operation is then repeated a predetermined number of times.

When this is completed, the switching signal 8 is output again and the series of operations described above are repeated.

Normally, the information processing device 9 rarely executes only the operations of reading and storing received data, and must also execute other functional processes in parallel.

In such a case, in such a circuit system, as is clear from the above explanation, from the perspective of the information processing device 9, the reading speed of the received data is determined by the clock frequency of the received data, and the reading speed of the received data is determined by the clock frequency of the received data, and Similar operations are required even for slow received data, and furthermore, the strobe signal 6 must be constantly monitored and parallel data reading and storage processing must be executed.

This is one of the major hindrances that prevent the efficient operation of the information processing device 9.

In other words, while paying close attention to the relationship between the time required for other functional processing and the time required to ensure the above operations, the information processing device 9 must be operated.

Next, the conventional circuit system shown in FIG. 2 will be explained.

Components in FIG. 2 labeled with the same symbols as in FIG. 1 are the same as in FIG. 1.

11 is a clock generation circuit, 13 is a clock selection switching circuit, and 16 is supplied to the input stage every time a clock signal is input, stores the signal in the first stage, and transfers the signals stored after the first stage one by one to the next stage. It is a serial input/serial output storage element such as a shift register that shifts and stores the signal and outputs the signal stored in the final stage to the outside as an output.

Next, its operation will be explained.

Prior to reception, the information processing device 9 receives the desired received data signal 1. . . 11 . . . 1N is output to the selection switching circuit 3.

At the same time, the clock switching signal 14 is output to the clock selection switching circuit 13, and the clock signal 2 is changed to the shift pulse 1.
Selected as 5.

The selected received data 1 is supplied to the storage element 16, and the clock signal 2 is also selected by the clock selection switching circuit 13 and supplied to the storage element 16 as a shift pulse 15.

Therefore, the storage element 16 shifts and stores the received data signal 1 every time it receives a shift pulse 15 consisting of the clock signal 2.

It goes without saying that this storage element 16 has a storage capacity sufficient to store a series of received data.

For a time sufficient to receive, shift and store a series of received data signals, the information processing device 9 switches each of the switching signals 8 and 14.
After maintaining this state, the clock switching signal 14 is then switched so that the internal clock signal 12, which is the output of the clock generation circuit 11, becomes the shift pulse 15.

Then, the received data previously stored in the storage element 16 is shifted by a shift pulse 15 consisting of the internal clock signal 12, and is outputted from the storage element 16 as serial data 17.

The information processing device 9 processes the serial data 17 while taking timing with the shift pulse 15 composed of the internal clock signal 12.
Read and process.

According to the conventional example shown in FIG. 2, the received data signal 1
is temporarily stored in the storage element 16 using the clock signal 2, and when the information processing device 9 reads and processes it, it is taken out from the storage element 16 using the internal clock signal 12.

Therefore, compared to FIG. 1, the information processing device 9 reads and processes the data once stored in the storage element 16 as serial data 17 at an arbitrary constant speed by controlling the clock switching signal 14 to the clock switching circuit 13. The received data signals 1 . . . 21 .
. . 11 .
The oscillation frequency of can be set to the optimum value for the information processing device 9.

For these reasons, FIG. 2 can compensate for the drawbacks of FIG. 1 mentioned above.

However, there are limits to the concrete implementation of the system shown in FIG. 2 above.

This mainly relates to the memory element 16, and generally speaking, the operating speed of the serial input/output memory element shown in FIG. 2 is lower than the processing speed of the components of the conversion circuit that converts serial data into parallel data in FIG. is slow.

Therefore, for high-speed received data signals, the circuit system of FIG. 2 has a disadvantage compared to the circuit system of FIG. 1.

It is an object of the present invention to provide a speed conversion receiving circuit which compensates for the drawbacks of the present invention and efficiently performs reception processing of various serial signals in receiving serial data with a simple circuit configuration.

An embodiment of the present invention will be described below based on the drawings.

In FIG. 3, 3 is an input signal selection switching circuit, 9 is an information processing device, 11 is a clock generation circuit that generates an internal clock signal, 13 is a clock selection switching circuit, and 20 is an operation mode of a shift register 23, which will be described later. 23 is a parallel output 2-bit shift register having both serial and parallel input modes; 25 is a frequency dividing circuit that divides the clock signal into l/2; 271 and 27;
□ are l-bit latch registers, and 291 and 292 are serial input/serial output storage elements such as shift registers.

Next, its operation will be explained.

This circuit stores the transmitted received data signal in the storage element 29.
．． and 29□ (hereinafter referred to as reception mode), and the information processing device 9 stores in the storage element 29. and 2
The operation mode is divided into two modes: an operation mode for reading and processing received data signals stored in the 92 (hereinafter referred to as read mode).

4 and 5 show operation timing charts when the circuit of FIG. 3 is set to receive mode and read mode, respectively.

First, the operation in the reception mode will be explained with reference to FIGS. 3 and 4.

Prior to receiving input data, the information processing device 9 receives received data signals 1. . . 11 . . . 1N and clock signals 21 . . . 21 . The signal 14 is outputted to the clock switching circuit 13, and the mode switching signal 21 is outputted to the mode switching circuit 20.

Upon receiving these signals, the selection switching circuit 3 sends the selected received data signal 1 and clock signal 2 to the shift register 23 and the clock selection switching circuit 13, respectively, and the clock selection switching circuit 13 selects the clock signal 2. As the shift pulse 15, the shift register 23 and the frequency dividing circuit 25,
Furthermore, the mode switching circuit 20 outputs to the shift register 23 a mode signal 22 that causes the shift register 23 to operate as a serial input/parallel output shift register.

After being set to receive mode as described above, A, B, and C as shown in FIG.

FIG. 4 shows each signal waveform and timing chart when the received data signal 1 of D... arrives.

The received data signal 1 selected by the selection switching circuit 3 is supplied to a 2-bit shift register 23 set to serial input/parallel output operation.

This serial received data signal 1 is shifted by a shift pulse 15 consisting of a clock signal 2 and converted into a parallel signal,
Output signal 24 of shift pulser 23. is output as 242.

These output signals 241 and 242 shift the shift pulse 15 to
Branch clock signal 26 as a latch pulse divided by 2
At the rising edge of , the bit is stored in latch registers 211 and 272.

Then, the output signals 28 of the latch registers 271 and 27□. and 282 are stored in storage elements 291 and 29□ at the falling edge of branch clock signal 26.

At this time, the previous memory element 29. The signals stored in and 292 are shifted and stored.

The above operations are repeated to complete the series of reception mode operations.

Note that the memory element 29. , 292 have sufficient storage capacity to store a series of received data.

Next, the operation in the read mode will be explained.

When the information processing device 9 completes the series of operations in the reception mode, the information processing device 9 transfers the clock switching signal 14 to the clock selection switching circuit 1.
3, the mode switching signal 21 is also output to the mode switching circuit 20.

Upon receiving these signals, the clock selection switching circuit 13 outputs the internal clock signal 12, which is the output of the clock generation circuit 11, as a shift pulse 15 to the shift register 23 and the frequency dividing circuit 25. A mode signal 22 is output to a shift register 23 to alternately switch between parallel input operation and shift operation.

When the reading mode is set in this way, the signals of P, R, TV, etc. and Q, S, U, W,... FIG. 5 shows the signal waveform and timing chart when it is assumed that .

The signals stored in storage elements 291 and 292 are shifted at the falling edge of branch clock signal 26 and supplied to parallel input points of shift register 23 as serial signal outputs 301 and 30□, respectively.

The shift register 23 alternately repeats parallel input operation and shift operation using the mode signal 22 synchronized with the frequency-divided clock signal 26, and outputs a serial signal 30. during the parallel input operation. and 302
During the shift operation, the signal 30
, are shifted to the bits on the extraction side and output as output signals 24□ and 24□ as shown in FIG.

Output signals 241 and 24□ are from launch register 271 to 27
The shift pulse 15 is supplied to the shift register 23.
Latch registers 271 and 272 on the rising edge of divided clock signal 26 as a latch pulse before being applied to latch registers 271 and 272.
are stored respectively.

Furthermore, the output signal 281 of the latch register 271 and 27□
and 28□ are stored again in storage elements 291 and 292, respectively, at the falling edge of frequency-divided clock signal 26.

On the other hand, the signals stored separately in the storage elements 291 and 29□ are converted into serial signals again in the shift register 23 as described above, so the information processing device 9 converts the output signal 241 converted into a serial signal into an internal clock signal. 12, the data is read and processed in a timely manner.

As is clear from the above description, the memory element 29. Since the signals stored in and 292 are reproduced and stored, the information processing device 9
can be set to repeat read mode and read the received signal any number of times.

In this embodiment, the shift register 23 and a 2-bit shift register are used, but it is also possible to use a larger number of bits. The same can be applied to a circuit in which the number of stages of the latch register composed of two stages and the number of stages of the serial output storage element composed of two stages of 29° and 292 are increased by corresponding to the number of bits of the shift register 23. .

As described above, the present invention has the following advantages.

(a) The conventional example shown in FIG. 1 has an advantage over the conventional example shown in FIG. 2, that is, it is advantageous in terms of high speed.

(b) In reception mode, the shift register converts the serial signal into a parallel signal to reduce the reception speed, and buffering in the latch register compensates for the storage element's manual signal retention time, allowing the serial signal to operate at a slower speed. This realizes the use of an input-serial-output storage element.

(C) In the read mode, the shift register used in the receive mode is shared, and by providing a plurality of storage elements with serial inputs and serial outputs, the output signals of each are sent to the shift register as parallel signals. Therefore, the information processing device can read data as a serial signal faster than the operating speed of the storage element.

Furthermore, since the output is circulated and stored again, it can be read out any number of times.

[Brief explanation of the drawing]

1 and 2 are circuit configuration diagrams of a conventional example, FIG. 3 is a circuit configuration diagram showing an embodiment of the present invention, and FIGS. 4 and 5 are timing charts of reception mode and readout mode, respectively. be. 1.1. ...11...1N...Received data signal, 2゜21...21...2N...Clock signal, 3...Selection switching circuit, 8・・・・・・
・Switching signal, 9... Information processing device, 11...
... Clock generation circuit, 12 ... Internal clock signal, 13 ... Clock selection switching circuit, 14
......Clock switching signal, 15...Shift pulse, 20...Mode switching circuit, 21...
...Mode switching signal, 22...Mode signal, 23...Shift register, 24t, 24□・
...Output signal, 25... Frequency divider circuit, 26
・・・・・・Divided clock signal, 271, 272...
...Latch register, 291, 29□...Storage element, 30, . 30□・・・Parallel signal output.

Claims (1)

[Scope of Claims] 1. A device for receiving a plurality of serial signals, such as a character/graphic information receiver or a data communication terminal, which comprises a selection switching circuit for switching a plurality of serial input signals, an internal clock generation circuit, and the like. , a clock selection circuit that selectively switches between an input clock signal corresponding to the serial input signal output from the selection switching circuit and an internal clock signal generated by the internal clock generation circuit, and a serial input parallel output, a parallel input, and a parallel output.
a shift register having two operating modes and having a plurality of bits shifted by a shift pulse output from the clock selection switching circuit; a mode switching circuit switching the operating mode of the shift register; a frequency divider circuit that divides the frequency; a plurality of latch registers that latch each of the plurality of parallel outputs of the shift register with a pulse of the output of the frequency divider circuit; and a series input serial output that stores each output of the latch register. a plurality of functional memory elements, supplying the output signal of the selection switching circuit to the serial input point of the shift register, and supplying each output signal of the memory element to the parallel input point of the shift register; In addition, in the serial input signal receiving mode, the clock selection circuit selects an input clock signal, and operates the shift register in a serial input parallel output operation mode to output each parallel output of the shift register to the serial input signal receiving mode. Latching the pulse of the frequency dividing circuit output into the latch register as a latch pulse, storing each output of the latch register in a plurality of storage elements,
In the read mode of the signal stored in the storage element, the clock selection circuit selects an internal clock signal as a shift pulse of the shift register, and the internal clock signal and this internal clock signal are used as the latch pulse of the output of the frequency dividing circuit. The shift register is operated by switching between an operation of latching the parallel signal output supplied from the storage element and an operation of shifting the latched signal by an output mode signal of the mode switching circuit controlled in synchronization with the output mode signal. A serial multi-signal speed conversion receiving device, characterized in that the signal stored in a plurality of storage elements is read out as a serial signal using one of the parallel output signals of the shift register. 2. After latching the parallel signal output supplied from the storage element in the shift register and before the first shift pulse is supplied to the shift register, store the parallel output signal of the shift register in the latch register with a latch pulse, and 2. The serial multi-signal speed conversion receiving device according to claim 1, further comprising the step of storing the data again in a storage element.