JPH07183163A - Trimming capacitor - Google Patents

Trimming capacitor

Info

Publication number
JPH07183163A
JPH07183163A JP34642893A JP34642893A JPH07183163A JP H07183163 A JPH07183163 A JP H07183163A JP 34642893 A JP34642893 A JP 34642893A JP 34642893 A JP34642893 A JP 34642893A JP H07183163 A JPH07183163 A JP H07183163A
Authority
JP
Japan
Prior art keywords
electrode
trimming
dielectric
electrodes
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP34642893A
Other languages
Japanese (ja)
Inventor
Kaneo Sasaki
金雄 佐々木
Hiroshi Yagi
博志 八木
Atsushi Ikeda
淳 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP34642893A priority Critical patent/JPH07183163A/en
Publication of JPH07183163A publication Critical patent/JPH07183163A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To provide a trimming capacitor in which trimming electrodes and an internal electrode are formed on one surface side and has such a structure that can prevent the occurrence of warps at the time of sintering. CONSTITUTION:A trimming capacitor is provided with trimming electrodes 3 formed on the surface of a dielectric 1 and an internal electrode 2 formed in the shape of a layer in the dielectric 1 near the surface of the dielectric 1. The capacitor is also provided built-in dummy electrodes 5 for preventing the occurrence of warps at the time of sintering. The electrodes 5 are provided at a depth from 0.05mm to 40% of the thickness of a chip from the surface of the dielectric 1 opposite to the surface of the dielectric 1 on which the electrode 3 is formed. Since the capacitor is provided with the built-in dummy electrodes 5, the electrodes 5 do not touch a conductor pattern on a substrate when the capacitor is mounted on the substrate. When multiple dummy electrodes 5 are provided in the direction of lamination and layers of the dielectric 1 are put between each dummy electrode 5, the occurrence of voids can be prevented in the capacitor.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、セラミックでなる誘電
体と導電体との積層構造により、チップ状の焼結体とし
て構成され、発振回路等において、電極のトリミングに
より高い精度で容量を可変設定する必要のある場合に用
いられるトリミングコンデンサに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is constructed as a chip-shaped sintered body by a laminated structure of a ceramic dielectric and a conductor, and in an oscillation circuit or the like, the capacitance can be varied with high accuracy by trimming electrodes. The present invention relates to a trimming capacitor used when it needs to be set.

【0002】[0002]

【従来の技術】図3(A)は従来のトリミングコンデン
サの例を示す縦断面図であり、スクリーン印刷法あるい
はシート法またはこれらを併用した方法により、チタン
酸バリウムや酸化チタン等の誘電体1を積層し形成する
と共に、一方の表面の近傍に白金、パラジウム、銀また
はこれらの合金からなる内部電極2、2を形成し、表面
に同じ導電材料でなるトリミング電極3を島状に、すな
わち他の導電体と接続せずに形成し、切断、焼結後、側
面に内部電極2、2にそれぞれ接続する外部電極(端子
電極)4、4を焼き付けやメッキ等により形成してな
る。このトリミングコンデンサは、両内部電極2、2と
トリミング電極3との間の各容量成分が直列接続された
等価回路で表現できるもので、予め必要とされる容量よ
り過大な容量が得られるように製造しておき、例えば発
振回路を構成した後、トリミング電極3をレーザビーム
等によってトリミングすることにより、所望の回路特性
を得るものである。
2. Description of the Related Art FIG. 3A is a vertical cross-sectional view showing an example of a conventional trimming capacitor, and a dielectric material 1 such as barium titanate or titanium oxide is formed by a screen printing method, a sheet method, or a combination of these methods. Are laminated and formed, internal electrodes 2, 2 made of platinum, palladium, silver or an alloy thereof are formed in the vicinity of one surface, and trimming electrodes 3 made of the same conductive material are formed in an island shape on the surface, that is, the other. Is formed without being connected to the electric conductor, and after cutting and sintering, external electrodes (terminal electrodes) 4 and 4 respectively connected to the internal electrodes 2 and 2 are formed on the side surfaces by baking or plating. This trimming capacitor can be represented by an equivalent circuit in which the respective capacitance components between both internal electrodes 2 and 2 and trimming electrode 3 are connected in series, so that a capacitance larger than that required in advance can be obtained. After manufacturing, for example, forming an oscillation circuit, the trimming electrode 3 is trimmed with a laser beam or the like to obtain desired circuit characteristics.

【0003】図3(B)の例は、表面近傍の内部電極2
を島状に形成し、表面のトリミング電極3、3をそれぞ
れ外部電極4、4に接続したものであり、トリミング電
極3、3の一方または双方をトリミングして容量を調整
するものである。
The example of FIG. 3B shows an internal electrode 2 near the surface.
Is formed in an island shape and the trimming electrodes 3 and 3 on the surface are connected to the external electrodes 4 and 4, respectively, and one or both of the trimming electrodes 3 and 3 is trimmed to adjust the capacitance.

【0004】[0004]

【発明が解決しようとする課題】このようなトリミング
コンデンサにおいては、所望の機械的剛性や取扱性を確
保するためにある程度以上の厚みが必要であって、厚み
は例えば0.6mm、0.8mm、1.1mm等の厚みに設定
される。一方、小型化すると電極面積が得がたいため、
所望の容量を得るためには内部電極2とトリミング電極
3との間の誘電体層の厚みは薄くしなければならなくな
り、その結果、図3(A)、(B)に示したように、内
部電極2とトリミング電極3、すなわち導体層が片面に
集中することになる。このように、片面側に電極2、3
が集中すると、図4(A)または(B)に示すように、
焼結による誘電体1と電極2、3の焼結の差や収縮率の
差により、トリミングコンデンサに反りrが発生する。
例えば外部電極4を除いたチップの厚みが0.6mm、縦
横の幅が3.2mm×2.5mmのものにおいて、電極2、
3の材質にパラジウムを用い、誘電体1の材質に酸化チ
タン系材料を用いた場合において、1350℃で焼結し
た場合、トリミング電極3の厚みと反りr(図4参照)
との関係は図5に示すように結果が得られている。図5
から明らかなように、誘電体1の厚み、すなわちコンデ
ンサの厚みを厚くすればするほど反りが大きくなる。従
って、このような反りを低減するには、トリミング電極
3等を薄くすれば良いわけであるが、しかしトリミング
電極3や内部電極2をあまり薄くすると、高周波におけ
るQが低下するため、ある程度のトリミング電極3の厚
みは確保しなければならない。従って実際上、従来構造
においては反りは避けられず、仮にトリミング電極3の
厚みを16μm程度の厚みとすると、数十μm前後の反
りが発生する。このような反りが発生すると、製造、検
査ラインにおける搬送、ハンドリングが良好に行えなか
ったり、基板への半田付けが良好に行えなかったりする
という不具合が生じる。
In such a trimming capacitor, a certain thickness or more is required to secure desired mechanical rigidity and handleability, and the thickness is, for example, 0.6 mm or 0.8 mm. , 1.1 mm or the like. On the other hand, it is difficult to obtain the electrode area when downsized,
In order to obtain the desired capacitance, the thickness of the dielectric layer between the internal electrode 2 and the trimming electrode 3 must be reduced, and as a result, as shown in FIGS. 3 (A) and 3 (B), The internal electrode 2 and the trimming electrode 3, that is, the conductor layer is concentrated on one surface. In this way, the electrodes 2, 3 are
Is concentrated, as shown in FIG. 4 (A) or (B),
A warp r occurs in the trimming capacitor due to a difference in sintering or a contraction rate between the dielectric 1 and the electrodes 2 and 3 due to sintering.
For example, in the case where the thickness of the chip excluding the external electrodes 4 is 0.6 mm and the width and width are 3.2 mm × 2.5 mm, the electrodes 2,
When palladium is used as the material of 3 and a titanium oxide-based material is used as the material of the dielectric 1, the thickness of the trimming electrode 3 and the warpage r (see FIG. 4) when sintered at 1350 ° C.
As for the relationship with, the result is obtained as shown in FIG. Figure 5
As is clear from the above, the greater the thickness of the dielectric 1, that is, the thickness of the capacitor, the greater the warp. Therefore, in order to reduce such a warp, it is sufficient to thin the trimming electrode 3 and the like. However, if the trimming electrode 3 and the internal electrode 2 are made too thin, the Q at a high frequency is lowered, so that the trimming is performed to some extent. The thickness of the electrode 3 must be ensured. Therefore, in reality, a warp is inevitable in the conventional structure, and if the thickness of the trimming electrode 3 is about 16 μm, a warp of about several tens μm occurs. When such warpage occurs, there arises a problem that manufacturing, transportation and handling in an inspection line cannot be performed favorably, or soldering to a substrate cannot be favorably performed.

【0005】本発明は、上記した問題点に鑑み、片面側
にトリミング電極、内部電極が集中するトリミングコン
デンサにおいて、焼結による反りの発生を防止しうる構
造のトリミングコンデンサを提供することを目的とす
る。
In view of the above-mentioned problems, it is an object of the present invention to provide a trimming capacitor having a structure in which a trimming electrode and an internal electrode are concentrated on one surface side and which can prevent warpage due to sintering from occurring. To do.

【0006】[0006]

【課題を解決するための手段】本発明は、上記目的を達
成するため、誘電体の表面に形成したトリミング電極
と、該トリミング電極に誘電体を介して対向するよう
に、誘電体の前記表面近傍の内部に層状に形成した内部
電極とを備えた焼結体でなるトリミングコンデンサにお
いて、前記誘電体のトリミング電極形成面の反対側の面
より0.05mmの深さないし誘電体の厚み寸法の40%
の深さまでの間に電気特性への影響の小さいダミー電極
層を設けたことを特徴とする。本発明においては、前記
ダミー電極を積層方向に複数層設け、各層間に誘電体層
を設けることがより好ましい。
In order to achieve the above object, the present invention provides a trimming electrode formed on the surface of a dielectric and the surface of the dielectric so as to face the trimming electrode through the dielectric. In a trimming capacitor made of a sintered body having a layered internal electrode formed in the vicinity thereof, a dielectric layer having a depth of 0.05 mm from the surface of the dielectric material opposite to the trimming electrode formation surface is formed. 40%
It is characterized in that a dummy electrode layer having a small influence on the electrical characteristics is provided up to the depth of. In the present invention, it is more preferable that the dummy electrodes are provided in a plurality of layers in the stacking direction and a dielectric layer is provided between the layers.

【0007】[0007]

【作用】本発明によれば、内部に設けたダミー電極が前
記トリミング電極の反対側に属する領域に形成されるの
で、トリミング電極とこれに対向する内部電極が誘電体
に対して相対的に縮める(伸ばす)方向に作用する場合
には、ダミー電極も誘電体に対してトリミング電極の反
対側の部分を縮める(伸ばす)方向に作用するため、主
体である誘電体の反りが抑制される。このような反りの
抑制作用を発揮するには、ダミー電極にはある程度の厚
みが必要になるが、ダミー電極を多層に設けてトータル
の厚みを確保するようにすれば、各ダミー電極の厚みを
薄くでき、内蔵電極を厚くした場合に生じ易い内部空隙
発生が回避される。
According to the present invention, since the dummy electrode provided inside is formed in the region opposite to the trimming electrode, the trimming electrode and the internal electrode facing the trimming electrode shrink relatively to the dielectric. When acting in the (stretching) direction, the dummy electrode also acts in a direction of contracting (stretching) the portion of the dielectric material on the side opposite to the trimming electrode, so that the warpage of the main dielectric material is suppressed. In order to exert such an effect of suppressing the warp, the dummy electrode requires a certain thickness, but if the dummy electrodes are provided in multiple layers to ensure the total thickness, the thickness of each dummy electrode can be reduced. It can be made thin, and the generation of internal voids that tends to occur when the built-in electrode is made thick is avoided.

【0008】[0008]

【実施例】図1(A)は本発明によるトリミングコンデ
ンサの一実施例を示す縦断面図であり、図3(B)のタ
イプ、すなわちトリミング電極3を外部電極4に接続さ
せて直方体状に形成されたものに本発明を適用した実施
例である。5は本発明により付加したダミー電極であ
り、その材質としては、前記内部電極2やトリミング電
極3と同様に、白金、パラジウム、銀あるいはこれらの
合金が使用される。誘電体1も前記同様にチタン酸バリ
ウムや酸化チタン等が用いられるが、本発明において、
これらの誘電体1や電極2、3、5の材質はこれらに限
定されないことはいうまでもない。
1A is a vertical sectional view showing an embodiment of a trimming capacitor according to the present invention, which is of the type shown in FIG. 3B, that is, the trimming electrode 3 is connected to an external electrode 4 to form a rectangular parallelepiped shape. It is an example in which the present invention is applied to the formed one. Reference numeral 5 denotes a dummy electrode added according to the present invention, and as the material thereof, platinum, palladium, silver or an alloy thereof is used, like the internal electrode 2 and the trimming electrode 3. The dielectric 1 is also made of barium titanate, titanium oxide or the like as described above, but in the present invention,
Needless to say, the materials of the dielectric 1 and the electrodes 2, 3, 5 are not limited to these.

【0009】このように、ダミー電極5を設ければ、こ
のダミー電極5は、焼結に伴う収縮の際に、トリミング
電極3と同様に誘電体1に作用し、誘電体1の反りを防
ぐことができる。すなわち、電極2、3、5が焼結時に
おける誘電体1より収縮率の大きい(小さい)ものであ
れば、ダミー電極5はトリミング電極3や内部電極2と
同様に、トリミング電極3や内部電極2のおおよそ反対
側の領域において、ダミー電極5の周辺部において誘電
体1をより収縮させる(収縮を妨げる)作用をなし、そ
の結果、誘電体1の反りが防止される。具体例について
述べると、誘電体1と電極2、3、5として従来例にお
いて説明したものと同様の材質のものを用い、外部電極
4を除いたチップの厚みt=0.6mm 、そのチップの
縦横の寸法を3.2mm×2.5mm、トリミング電極3の
厚み=9.0μm、内部電極2の厚み=2.0μmと
し、かつ、ダミー電極5の厚み=2.0μmにしたもの
においては、反りを10.0μm以下に抑えることが可
能であった。また、本実施例によれば、ダミー電極5が
トリミング電極3に並列接続されることになるので、抵
抗が減少し、Qを向上させることができる。
As described above, when the dummy electrode 5 is provided, the dummy electrode 5 acts on the dielectric 1 in the same manner as the trimming electrode 3 when contracting due to sintering, and prevents the dielectric 1 from warping. be able to. That is, if the electrodes 2, 3 and 5 have a contraction rate larger (smaller) than the dielectric body 1 at the time of sintering, the dummy electrode 5 is the same as the trimming electrode 3 or the internal electrode 2 in the same manner as the trimming electrode 3 or the internal electrode 2. In a region approximately opposite to 2, it has an effect of further contracting (preventing contraction) of the dielectric 1 in the peripheral portion of the dummy electrode 5, and as a result, warpage of the dielectric 1 is prevented. A specific example will be described. As the dielectric 1 and the electrodes 2, 3 and 5, the same material as that described in the conventional example is used, and the thickness t of the chip excluding the external electrode 4 is 0.6 mm. In the case where the vertical and horizontal dimensions are 3.2 mm × 2.5 mm, the thickness of the trimming electrode 3 is 9.0 μm, the thickness of the internal electrode 2 is 2.0 μm, and the thickness of the dummy electrode 5 is 2.0 μm, The warp could be suppressed to 10.0 μm or less. Further, according to this embodiment, since the dummy electrode 5 is connected in parallel to the trimming electrode 3, the resistance can be reduced and the Q can be improved.

【0010】本発明においては、前記チップ厚みtが
0.5mm〜1.3mm、前記チップの縦横の寸法を3.2
mm×2.5mm〜4.5mm×3.2mm、内部電極2とトリ
ミング電極3との間の間隔bが4.0μm〜10.0μ
m程度(該間隔と厚みtとの比b/t=0.3%〜2.
0%)、トリミング電極3の厚みが5.0μm〜9.0
μm、内部電極2の厚みが1.0μm〜3.0μmに設
定されるコンデンサにおいて、前記ダミー電極5は、ト
リミング電極3を形成した面の反対側の面から深さsを
0.05mm以上、誘電体1の厚みtの0.4倍以下の範
囲(より好ましくは0.07mm以上、厚みtの0.35
倍以下の範囲)内に形成する。また、ダミー電極5の厚
みは1.0μm〜3.0μmの範囲(より好ましくは
1.5μm〜2.5μm)に設定する。
In the present invention, the chip thickness t is 0.5 mm to 1.3 mm, and the vertical and horizontal dimensions of the chip are 3.2.
mm × 2.5 mm to 4.5 mm × 3.2 mm, the distance b between the internal electrode 2 and the trimming electrode 3 is 4.0 μm to 10.0 μ
m (ratio of the interval and the thickness t, b / t = 0.3% to 2.
0%), and the thickness of the trimming electrode 3 is 5.0 μm to 9.0.
μm, and the thickness of the internal electrode 2 is set to 1.0 μm to 3.0 μm, the dummy electrode 5 has a depth s of 0.05 mm or more from the surface opposite to the surface on which the trimming electrode 3 is formed, 0.4 times or less of the thickness t of the dielectric 1 (more preferably 0.07 mm or more, 0.35 of the thickness t
It is formed within the range of less than twice. The thickness of the dummy electrode 5 is set in the range of 1.0 μm to 3.0 μm (more preferably 1.5 μm to 2.5 μm).

【0011】ダミー電極5を誘電体1の内部に設けた理
由は、基板(図示せず)の導体パターン上にこのトリミ
ングコンデンサを搭載した場合、外部電極4以外の導体
部分が前記導体パターンに接触する可能性を無くすため
である。また、ダミー電極5の深さを50μm以上とし
た理由は、電極の表面をセラミック(誘電体)で絶縁す
ることにより、その表面に欠け、クラックが発生しても
ダミー電極5と他の回路パターンとの短絡を防止するた
めであり、また、ダミー電極5の深さを誘電体1の厚み
tの0.4倍までの深さとした理由は、より以上の深さ
になると電気特性への影響が大きくなり、また、前記反
り防止効果がそれほど期待できなくなるからである。
The reason why the dummy electrode 5 is provided inside the dielectric 1 is that when this trimming capacitor is mounted on the conductor pattern of the substrate (not shown), the conductor portion other than the external electrode 4 contacts the conductor pattern. This is to eliminate the possibility of The reason why the depth of the dummy electrode 5 is set to 50 μm or more is that the surface of the electrode is insulated with a ceramic (dielectric) so that even if a crack or crack is generated on the surface, the dummy electrode 5 and other circuit patterns are not formed. This is for the purpose of preventing a short circuit with the dummy electrode 5 and the reason why the depth of the dummy electrode 5 is set to 0.4 times the thickness t of the dielectric 1 is that the influence on the electrical characteristics becomes greater. Is large, and the warp prevention effect cannot be expected so much.

【0012】なお、ダミー電極5がコンデンサの電気特
性になるべく影響を与えないようにするためには、ダミ
ー電極5と内部電極2との間の間隔aと、内部電極2と
トリミング電極3との間隔bとの比a/bは50〜80
とする。本実施例においては、ダミー電極5のパターン
をトリミング電極3のパターンと同じにしているので、
トリミング電極3と同じ印刷パターンが使用できるとい
う利益が得られる。
In order to prevent the dummy electrode 5 from affecting the electrical characteristics of the capacitor as much as possible, the distance a between the dummy electrode 5 and the internal electrode 2 and the internal electrode 2 and the trimming electrode 3 are set. Ratio a / b with interval b is 50-80
And In this embodiment, since the pattern of the dummy electrode 5 is the same as the pattern of the trimming electrode 3,
The advantage is that the same printed pattern as the trimming electrode 3 can be used.

【0013】図1(B)は本発明の他の実施例であり、
本実施例は、ダミー電極5を2層に形成したものであ
り、このようにダミー電極5を2層以上に形成して各ダ
ミー電極5の間を誘電体層とすれば、各ダミー電極5の
層の厚みを薄くすることができ、ダミー電極5を内部電
極として誘電体以外の収縮率の異なる材質を用いた場合
において、異なる層を厚くした場合に起こる不具合、す
なわちダミー電極5と誘電体1との接合部における空隙
部の発生を無くすことができる。
FIG. 1B shows another embodiment of the present invention.
In this embodiment, the dummy electrodes 5 are formed in two layers. If the dummy electrodes 5 are formed in two layers or more and the dummy electrodes 5 are formed as a dielectric layer, the dummy electrodes 5 are formed. The thickness of the layer can be reduced, and when the dummy electrode 5 is made of a material having a different contraction rate other than the dielectric as the internal electrode, a problem occurs when the different layers are thickened, that is, the dummy electrode 5 and the dielectric. It is possible to eliminate the generation of voids at the joint with 1.

【0014】図2(A)は本発明の他の実施例であり、
ダミー電極5を外部電極4に接続しない島状電極として
形成したものであり、本実施例は、外部電極4に接続さ
れるトリミング電極3とダミー電極5とが直接対向しな
いため、ダミー電極5を設けたことによる電気特性への
影響が小さくなるという利点がある。
FIG. 2A shows another embodiment of the present invention,
The dummy electrode 5 is formed as an island-shaped electrode that is not connected to the external electrode 4. In this embodiment, the trimming electrode 3 connected to the external electrode 4 and the dummy electrode 5 do not directly face each other. There is an advantage that the influence on the electric characteristics due to the provision is reduced.

【0015】上記実施例においては、トリミング電極3
を外部電極4に接続した例について説明したが、図2
(B)に示すように、トリミング電極3を島状に形成し
たものにも適用できる。本実施例による場合、ダミー電
極5を外部電極4に接続し、かつダミー電極5はトリミ
ング電極3に直接対向しないから、ダミー電極5を設け
たことによるコンデンサの電気特性への影響はより小さ
くなる。
In the above embodiment, the trimming electrode 3
The example in which the external electrode 4 is connected to the
As shown in (B), the trimming electrode 3 may be formed in an island shape. In the case of the present embodiment, since the dummy electrode 5 is connected to the external electrode 4 and the dummy electrode 5 does not directly face the trimming electrode 3, the influence of the provision of the dummy electrode 5 on the electric characteristics of the capacitor becomes smaller. .

【0016】本発明は、コンデンサを誘電体1の面方向
(紙面に垂直方向)に複数個形成する場合にも適用する
ことができる。
The present invention can also be applied to the case where a plurality of capacitors are formed in the plane direction of the dielectric 1 (perpendicular to the plane of the drawing).

【0017】[0017]

【発明の効果】請求項1によれば、トリミング電極の反
対側表面よりある深さの範囲内にダミー電極を設けたの
で、トリミング電極やこれに近接対向する内部電極によ
る焼結時の誘電体との収縮率の差による反りを防止する
ことができる。このため、製造、検査ラインにおける搬
送、ハンドリングが円滑に行えると共に、基板への半田
等による取付けも良好に行えるトリミングコンデンサが
提供でき、歩留りが向上する。また、ダミー電極が内部
に形成されているので、コンデンサを搭載する基板がダ
ミー電極に接触するおそれがない。
According to the first aspect of the present invention, since the dummy electrode is provided within a certain depth range from the surface on the opposite side of the trimming electrode, the dielectric material at the time of sintering by the trimming electrode and the internal electrode closely facing the trimming electrode. It is possible to prevent the warpage due to the difference in shrinkage rate between and. Therefore, it is possible to provide a trimming capacitor that can be smoothly transported and handled in the manufacturing and inspection lines, and can be attached to a substrate by soldering, and the yield is improved. Further, since the dummy electrode is formed inside, there is no possibility that the substrate on which the capacitor is mounted will come into contact with the dummy electrode.

【0018】請求項2によれば、内部に複数層のダミー
電極を設けたため、各ダミー電極を薄く形成でき、ダミ
ー電極と誘電体との間の空隙の発生を防止することがで
きる。
According to the second aspect, since the plurality of layers of dummy electrodes are provided inside, each dummy electrode can be thinly formed, and it is possible to prevent the generation of the void between the dummy electrode and the dielectric.

【図面の簡単な説明】[Brief description of drawings]

【図1】(A)、(B)はそれぞれ本発明によるトリミ
ングコンデンサの実施例を示す縦断面図である。
1A and 1B are vertical cross-sectional views showing an embodiment of a trimming capacitor according to the present invention.

【図2】(A)、(B)はそれぞれ本発明によるトリミ
ングコンデンサの他の実施例を示す縦断面図である。
2A and 2B are vertical sectional views showing another embodiment of a trimming capacitor according to the present invention.

【図3】(A)、(B)はそれぞれ従来のトリミングコ
ンデンサを示す縦断面図である。
3A and 3B are vertical cross-sectional views showing a conventional trimming capacitor.

【図4】(A)、(B)はそれぞれ従来のトリミングコ
ンデンサにおける焼結による反りを示す縦断面図であ
る。
4 (A) and 4 (B) are vertical cross-sectional views showing warpage due to sintering in a conventional trimming capacitor.

【図5】従来のトリミングコンデンサにおけるトリミン
グ電極と反りとの相関関係を示す図である。
FIG. 5 is a diagram showing a correlation between a trimming electrode and a warp in a conventional trimming capacitor.

【符号の説明】[Explanation of symbols]

1 誘電体 2 内部電極 3 トリミング電極 4 外部電極 5 ダミー電極 1 Dielectric 2 Internal electrode 3 Trimming electrode 4 External electrode 5 Dummy electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】誘電体の表面に形成したトリミング電極
と、該トリミング電極に誘電体を介して対向するよう
に、誘電体の前記表面近傍の内部に層状に形成した内部
電極とを備えた積層構造の焼結体でなるトリミングコン
デンサにおいて、前記誘電体のトリミング電極形成面の
反対側の面より0.05mmの深さ、ないしチップの厚み
寸法の40%の深さまでの間に電気特性への影響の小さ
いダミー電極層を設けたことを特徴とするトリミングコ
ンデンサ。
1. A laminate comprising a trimming electrode formed on a surface of a dielectric, and an internal electrode formed in a layer inside the dielectric near the surface so as to face the trimming electrode via the dielectric. In a trimming capacitor made of a sintered body having a structure, the electrical characteristics of the trimming capacitor are increased to a depth of 0.05 mm from the surface opposite to the trimming electrode formation surface of the dielectric or to a depth of 40% of the chip thickness dimension. A trimming capacitor having a dummy electrode layer having a small influence.
【請求項2】請求項1において、前記ダミー電極を積層
方向に複数層設け、各ダミー電極間に誘電体層を設けた
ことを特徴とするトリミングコンデンサ。
2. A trimming capacitor according to claim 1, wherein a plurality of said dummy electrodes are provided in a stacking direction and a dielectric layer is provided between each dummy electrode.
JP34642893A 1993-12-22 1993-12-22 Trimming capacitor Withdrawn JPH07183163A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34642893A JPH07183163A (en) 1993-12-22 1993-12-22 Trimming capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34642893A JPH07183163A (en) 1993-12-22 1993-12-22 Trimming capacitor

Publications (1)

Publication Number Publication Date
JPH07183163A true JPH07183163A (en) 1995-07-21

Family

ID=18383360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34642893A Withdrawn JPH07183163A (en) 1993-12-22 1993-12-22 Trimming capacitor

Country Status (1)

Country Link
JP (1) JPH07183163A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002015941A (en) * 2000-06-28 2002-01-18 Matsushita Electric Ind Co Ltd Chip-type electronic component
JP2002033236A (en) * 2000-07-13 2002-01-31 Matsushita Electric Ind Co Ltd Chip-type electronic component
KR101309326B1 (en) * 2012-05-30 2013-09-16 삼성전기주식회사 Laminated chip electronic component, board for mounting the same, packing unit thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002015941A (en) * 2000-06-28 2002-01-18 Matsushita Electric Ind Co Ltd Chip-type electronic component
JP2002033236A (en) * 2000-07-13 2002-01-31 Matsushita Electric Ind Co Ltd Chip-type electronic component
JP4581194B2 (en) * 2000-07-13 2010-11-17 パナソニック株式会社 Chip-type electronic components
KR101309326B1 (en) * 2012-05-30 2013-09-16 삼성전기주식회사 Laminated chip electronic component, board for mounting the same, packing unit thereof
US20130321981A1 (en) 2012-05-30 2013-12-05 Young Ghyu Ahn Laminated chip electronic component, board for mounting the same, and packing unit thereof
KR20130135015A (en) * 2012-05-30 2013-12-10 삼성전기주식회사 Laminated chip electronic component, board for mounting the same, packing unit thereof
US8638543B2 (en) 2012-05-30 2014-01-28 Samsung Electro-Mechanics Co., Ltd. Laminated chip electronic component, board for mounting the same, and packing unit thereof
KR101504001B1 (en) * 2012-05-30 2015-03-18 삼성전기주식회사 Laminated chip electronic component, board for mounting the same, packing unit thereof

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