JP6483400B2 - Multilayer capacitor and mounting structure - Google Patents

Description

  The present invention relates to a multilayer capacitor, and more particularly to, for example, a multilayer capacitor having a multilayer body in which a plurality of dielectric layers and internal electrodes are alternately stacked.

  In multilayer capacitors, dielectric layers and internal electrodes are alternately stacked, and a ferroelectric material such as barium titanate with a relatively high dielectric constant is generally used as the ceramic material for the dielectric. It has been. When an AC voltage is applied to such a multilayer capacitor, distortion occurs in the dielectric layer due to the electrostrictive effect, and vibration occurs in the multilayer capacitor itself. The vibration of the multilayer capacitor propagates to the substrate on which the multilayer capacitor is mounted via solder or the like, and the vibration propagated to the substrate causes the substrate to resonate and amplify the vibration, and vibration sound is generated in the substrate. When the vibration frequency of the substrate becomes an audible frequency band, an audible sound is generated from the substrate. That is, a so-called “sounding” phenomenon occurs. Specifically, when a multilayer capacitor is mounted with an external electrode and a substrate via solder, the vibration of the multilayer capacitor deforms the substrate via the solder adhering to the external electrode. Sound will be generated.

  In order to reduce vibration noise in such a substrate, a multilayer capacitor having a multilayer capacitor body having a pair of external electrodes on opposite side surfaces and a pair of external terminals connected to the pair of external electrodes is used. It has been. In such a multilayer capacitor, a pair of external terminals are connected to a pair of external electrodes, and the multilayer capacitor body is floated from the substrate by the pair of external terminals and mounted on the substrate. By adopting such a configuration, vibration generated in the multilayer capacitor main body is hardly propagated to the substrate, and generation of vibration noise on the substrate due to the multilayer capacitor main body is suppressed. An example of such a multilayer capacitor is disclosed in Patent Document 1.

JP 2012-23322 A

  However, the above-described multilayer capacitor is provided with a multilayer capacitor body floating from the substrate using a pair of external terminals, and the vibration of the multilayer capacitor body is difficult to propagate to the substrate with a pair of external terminals. There has been a problem that the structure is complicated by newly providing a pair of external terminals that suppresses “squeal”.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide a multilayer capacitor capable of suppressing “sounding”.

In the multilayer capacitor of the present invention, a plurality of dielectric layers are stacked to connect the first and second main surfaces facing each other and the first and second main surfaces facing each other. a second end surface connecting between said first and second end surfaces, and a substantially rectangular parallelepiped laminate having a first and second side surfaces facing each other, of the plurality of dielectric layers of the laminate a plurality of internal electrodes are arranged at intervals in the stacking direction, are arranged in the first and second end surfaces, and a pair of external electrodes being electrically connected to the internal electrode the pair of external electrodes has a plated layer positioned outside of the conductive resin layer and the base electrode including a conductive resin layer covering the metallic layer and the metal layer, wherein the base electrode is , An end surface covering the first and second end surfaces, and the end surface from the end surface A first main surface extending portion extending to the main surface, a second main surface extending portion extending to the second main surface, and a first extending from the end surface portion to the first side surface. 1 side extending portion and has a second side extending portion extending in the second aspect, the first major surface of the laminate is the mounting surface, before Kitan surface And a ridge line portion located between the first main surface extension portion, and a ridge line portion located between the first and second side surface extension portions and the first main surface extension portion, and the conductive resin layer is characterized in that it is exposed from the plating layer in.

  According to the multilayer capacitor of the present invention, since only the lower surface portions of the pair of external electrodes become the solder adhesion portions, it is possible to make it difficult for vibration to propagate to the substrate.

(A) is a schematic perspective view which shows the multilayer capacitor | condenser which concerns on embodiment, (b) is sectional drawing cut | disconnected by the AA line of the multilayer capacitor | condenser shown to (a). (A)-(c) is explanatory drawing for demonstrating the formation area of the plating layer formed in the base electrode. It is sectional drawing which expands and shows the principal part C of the multilayer capacitor | condenser shown in FIG.1 (b). (A) is a perspective view showing a state in which the multilayer capacitor shown in FIG. 1 is mounted on a substrate, and (b) is a multilayer capacitor in a state where the multilayer capacitor shown in (a) is mounted on a substrate. It is sectional drawing cut | disconnected by the BB line | wire. FIG. 5 is an enlarged cross-sectional view illustrating a main part D of the multilayer capacitor illustrated in FIG.

<Embodiment>
Hereinafter, a multilayer capacitor 10 according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic perspective view showing a multilayer capacitor 10 according to an embodiment of the present invention. The multilayer capacitor 10 includes a dielectric layer of ceramic material and internal electrodes 2 (first internal electrode 2a and first internal electrode 2). 2 internal electrodes 2b), dielectric layers and internal electrodes 2 are alternately stacked, and a pair of external electrodes 3 (first external electrode 3a and second external electrode 3b) It is electrically connected to the internal electrode 2 drawn out to the first and second end faces 1c, 1d. That is, in the internal electrode 2, the first internal electrode 2a is electrically connected to the first external electrode 3a, and the second internal electrode 2b is electrically connected to the second external electrode 3b. . In addition, for convenience, the multilayer capacitor 10 defines an orthogonal coordinate system XYZ, and appropriately uses terms of an upper surface or a lower surface, with the positive side in the Z direction being the upper side.

  The multilayer capacitor 10 is mounted on a circuit board (hereinafter referred to as a board 9) via a solder 7. The substrate 9 is used in, for example, a notebook personal computer, a smartphone, a mobile phone, or the like. For example, an electric circuit on which the multilayer capacitor 10 is electrically connected is formed on the surface.

As shown in FIG. 4, the substrate 9 is provided with, for example, a substrate electrode 9a and a substrate electrode 9b on the surface on which the multilayer capacitor 10 is mounted, and wiring (not shown) is provided from the substrate electrode 9a. ) And a wiring (not shown) extends from the substrate electrode 9b. In the multilayer capacitor 10, for example, the first external electrode 3a and the substrate electrode 9a are soldered by soldering, and the second external electrode 3b and the substrate electrode 9b are soldered by soldering.

  As shown in FIG. 1, the multilayer capacitor 10 includes a multilayer body 1, internal electrodes 2 (first internal electrode 2 a and second internal electrode 2 b) formed in the multilayer body 1, and multilayer body 1. The first and second end faces 1c, 1d of the first and second end faces 1c, 1d are electrically connected to the internal electrode 2 drawn out to the first and second end faces 1c, 1d (first External electrode 3a and second external electrode 3b).

  The laminated body 1 is formed in a substantially rectangular parallelepiped shape by laminating a plurality of dielectric layers, and first and second end faces 1c facing each other and the first and second main faces 1a and 1b facing each other, 1d and first and second side surfaces 1e and 1f facing each other. The first and second end faces 1c, 1d facing each other connect the first and second main faces 1a, 1b, and the first and second side faces 1e, 1f facing each other. Connects the first and second main faces 1a, 1b and the first and second end faces 1c, 1d. Note that the substantially rectangular parallelepiped shape includes not only a cubic shape or a rectangular parallelepiped shape, but also includes, for example, a shape in which the ridge line portion of the rectangular parallelepiped is chamfered and the ridge line portion has an R shape.

  The laminated body 1 is a sintered body obtained by laminating and firing a plurality of ceramic green sheets serving as dielectric layers. Thus, the laminated body 1 is formed in a substantially rectangular parallelepiped shape, and is formed on the first main surface 1a and the second main surface 1b, the first main surface 1a, and the second main surface 1b facing each other. The first end face 1c and the second end face 1d that are orthogonal and face each other, and the first side face 1e and the second side face 1f that are orthogonal to the first end face 1c and the second end face 1d and face each other. And have. Moreover, the laminated body 1 has a rectangular plane as a cross section (XY plane) in a direction orthogonal to the stacking direction (Z direction) of the dielectric layers. In the multilayer capacitor 10, each ridge line portion of the multilayer body 1 may be rounded.

  The dimension of the multilayer capacitor 10 having such a configuration is such that the length in the longitudinal direction (Y direction) is, for example, 0.6 (mm) to 2.2 (mm), and the length in the short direction (X direction). However, the length in the height direction (Z direction) is, for example, 0.3 (mm) to 1.5 (mm), for example, 0.3 (mm) to 1.2 (mm).

  The dielectric layer has a rectangular shape in a plan view from the stacking direction, and the thickness per layer is, for example, 0.5 (μm) to 3 (μm). In the laminated body 1, for example, a plurality of dielectric layers made of 10 (layers) to 1000 (layers) are laminated in the Z direction. The number of internal electrodes 2 in the multilayer body 1 is appropriately designed according to the characteristics of the multilayer capacitor 10.

The dielectric layer is, for example, barium titanate (BaTiO ₃ ), calcium titanate (CaTiO ₃ ), strontium titanate (SrTiO ₃ ), or calcium zirconate (CaZrO ₃ ). The dielectric layer preferably uses barium titanate as a ferroelectric material having a high dielectric constant from the viewpoint of a high dielectric constant.

  The plurality of internal electrodes 2 include a first internal electrode 2a and a second internal electrode 2b. The first internal electrode 2a and the second internal electrode 2b are opposed to each other with a predetermined interval. As shown in FIG. 1B, the plurality of dielectric layers in the multilayer body 1 are alternately arranged in the lamination direction at a predetermined interval, and the first main surface 1a and the first main surface 1a of the multilayer body 1 are arranged. 2 are provided so as to be substantially parallel to the main surface 1b. The first internal electrodes 2a and the second internal electrodes 2b are paired and alternately arranged in the stacked body 1.

As described above, the first internal electrode 2a and the second internal electrode 2b are separated from each other by the dielectric layer in the multilayer body 1 and are disposed so as to face each other. The first internal electrode 2a and the second internal electrode 2b At least one dielectric layer is sandwiched between the internal electrode 2b. A plurality of dielectric layers on which the internal electrodes 2 are formed are laminated to form the multilayer body 1 of the multilayer capacitor 10.

  As shown in FIG. 1B, the first internal electrode 2a is disposed between the dielectric layers, and one end portion is drawn out to the first end face 1c, and the second internal electrode 2b is Arranged between the dielectric layers, one end is drawn out to a second end face 1d facing the first end face 1c.

  The conductive material of the first and second internal electrodes 2a and 2b is, for example, a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd) or gold (Au), or these For example, an alloy material such as an Ag—Pd alloy including one or more of the above metal materials. The first and second internal electrodes 2a and 2b have an electrode thickness of, for example, 0.5 (μm) to 2 (μm), and the thickness may be set as appropriate depending on the application. The first internal electrode 2a and the second internal electrode 2b are preferably formed of the same metal material or alloy material.

  The pair of external electrodes 3 are formed on the first and second end faces 1c and 1d, respectively, and are electrically connected to the internal electrode 2 drawn to the first end face 1c or the second end face 1d. . Specifically, the first external electrode 3a is disposed on the first end face 1c, and is electrically connected to the first internal electrode 2a drawn out to the first end face 1c. The second external electrode 3b is disposed on the second end face 1d, and is electrically connected to the second internal electrode 2b drawn to the second end face 1d.

  As described above, the pair of external electrodes 3 includes the first external electrode 3a and the second external electrode 3b, and is formed so as to cover the first and second end faces 1c and 1d. The external electrode 3a and the second external electrode 3b are arranged so as to face each other. As shown in FIG. 1, the pair of external electrodes 3 are formed so as to cover the first and second end faces 1c and 1d, and in the stacked body 1, the first and second end faces 1c, The first and second main faces 1a and 1b are formed to extend from 1d to the surfaces of the first and second main faces 1a and 1b, respectively, and from the first and second end faces 1c and 1d to the first and second side faces 1e and 1f. Each is formed extending on the surface.

  Thus, the pair of external electrodes 3 (the first external electrode 3a and the second external electrode 3b) are formed on the surface (end surface, main surface, and side surface) of the multilayer body 1 as shown in FIG. The base electrode 4 includes a metal layer 4g and a conductive resin layer 4h covering the metal layer 4g. The plating layer 5 includes: It is formed on the surface of the conductive resin layer 4h so as to cover the conductive resin layer 4h.

  The base electrode 4 has a first end surface portion 4c and a second end surface portion 4d, the first end surface portion 4c covers the first end surface 1c, and the second end surface portion 4d is the first end surface portion 4d. 2 end face 1d is covered. Further, the base electrode 4 has a first main surface extension portion 4a and a second main surface extension portion 4b, and the first main surface extension portion 4a is a first end surface portion 4c and The second main surface 1b extends from the second end surface portion 4d to the first main surface 1a, and the second main surface extending portion 4b extends from the first end surface portion 4c and the second end surface portion 4d to the second main surface 1b. It extends to. Further, the base electrode 4 has a first side surface extension portion 4e and a second side surface extension portion 4f, and the first side surface extension portion 4e has the first end surface portion 4c and the second side surface extension portion 4e. The end surface portion 4d extends to the first side surface 1e, and the second side surface extension portion 4f extends from the first end surface portion 4c and the second end surface portion 4d to the second side surface 4f. .

Thus, the base electrode 4 includes the metal layer 4g and the conductive resin layer 4h, and the metal layer 4g is formed on the surface (end surface, main surface, and side surface) of the multilayer body 1. That is, the metal layer 4
h is formed so as to extend from the first end face 1c and the second end face 1d to the first and second main faces 1a and 1b, and the first end face 1c and the second end face 1d. To the first and second side faces 1e and 1f. The conductive resin layer 4h is formed on the surface of the metal layer 4g so as to cover the metal layer 4g.

  The metal layer 4g is electrically connected to the internal electrode 2 drawn out to the first end face 1c or the second end face 1d. The conductive material of the metal layer 4g is, for example, a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au), or one or more of these metal materials. For example, an alloy material such as an Ag—Pd alloy. The pair of metal layers 4g are preferably formed of the same metal material or alloy material.

  The metal layer 4g has a thickness at the first and second main surfaces 1a and 1b of, for example, 4 (μm) to 10 (μm), and a thickness at the first and second end surfaces 1c and 1d, for example, 10 (μm) to 25 (μm), and the thickness of the first and second side surfaces 1e and 1f is, for example, 4 (μm) to 10 (μm).

  The conductive resin layer 4h of the base electrode 4 has conductivity, and is formed so as to cover the entire metal layer 4g as shown in FIG. The conductive resin layer 4h is made of a material that prevents the molten solder from adhering when the molten solder is brought into contact with the multilayer capacitor 10 from the outside. The conductive resin layer 4h is made of, for example, a resin material such as an epoxy resin, a silicone resin, or a urethane resin. As the conductive material, for example, nickel (Ni), copper (Cu), silver (Ag), platinum (Pt), Powder (filler) of a metal material such as palladium (Pd) or gold (Au), or a powder (filler) of an alloy material such as an Ag-Pd alloy containing at least one of these metal materials is included. Yes.

  Moreover, it is preferable that the resin material of the conductive resin layer 4h is made of a heat-resistant resin material that hardly deforms at a lead (Pb) -free soldering peak temperature (for example, 250 (° C.)). The conductive resin layer 4h has a thickness of the first and second main surfaces 1a and 1b of, for example, 2 (μm) to 10 (μm), and a thickness of the first and second end surfaces 1c and 1d. For example, the thickness is 5 (μm) to 25 (μm), and the thickness of the first and second side surfaces 1e and 1f is, for example, 2 (μm) to 10 (μm).

  For example, in the case of a conductive resin material made of an epoxy resin, the conductive resin layer 4h contains 70 (wt%) to 85 (wt%) of silver powder (filler) as the conductive material. The elastic modulus is in the range of 1 (PGa) to 10 (PGa).

  The conductive resin layer 4h has a plating layer 5 formed on the surface for solder bonding with the substrate electrodes 9a and 9b. The plating layer 5 covers the conductive resin layer 4h so as to cover the conductive resin layer 4h. The pair of external electrodes 3 is mounted on the substrate electrode 9a and the substrate electrode 9b of the substrate 9 via the solder 7 easily and reliably by a reflow method or the like.

  Here, the formation region of the plating layer 5 on the conductive resin layer 4h will be described below. 2 is an explanatory diagram for explaining the formation region of the plating layer 5, and FIG. 2 (a) is a diagram of the multilayer capacitor 10 viewed from a direction (Z direction) orthogonal to the XY plane. 2B is a view of the multilayer capacitor 10 viewed from a direction (X direction) orthogonal to the ZY plane, and FIG. 2C is a direction orthogonal to the ZX plane (Y It is the figure seen from (direction).

In the pair of external electrodes 3a and 3b, the ridge line part 6a is located between the first and second end face parts 4c and 4d and the first main surface extension part 4a, and the ridge line part 6b is the first The plating layer 5 is located between the first and second end face parts 4c, 4d and the second main surface extension part 4b.
As shown, the conductive resin layer 4h is exposed at the ridge line portion 6a and the ridge line portion 6b.

  The pair of external electrodes 3a and 3b has a ridge line portion 6c located between the first and second side surface extension portions 4e and 4f and the first main surface extension portion 4a. The portion 6d is located between the first and second side surface extending portions 4e, 4f and the second main surface extending portion 4b, and the plating layer 5 is conductive at the ridge line portion 6c and the ridge line portion 6d. The resin layer 4h is formed so as to be exposed.

  The pair of external electrodes 3a and 3b has a ridge line portion 6e positioned between the first and second end surface portions 4c and 4d and the first side surface extension portion 4e, and the ridge line portion 6f Located between the first and second end face parts 4c, 4d and the second side surface extension part 4f, the plating layer 5 exposes the conductive resin layer 4h at the ridge line part 6e and the ridge line part 6f. It is formed as follows.

  Further, the corner portion of the multilayer capacitor 10 is included in any ridge line portion 6, and the plating layer 5 is formed so that the conductive resin layer 4h is exposed. For example, the plating layer 5 is formed such that the conductive resin layer 4h is exposed at a portion (corner portion) where the ridge line portion 6a, the ridge line portion 6c, and the ridge line portion 6e intersect. Further, in the ridge line portion 6e and the ridge line portion 6f, when the plating layer 5 is formed so that the conductive resin layer 4h is not exposed, the plating layer 5 is formed at a portion where the ridge line portion 6a and the ridge line portion 6c intersect. The conductive resin layer 4h is formed to be exposed.

  As shown in FIG. 2A, the ridge line portion 6e is first in the direction (XY plane) perpendicular to the first end surface portion 4c, the second end surface portion 4d, and the first side surface extending portion 4e. The side surface extending portion 4e side and the first end surface portion 4c side each have a starting point that is curved, and the first side surface extending portion 4e side, the second end surface portion 4d side, Each has a starting point that is curved. Further, the ridge line portion 6f is formed on the second side surface extension portion 4f side in a direction (XY plane) orthogonal to the first end surface portion 4c, the second end surface portion 4d, and the second side surface extension portion 4f. The first end surface portion 4c side has a start point that is curved, and the second side surface extension portion 4f side and the second end surface portion 4d side are start points that are curved. have. Note that the curved shape includes those in which the ridge line portions 6e and 6f are curved or those in which the ridge line portions 6e and 6f are rounded.

  Further, as shown in FIG. 2B, the ridge line portion 6a is in a direction (ZY plane) orthogonal to the first end surface portion 4c, the second end surface portion 4d, and the first main surface extending portion 4a. The first main surface extending portion 4a side and the first end surface portion 4c side each have a starting point that is curved, and the first main surface extending portion 4a side and the second main surface extending portion 4c side. Each of the end faces 4d has a starting point that is curved. Further, the ridge line portion 6b has a second main surface extending portion 4b in a direction (ZY surface) orthogonal to the first end surface portion 4c, the second end surface portion 4d, and the second main surface extending portion 4b. And the first end surface portion 4c side have respective starting points that are curved, and the second main surface extending portion 4b side and the second end surface portion 4d side are respectively curved. Has a starting point. Note that the curved shape includes those in which the ridge line portions 6a and 6b are curved or those in which the ridge line portions 6a and 6b are rounded.

Further, as shown in FIG. 2C, the ridge line portion 6c has a direction (ZX) orthogonal to the first side surface extension portion 4e and the second side surface extension portion 4f and the first main surface extension portion 4a. Surface), the first main surface extending portion 4a side and the first side surface extending portion 4e side have respective start points that are curved, and the first main surface extending portion 4a. On the side and the second side surface extension portion 4f side, there are start points that are curved. Further, the ridge line portion 6d is a second main surface in a direction (ZX surface) orthogonal to the first side surface extension portion 4e, the second side surface extension portion 4f, and the second main surface extension portion 4b. The extending portion 4b side and the first side surface extending portion 4e side each have start points that are curved, and the second main surface extending portion 4b side and the second side surface extending portion. The 4f side has a starting point that is curved. Note that the curved shape includes those in which the ridge line portions 6c and 6d are curved or those in which the ridge line portions 6c and 6d are rounded.

  As shown in FIGS. 1 and 2, the pair of external electrodes 3 a and 3 b are not formed with the plating layer 5 on each ridge line portion 6, and the plating layer 5 is formed of the conductive resin layer 4 h at each ridge line portion 6. Is formed on the conductive resin layer 4h so as to be exposed.

  For example, as shown in FIG. 3, in the external electrode 3, the plating layer 5 is not formed in a region between the start points 6 a 1 and 6 a 2 that are curved adjacent to each other in the ridge line portion 6 a. The conductive resin layer 4h of the base electrode 4 is formed so as to be exposed.

  Similarly, in the pair of external electrodes 3a and 3b, the plating layer 5 is not formed in the region between the starting points that are curved in the ridge line portions 6b to 6f. The conductive resin layer 4h is formed to be exposed.

  In addition, the multilayer capacitor 10 is provided so that each ridge line portion 6 is curved, and the occurrence of chipping or the like is suppressed. In the multilayer capacitor 10, the external electrode 3 is composed of the metal layer 4 g, the conductive resin layer 4 h, and the plating layer 5, and each ridge line portion 6 has a curved shape (curved shape). Is dispersed, and the occurrence of peeling or cracking between layers is suppressed. For example, in the multilayer capacitor 10, interlayer peeling between the metal elephant layer 4 g and the conductive resin layer 4 h or interlayer peeling between the conductive resin layer 4 h and the plating layer 5 is suppressed. Further, in the multilayer capacitor 10, since the stress at the ridge line portion 6 is dispersed, the occurrence of cracks and the like in the solder joint portion is suppressed.

  The plating layer 5 may be formed from a single plating layer, but may include a first plating layer 5a and a second plating layer 5b as shown in FIG. The first plating layer 5a is formed so as to cover the conductive resin layer 4h, and the second plating layer 5b is formed on the surface of the first plating layer 5a so as to cover the first plating layer 5a. Is formed. The plating layer 5 is formed of one or a plurality of plating layers such as a nickel (Ni) plating layer, a copper (Cu) plating layer, a gold (Au) plating layer, or a tin (Sn) plating layer. The first plating layer 5a has a thickness of, for example, 5 (μm) to 10 (μm), and the second plating layer 5b has a thickness of, for example, 3 (μm) to 5 (μm). In the multilayer capacitor 10, the plating layer 5 includes, for example, a first plating layer 5a that is a nickel (Ni) plating layer and a second plating layer that is a tin (Sn) plating layer.

  As shown in FIG. 4, the multilayer capacitor 10 includes a substrate in which the first external electrode 3 a and the substrate electrode 9 a are interposed via solder, and the second external electrode 3 b and the substrate electrode 9 b are interposed in the solder 7. 9 will be implemented.

  As shown in FIG. 4, in the first external electrode 3a, the plating layer 5 of the first main surface extending portion 4a and the substrate electrode 9a are solder-bonded via the solder 7. In the external electrode 3 b, the plating layer 5 of the first main surface extending portion 4 a and the substrate electrode 9 b are soldered via the solder 7. Therefore, in the multilayer capacitor 10, the lower surface portions of the pair of external electrodes 3a and 3b serve as solder adhesion portions, and are soldered between the plating layer 5 of the first main surface extending portion 4a and the substrate electrodes 9a and 9b. ing.

Thus, as shown in FIG. 4, the first external electrode 3a is joined to the substrate electrode 9a on the substrate 9 via the solder 7, and the ridge line portion 6a is connected to the first end face portion 4c and the first end portion 4c. Main surface extension 4a
In this ridge 6a, the plating layer 5 is not formed, and the conductive resin layer 4h of the base electrode 4 is exposed, and the exposed portion of the conductive resin layer 4h is exposed. Solder non-adhered part. Accordingly, the first external electrode 3a is prevented from forming a fillet of the solder 7 from the plating layer 5 of the first main surface extending portion 4a to the plating layer 5 of the first end surface portion 4c. That is, in the first external electrode 3a, the region where the conductive resin layer 4h is exposed in the ridge line portion 6a becomes a non-attached portion of the solder 7, and the solder 7 is plated on the first main surface extending portion 4a in the molten state. The flow from the layer 5 toward the plating layer 5 of the first end surface portion 4c is suppressed, and a fillet is not formed at the first end surface portion 4c.

  Similarly, as shown in FIG. 4, the second external electrode 3b is joined to the substrate electrode 9b on the substrate 9 via the solder 7, and the ridge line portion 6a is connected to the second end surface portion 4d and the second end surface portion 4d. 1, the plating layer 5 is not formed on the ridge 6a, and the conductive resin layer 4h of the base electrode 4 is exposed. The exposed portion of the conductive resin layer 4h becomes a solder non-adhered portion. Therefore, the second external electrode 3b is prevented from forming a fillet of the solder 7 from the plating layer 5 of the first main surface extending portion 4a to the plating layer 5 of the second end surface portion 4d. That is, in the second external electrode 3b, a region where the conductive resin layer 4h is exposed in the ridge portion 6a is a non-attached portion of the solder 7, and the solder 7 is plated on the first main surface extending portion 4a in the molten state. The flow from the layer 5 toward the plating layer 5 of the second end surface portion 4d is suppressed, and the fillet is not formed at the second end surface portion 4d.

  For example, as shown in FIG. 5, in the external electrode 3, the plating layer 5 is not formed in the region between the start points 6 a 1 and 6 a 2 that are curved in the ridge line portion 6 a, and the conductive resin of the base electrode 4 is formed. The plating layer 5 is formed so that the layer 4h is exposed. Therefore, in the multilayer capacitor 10, the region where the conductive resin layer 4 h is exposed in the ridge portion 6 a becomes a non-attached portion of the solder 7, and the solder 7 is a plating layer of the first main surface extending portion 4 a in the molten state. The flow from 5 toward the plating layer 5 of the second end surface portion 4d is suppressed, and the fillet is not formed at the second end surface portion 4d.

  Therefore, as shown in FIG. 4, in the pair of external electrodes 3, in the ridge portion 6a, the region where the conductive resin layer 4h is exposed becomes a non-attached portion of the solder 7, and the first and second end surface portions 4c, 4d No fillet of solder 7 is formed on the plating layer 5.

  Further, as shown in FIG. 4, the first external electrode 3 a and the second external electrode 3 b are joined to the substrate electrode 9 a and the substrate electrode 9 b on the substrate 9 via the solder 7, and the ridge line portion 6 c is formed. It is located between the first side surface extension portion 4e and the first main surface extension portion 4a and between the second side surface extension portion 4f and the first main surface extension portion 4a, and this In the ridge 6c, the plating layer 5 is not formed, and the conductive resin layer 4h of the base electrode 4 is exposed, and the exposed portion of the conductive resin layer 4h becomes a solder non-adhered portion. Therefore, in the first external electrode 3a and the second external electrode 3b, the fillet of the solder 7 is extended from the plating layer 5 of the first main surface extension portion 4a to the first side surface extension portion 4e and the second side surface extension. It is not formed over the plating layer 5 of the existing portion 4f.

  That is, in the first external electrode 3a and the second external electrode 3b, the region where the conductive resin layer 4h is exposed in the ridge portion 6c is a non-attached portion of the solder 7, and the solder 7 is in the molten state in the first main electrode 3a. Flow from the plating layer 5 of the surface extension portion 4a toward the plating layer 5 on the surface of the first side surface extension portion 4e and the second side surface extension portion 4f is suppressed, and the first side surface extension is performed. The fillet is not formed by the portion 4e and the second side surface extending portion 4f.

  Therefore, as shown in FIG. 4, in the pair of external electrodes 3, in the ridge line portion 6c, the region where the conductive resin layer 4h is exposed becomes a non-attached portion of the solder 7, and the first and second side surface extending portions 4e. The fillet of the solder 7 is not formed on the 4f plating layer 5.

  Further, the ridge line portion 6e is located between the first side surface extension portion 4e and the first first end surface portion 4c and between the first side surface extension portion 4e and the second end surface portion 4d. In this ridge line portion 6e, the plating layer 5 is not formed, and the conductive resin layer 4h of the base electrode 4 is exposed. Therefore, the fillet of the solder 7 is not formed on the ridge line portion 6e. Further, the ridge line portion 6f is located between the second side surface extension portion 4f and the first first end surface portion 4c and between the second side surface extension portion 4f and the second end surface portion 4d. Since the plating layer 5 is not formed on the ridge line portion 6f and the conductive resin layer 4h of the base electrode 4 is exposed, the fillet of the solder 7 is not formed on the ridge line portion 6f.

  In the pair of external electrodes 3a and 3b, the ridge portions 6e and 6f are located between the first and second side surface extending portions 4e and 4f and the first and second end surface portions 4c and 4d. Although the layer 5 is formed so that the conductive resin layer 4h is exposed at the ridge lines 6e and 6f, the plating layer 5 may be formed so that the conductive resin layer 4h is not exposed at the ridge lines 6e and 6f. Good.

  The first and second external electrodes 3a and 3b have a ridge line portion 6b located between the first end surface portion 4c and the second main surface extension portion 4b. In the ridge line portion 6b, The plating layer 5 is not formed, the conductive resin layer 4h of the base electrode 4 is exposed, and the exposed portion of the conductive resin layer 4h becomes a solder non-adhered portion. In the first and second external electrodes 3a and 3b, the ridge line portion 6d is between the first side surface extension portion 4e and the second main surface extension portion 4b, and between the second side surface extension portion 4f and the second side electrode extension portion 4f. The plating layer 5 is not formed in the ridge line portion 6d, and the conductive resin layer 4h of the base electrode 4 is exposed at the ridge line portion 6b. The exposed portion of the resin layer 4h becomes a solder non-adhered portion.

  Thus, the pair of external electrodes 3a and 3b has the plating layer 5 formed so that the conductive resin layer 4h is exposed, and the ridge line portions 6a to 6f are non-solder-attached portions. The capacitor 10 can be mounted in either direction with respect to the substrate 9.

  As described above, in the multilayer capacitor 10, the pair of external electrodes 3 are soldered to the substrate electrode 9a and the substrate electrode 9b only by the plating layer 5 of the first main surface extending portion 4a.

  For example, when a multilayer capacitor is composed of, for example, barium titanate as a main component as a dielectric layer, the multilayer capacitor has a large AC voltage due to an electrostrictive effect when an AC voltage is applied. Accordingly, distortion occurs in the dielectric layer. This distortion causes vibration in the multilayer capacitor itself, and the vibration is propagated to the substrate 9, causing the substrate 9 to vibrate. When this vibration is in an audible frequency band, the vibration of the substrate 9 becomes a vibration sound. Will appear.

  However, in the multilayer capacitor 10 according to the embodiment, since the plating layer 5 is formed so that the conductive resin layer 4h is exposed at the ridge line portion 6a and the ridge line portion 6c, the pair of external electrodes 3a, 3b Means that the plating layer 5 of the first main surface extending portion 4a of the base electrode 4 and the substrate electrodes 9a, 9b are soldered together, while the first and second end surface portions 4c, 4d, The fillet of the solder 7 is not formed on the first and second side surface extending portions 4e and 4f.

  As described above, the multilayer capacitor 10 has no fillet formed in the first and second end surface portions 4c, 4d and the first and second side surface extending portions 4e, 4f, and therefore vibrations through the fillet Is suppressed, the vibration due to the generated distortion is hardly transmitted to the substrate 9, and the generation of vibration noise on the substrate 9 can be suppressed. Therefore, in the multilayer capacitor 10, the vibration of the substrate 9 is suppressed, so that "sounding" is less likely to occur, and the effect of suppressing vibration noise can be improved.

  That is, when an AC voltage is applied, the multilayer capacitor 10 tends to expand and contract easily at the center portions of the first and second end face portions 4c and 4d. Thus, the first and second expansion and contraction are large. Since the fillet 5 of the solder 7 is not formed on the plating layer 5 of the end face portions 4c and 4d, vibration to the substrate can be more effectively suppressed. Further, the first and second side surface extending portions 4e and 4f are easily expanded and contracted, and no solder 7 fillet is formed on the plating layer 5 of the first and second side surface extending portions 4e and 4f. Therefore, vibration to the substrate can be further effectively suppressed.

  In the multilayer capacitor 10, the conductive resin layer 4 h is exposed at the ridge line portion 6, and the exposed portion of the conductive resin layer 4 h becomes a solder non-adhered portion, and the solder non-adhered portion causes the solder 7 to flow. Therefore, the fillet of the solder 7 can be prevented from being formed regardless of the size of the substrate electrodes 9a and 9b.

  The multilayer capacitor 10 is formed so that the conductive resin layer 4h covers the metal layer 4g, and becomes an absorber that absorbs vibration caused by the distortion generated by the conductive resin layer 4h. 9 and the generation of vibration noise on the substrate 9 can be effectively suppressed.

  In addition, when a fillet is formed on the end face part and the side face part of a multilayer capacitor, a so-called tombstone phenomenon in which the multilayer capacitor rises due to a difference in tension between the left and right (both sides) external electrodes caused by solder. It tends to happen. However, in the multilayer capacitor 10, the fillet of the solder 7 is formed on the first side surface extension portion 4e, the second side surface extension portion 4f, and the first end surface portion 4c in the pair of external electrodes 3a and 3b. In addition, since the fillet of the solder 7 is not formed on the first side surface extension portion 4e, the second side surface extension portion 4f, and the second end surface portion 4d, the tombstone phenomenon is suppressed. Can do.

  Here, an example of a manufacturing method of the multilayer capacitor 10 shown in FIG. 1 will be described below.

  A plurality of first and second ceramic green sheets are prepared. The first ceramic green sheet is formed with the first internal electrode 2a, and the second ceramic green sheet is formed with the second internal electrode 2b.

  The plurality of first ceramic green sheets are formed with a first internal electrode conductor paste layer in order to form the first internal electrode 2a. The first internal electrode conductor paste layer is formed using the conductor paste for the first internal electrode 2a so as to have the pattern shape of the first internal electrode 2a. In the first ceramic green sheet, a plurality of first internal electrodes 2 a are formed in one ceramic green sheet in order to obtain a large number of multilayer capacitor bodies 10.

  The plurality of second ceramic green sheets are provided with a second internal electrode conductor paste layer in order to form the second internal electrode 2b. The second internal electrode conductive paste layer is formed using a conductor paste for the second internal electrode 2b so as to have the pattern shape of the second internal electrode 2b. In the second ceramic green sheet, in order to obtain a large number of multilayer capacitor bodies 10, a plurality of second internal electrodes 2b are formed in one ceramic green sheet.

  The first and second internal electrode conductor paste layers described above are formed by printing each conductor paste in a predetermined pattern shape on each ceramic green sheet using, for example, a screen printing method or the like.

  The first and second ceramic green sheets serve as dielectric layers, the first internal electrode conductor paste layer serves as the first internal electrode 2a, and the second internal electrode conductor paste layer serves as the second internal electrode 2b. Become.

Examples of the material of the ceramic green sheet used as the dielectric layer include dielectrics such as barium titanate (BaTiO ₃ ), calcium titanate (CaTiO ₃ ), strontium titanate (SrTiO ₃ ), or calcium zirconate (CaZrO ₃ ). The main component is ceramics. For example, a Mn compound, Fe compound, Cr compound, Co compound, or Ni compound may be added as the accessory component.

  The first and second ceramic green sheets are prepared by adding a suitable organic solvent and the like to the dielectric ceramic raw material powder and the organic binder and mixing them, and using a doctor blade method or the like. It is obtained by forming a ceramic slurry.

  The conductor paste for the first and second internal electrodes 2a, 2b is kneaded by adding an additive (dielectric material), a binder, a solvent, a dispersant, etc. to the powder of each of the above-described conductor materials (metal materials). It is produced by. The conductive material of the first and second internal electrodes 2a and 2b is, for example, a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au), or a metal thereof. For example, an alloy material such as an Ag—Pd alloy including one or more materials may be used. The first and second internal electrodes 2a and 2b are preferably formed of the same metal material or alloy material.

  The first ceramic green sheet is formed with a first internal electrode 2a, and the second ceramic green sheet is formed with a second internal electrode 2b. The first ceramic green sheet and the second ceramic green sheet A plurality of ceramic green sheets are alternately laminated, and ceramic green sheets on which no internal electrodes are formed are laminated on the outermost layer in the lamination direction, thereby producing a laminate made of a ceramic material.

  Thus, the laminated body which consists of a some 1st and 2nd ceramic green sheet becomes a large-sized raw laminated body containing many raw laminated bodies 1 by pressing and integrating. By cutting this large green laminate, a green laminate 1 that becomes the laminate 1 of the multilayer capacitor body 10 as shown in FIG. 1 can be obtained. The large green laminate can be cut using, for example, a dicing blade.

  And the laminated body 1 can be obtained by baking the raw laminated body 1 at 800 (degreeC) -1300 (degreeC), for example. By this step, the plurality of first and second ceramic green sheets become dielectric layers, the first internal electrode conductor paste layer becomes the first internal electrode 2a, and the second internal electrode conductor paste layer becomes the second internal electrode. It becomes the internal electrode 2b. Moreover, the laminated body 1 can round a corner | angular part or a side part using grinding | polishing means, such as barrel grinding | polishing, for example. The laminated body 1 becomes a thing which a corner | angular part or a side part cannot be easily chipped by rounding a corner | angular part or a side part.

  Next, a pair of external electrodes 3 composed of the base electrode 4 and the plating layer 5 are formed. The base electrode 4 includes a metal layer 4g and a conductive resin layer 4h covering the metal layer 4g, and is formed on the first and second end faces 1c and 1d. For example, the metal layer 4g forms a pair of metal layers 4g by applying and baking a conductive paste for the metal layer 4g to be the metal layer 4g on the first and second end faces 1c and 1d of the laminate 1.

Further, the conductive paste for the metal layer 4g is prepared by adding a binder, a solvent, a dispersant and the like to the powder of the metal material constituting the metal layer 4g and kneading. The conductive material of the metal layer 4g is, for example, a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au), or one or more of these metal materials. For example, an alloy material such as an Ag—Pd alloy. The metal layer 4g may be formed by using a thin film forming method such as a vapor deposition method, a plating method, or a sputtering method, in addition to using a method of baking a conductor paste.

  The conductive resin layer 4h is formed on the surface of the metal layer 4g so as to cover the metal layer 4g. For example, the conductive resin layer 4h is formed on the surface of the metal layer 4g as follows. The conductive resin layer 4h is formed using a conductive paste, and the conductive paste becomes the conductive resin layer 4h. The conductive paste is produced, for example, by adding and kneading a conductive material powder (filler), a binder, a solvent, a dispersant, and the like to the above-described resin material.

  First, a flat stage having a recess (dent) for holding a conductive paste is prepared. And the conductive pace used as the conductive resin layer 4h is discharged to the recessed part of this stage using a dispenser etc., for example. Furthermore, in order to make the thickness of the conductive paste uniform, the thickness of the discharged conductive paste is made uniform using a squeegee or the like.

  Next, the portion of the pair of external electrodes 3 where the metal layer 4g of the first external electrode 3a is formed is dipped on the uniform conductive paste, and the conductive paste is transferred to the surface of the metal layer 4g. . Similarly, the portion of the first external electrode 3a where the metal layer 4g is formed is dipped in the uniform conductive paste, and the conductive paste is transferred to the surface of the metal layer 4g.

  Then, using a drying furnace or the like, the transferred conductive paste is dried and cured to form the conductive resin layer 4h so as to cover the metal layer 4g.

  Next, the plating layer 5 is formed on the surface of the conductive resin layer 4h so as to cover the conductive resin layer 4h. The plating layer 4h is formed on the surface of the conductive resin layer 4h using, for example, an electrolytic plating method or the like. The conductive resin layer 4h is, for example, a single plating layer or a plurality of plating layers such as a nickel (Ni) plating layer, a copper (Cu) plating layer, a gold (Au) plating layer, or a tin (Sn) plating layer. Formed on the surface. Although the plating layer 5 may be formed from a single plating layer, the multilayer capacitor 10 includes a laminated body in which the plating layer 5 includes a first plating layer 5a and a second plating layer 5b. Is formed on the surface. In the multilayer capacitor 10, for example, the first plating layer 5a is made of a nickel (Ni) plating layer, the second plating layer 5b is made of a tin (Sn) plating layer, and the tin (Sn) of the second plating layer 5b is made. ) The plating layer is formed so as to cover the nickel (Ni) plating layer of the first plating layer 5a. At this stage, the plating layer 5 is formed over the entire base electrode 4 of the pair of external electrodes 3, and the conductive resin layer 4 h is not exposed at each ridge line portion 6 of the pair of external electrodes 3.

  Next, the pair of external electrodes 3 a and 3 b expose the conductive resin layer 4 h at each ridge line portion 6. For example, by polishing each ridge line part 6 (corner part and side part) using a polishing means such as barrel polishing, the conductive resin layer 4h under the plating layer 5 can be exposed at the ridge line part 6. . By using the polishing means, the ridge line portions 6 a to 6 f can expose the conductive resin layer 4 h from the plating layer 5 without forming the plating layer 5.

  Thus, the 1st external electrode 3a and the 2nd external electrode 3b are formed so that the conductive resin layer 4h may be exposed in the plating layer 5 in the ridgeline parts 6a-6f. In the first external electrode 3a and the second external electrode 3b, the conductive resin layer 4h is exposed at each ridge line portion 6, and each ridge line portion 6 is curved.

  The present invention is not particularly limited to the above-described embodiments, and various changes and improvements can be made within the scope of the present invention.

  For example, in the above-described embodiment, the general multilayer capacitor 10 has been described as an example. However, the external electrode 3 is not limited to the two multilayer capacitors 10, and the present invention has three terminals with three external electrodes. The present invention can also be applied to the multilayer capacitor. That is, even in a three-terminal multilayer capacitor, the effect of suppressing vibration noise can be improved by applying the technique of the present invention and forming a solder non-adhered portion at the ridge line portion of the external electrode.

DESCRIPTION OF SYMBOLS 1 Laminate 1a 1st main surface 1b 2nd main surface 1c 1st end surface 1d 2nd end surface 1e 1st side surface 1f 2nd side surface 2 Internal electrode 2a 1st internal electrode 2b 2nd internal electrode 3 External electrode 3a 1st external electrode 3b 2nd external electrode 4 Base electrode 4a 1st main surface extension part 4b 2nd main surface extension part 4c 1st end surface part 4d 2nd end surface part 4e 1st 1 side extended portion 4 f second side extended portion 4 g metal layer 4 h conductive resin layer 5 plated layer 5 a first plated layer 5 b second plated layer 6 ridge line portion 7 solder 9 substrates 9 a and 9 b substrate electrode 10 Multilayer capacitor

Claims (2)

A plurality of dielectric layers are stacked to connect the first and second main surfaces facing each other and the first and second main surfaces, and the first and second end surfaces facing each other and the first and connecting the second end surface, a substantially rectangular parallelepiped laminate having a first and second side surfaces facing each other,
A plurality of internal electrodes arranged at intervals in the stacking direction of the plurality of dielectric layers in the stack;
Wherein arranged in the first and second end surfaces, and a pair of external electrodes being electrically connected to said internal electrodes,
Said pair of external electrodes has a plated layer positioned outside of the conductive resin layer and the base electrode including a conductive resin layer covering the metallic layer and the metallic layer,
The base electrode extends to an end surface portion covering the first and second end surfaces, a first main surface extending portion extending from the end surface portion to the first main surface, and the second main surface. A second main surface extending portion, a first side extending portion extending from the end surface portion to the first side surface, and a second side surface extending portion extending to the second side surface. Have
The first main surface of the laminate is a mounting surface,
Located between the first major surface extending portion and the ridge portion positioned between the first and second side surfaces extending portion between the front Kitan surface and the first principal surface extending portion multilayer capacitor wherein the conductive resin layer and wherein the exposed from the plating layer in each ridge. The multilayer capacitor according to claim 1 and a substrate having a substrate electrode on which the multilayer capacitor is mounted are disposed so that the first main surface extending material portion and the substrate electrode are opposed to each other, A mounting structure in which the first main surface extending material portion and the substrate electrode are joined by soldering .

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