JPH11251177A - Chip component - Google Patents
Chip componentInfo
- Publication number
- JPH11251177A JPH11251177A JP10314099A JP31409998A JPH11251177A JP H11251177 A JPH11251177 A JP H11251177A JP 10314099 A JP10314099 A JP 10314099A JP 31409998 A JP31409998 A JP 31409998A JP H11251177 A JPH11251177 A JP H11251177A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- chip component
- bottom electrode
- exclusion
- forming surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Ceramic Capacitors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、チップ部品に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip component.
【０００２】[0002]
【従来の技術】図７にはコンデンサ、抵抗等の一般的な
チップ部品の斜視図が示されている。このチップ部品１
の両端側に一対の外部電極２が形成されている。この外
部電極２は上面電極４と、底面電極５と、前後電極１０
と、側面電極３とが一体的に接続されたものである。こ
のチップ部品１を回路基板７に搭載し、半田９で接続し
た状態が図８に示されている。図９にはチップ部品１の
底面電極５と基板７側の導体部であるランド８の関係が
示されており、底面電極５に対してランド８が大きくは
み出している。このはみ出し部分を利用してチップ部品
１とランド８とを図８に示すように半田フィレット（半
田の盛り上がり形状）６を形成することによって接続し
ている。2. Description of the Related Art FIG. 7 is a perspective view of a general chip component such as a capacitor and a resistor. This chip part 1
A pair of external electrodes 2 are formed at both ends of the. The external electrode 2 includes a top electrode 4, a bottom electrode 5, and front and rear electrodes 10.
And the side electrode 3 are integrally connected. FIG. 8 shows a state in which the chip component 1 is mounted on the circuit board 7 and connected by the solder 9. FIG. 9 shows the relationship between the bottom electrode 5 of the chip component 1 and the land 8 which is a conductor on the substrate 7 side, and the land 8 protrudes greatly from the bottom electrode 5. The protruding portion is used to connect the chip component 1 and the land 8 by forming a solder fillet (bump shape of solder) 6 as shown in FIG.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来例
においては、半田フィレット６がチップ部品１から外に
大きく突き出しているので、他の回路素子をチップ部品
１に近接配置できず、高密度実装の障害となっている。
この障害は、実願平１−７３５９９号（実開平３−５６
１２１号）のマイクロフィルムに記載されているよう
に、チップ部品１の前後電極１０及び側面電極３の電極
下部に半田フィレット６を形成する場合でも発生する。However, in the conventional example, since the solder fillet 6 protrudes largely from the chip component 1, other circuit elements cannot be arranged close to the chip component 1, and high-density mounting is not possible. It is an obstacle.
This obstacle is described in Japanese Utility Model Application No. 1-73599 (Japanese Utility Model Application No. 3-56).
As described in the microfilm of No. 121), it occurs even when the solder fillet 6 is formed below the front and rear electrodes 10 and the side electrodes 3 of the chip component 1.
【０００４】また、半田フィレット６を形成してチップ
部品１と回路基板７とを接続する方式は、半田９の供給
量や形状がばらついて変わり易く、コントロールが難し
く半田接続の信頼性の上でも問題がある。Further, the method of forming the solder fillet 6 to connect the chip component 1 and the circuit board 7 is apt to change due to variations in the supply amount and shape of the solder 9 and is difficult to control, so that the solder connection reliability is high. There's a problem.
【０００５】本発明は上記従来の課題を解決するために
なされたものであり、その目的は、回路基板へチップ部
品を実装接続する際に、高密度実装、高信頼性接続を可
能にするチップ部品を提供することにある。The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a chip which enables high-density mounting and high-reliability connection when mounting and connecting chip components to a circuit board. To provide parts.
【０００６】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するために、次のように構成されている。すなわち、第
１の発明のチップ部品は、チップ部品の両端側に少なく
とも一対の外部電極を形成し、該チップ部品の両端側底
面に外部電極の一部となる底面電極を配置し、これら底
面電極領域のみにそれぞれ半田形成面を設け、この半田
形成面以外の外部電極表面を半田になじまない半田排除
面となっていることを特徴として構成されている。The present invention is configured as follows to achieve the above object. That is, in the chip component of the first invention, at least a pair of external electrodes are formed on both end sides of the chip component, and a bottom electrode serving as a part of the external electrode is arranged on the bottom surface on both ends of the chip component. It is characterized in that a solder forming surface is provided only in each of the regions, and the surface of the external electrode other than the solder forming surface is a solder exclusion surface that does not adapt to the solder.
【０００７】また第２の発明のチップ部品は、チップ部
品の底面に少なくとも一対の底面電極を形成し、この一
対の底面電極領域にそれぞれ半田形成面を設け、この半
田形成面の周りを半田になじまない半田排除面で構成し
たことを特徴として構成されている。In a chip component according to a second aspect of the present invention, at least a pair of bottom electrodes are formed on the bottom surface of the chip component, and a solder forming surface is provided in each of the pair of bottom electrode regions. It is characterized in that it is configured with a solder removal surface that does not fit.
【０００８】さらに、第３の発明のチップ部品は、前記
第１又は第２の発明の構成を備えたものにおいて、底面
電極の外端縁部は半田になじまない半田排除面とし、半
田形成面は外端縁部の半田排除面よりも内側寄りに設け
られていることを特徴として構成されている。Further, a chip component according to a third aspect of the present invention is the chip component having the configuration according to the first or second aspect, wherein an outer edge of the bottom electrode is a solder exclusion surface that is not compatible with solder, and a solder forming surface. Are characterized in that they are provided closer to the inside than the solder exclusion surface at the outer edge.
【０００９】さらに、第４の発明のチップ部品は、前記
第１又は第２の発明の構成を備えたものにおいて、底面
電極の外端縁部は全周に亙って半田になじまない半田排
除面とし、半田排除面に囲まれた局部領域に半田形成面
が設けられていることを特徴として構成されている。Further, a chip component according to a fourth aspect of the present invention is the chip component having the configuration according to the first or second aspect of the present invention, wherein the outer edge of the bottom electrode is free of solder over the entire periphery. And a solder forming surface is provided in a local area surrounded by the solder exclusion surface.
【００１０】さらに、第５の発明のチップ部品は、前記
第１又は第２の発明の構成を備えたものにおいて、底面
電極の表面を半田になじまない金属又は素材で被覆して
半田排除面とし、底面電極の局部領域に半田になじむ金
属で半田形成面を形成したことを特徴として構成されて
いる。A fifth aspect of the present invention is the chip component according to the first or second aspect, wherein the surface of the bottom electrode is covered with a metal or a material that does not mix with solder to form a solder removal surface. The solder forming surface is formed of a metal compatible with solder in a local area of the bottom electrode.
【００１１】さらに、第６の発明のチップ部品は、前記
第１又は第２の発明の構成を備えたものにおいて、底面
電極を半田になじまない金属で形成して半田排除面と
し、この半田排除面の上に半田形成面を形成したことを
特徴として構成されている。Further, according to a sixth aspect of the present invention, in the chip component having the configuration of the first or second aspect, the bottom electrode is formed of a metal which does not mix with solder to form a solder exclusion surface. It is characterized in that a solder forming surface is formed on the surface.
【００１２】さらに、第７の発明のチップ部品は、前記
第１乃至第６の何れか１つの発明の構成を備えたものに
おいて、半田形成面に半田を付着形成したことを特徴と
して構成されている。Further, a chip component according to a seventh aspect of the present invention is provided with the configuration according to any one of the first to sixth aspects, characterized in that solder is attached and formed on a solder forming surface. I have.
【００１３】上記構成の本発明において、チップ部品の
底面電極の領域に半田形成面を形成し、その半田形成面
以外の電極表面に半田排除面を設ける。チップ部品はそ
の半田形成面をランドと対向させて回路基板のランドに
搭載し、半田形成面とランドとを半田接続する。この半
田接続に際し、半田は底面電極の半田形成面以外には付
着しないので、チップ部品の外側に半田フィレットは生
じない。In the present invention having the above structure, a solder forming surface is formed in the area of the bottom electrode of the chip component, and a solder removing surface is provided on the electrode surface other than the solder forming surface. The chip component is mounted on the land of the circuit board with the solder forming surface facing the land, and the solder forming surface and the land are connected by soldering. At the time of this solder connection, the solder does not adhere to portions other than the solder forming surface of the bottom electrode, so that no solder fillet is formed outside the chip component.
【００１４】[0014]
【発明の実施の形態】以下、本発明の実施形態例を図面
に基づいて説明する。図１には本発明に係るチップ部品
の一実施形態例の要部構成図が示されている。このチッ
プ部品１の両端側には従来例と同様に一対の外部電極２
が形成されており、この外部電極２の底面電極５の白抜
き部分が、このチップ部品１の半田形成面１１を構成す
るもので、この半田形成面１１の形状は様々な形態を採
ることができ、例えば、図１の（ａ）の半田形成面１１
は矩形状を呈しており、各底面電極５の左右側外端縁５
ａ，左右側内端縁５ｂ，前側外端縁５ｃおよび後側外端
縁５ｄを半田排除面とし、この底面電極５の外端縁部全
周に亙る半田排除面に囲まれた内部の局部領域に半田形
成面１１が形成されている。見方を換えれば、この図１
の（ａ）に示すものは、底面電極５の左右側の外端縁部
５ａおよび内端縁部５ｂの半田排除面よりも内側寄りで
あって、かつ、前後側の外端縁部５ｃ，５ｄの半田排除
面よりも内側寄りに半田形成面１１を形成した構成とな
っている。そして、その半田形成面１１以外の外部電極
２の電極表面、つまり、図１の（ａ）に示す底面電極５
の斜線領域と、上面電極４と、前後電極１０と、側面電
極３との各電極表面には半田レジスト１２等の半田排除
面が形成されている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a main part of an embodiment of a chip component according to the present invention. A pair of external electrodes 2 is provided on both ends of the chip component 1 as in the conventional example.
The outline of the bottom electrode 5 of the external electrode 2 constitutes the solder forming surface 11 of the chip component 1, and the shape of the solder forming surface 11 may take various forms. For example, the solder forming surface 11 shown in FIG.
Has a rectangular shape, and the left and right outer edges 5 of each bottom electrode 5
a, the left and right inner edges 5b, the front outer edge 5c and the rear outer edge 5d are used as the solder exclusion surfaces, and the internal local area surrounded by the solder exclusion surface over the entire outer edge of the bottom electrode 5. A solder forming surface 11 is formed in the region. In other words, this figure 1
(A) is closer to the inner side than the solder exclusion surface of the outer edge 5a and the inner edge 5b on the left and right sides of the bottom electrode 5, and is the outer edge 5c on the front and rear sides. The configuration is such that the solder formation surface 11 is formed closer to the inside than the solder removal surface 5d. Then, the electrode surface of the external electrode 2 other than the solder forming surface 11, that is, the bottom electrode 5 shown in FIG.
, An upper surface electrode 4, a front and rear electrode 10, and a side surface electrode 3 are formed with a solder exclusion surface such as a solder resist 12 on each electrode surface.
【００１５】図１の（ｂ）は底面電極５の表面に円形の
半田形成面１１を左右２個ずつ計４個設け、その周りを
半田排除面としたもので、この方式は、チップ部品１を
回路基板７のランド８に搭載する際に４つの支点がある
ので載置状態が最も安定し、半田接続作業を安定に行う
ことができる。図１の（ｃ）の半田形成面１１はさらに
他の形態例を示したものである。この図１の（ｃ）に示
すものは、底面電極５の前側外端縁５ｃと後側外端縁５
ｄの部分に半田排除面１１を形成し、底面電極外端縁５
ｃ，５ｄの半田排除面１１の内側寄りに半田形成面１１
を形成した構成としてある。なお、図１の（ａ），
（ｂ），（ｃ）に示されるこれら各半田形成面１１には
適宜の手段により半田膜が形成されている。FIG. 1B shows a case in which four circular solder forming surfaces 11 are provided on the surface of the bottom electrode 5, two on each of the left and right sides, and the periphery thereof is used as a solder exclusion surface. Since there are four fulcrums when mounting on the land 8 of the circuit board 7, the mounting state is the most stable, and the solder connection work can be performed stably. The solder forming surface 11 in FIG. 1C shows another embodiment. FIG. 1C shows a front outer edge 5 c and a rear outer edge 5 c of the bottom electrode 5.
d, a solder exclusion surface 11 is formed, and a bottom electrode outer edge 5 is formed.
The solder forming surface 11 is located closer to the inside of the solder removal surface 11 of c and 5d.
Is formed. In addition, (a) of FIG.
A solder film is formed on each of the solder forming surfaces 11 shown in (b) and (c) by an appropriate means.
【００１６】図２には本実施形態例のチップ部品１を回
路基板７に搭載して半田接続した実装状態が示されてい
る。このチップ部品１を実装接続するための回路基板７
側には、導体層としてのランド８が、チップ部品１をは
み出さない大きさで形成されている。このランド８上に
は半田形成面１１をランド８に対向させてチップ部品１
をランド８に搭載し、適宜の加熱手段等によって、半田
形成面１１に形成されている半田膜を溶融して半田形成
面１１とランド８とを半田接続している。上記のように
チップ部品１と基板７とを半田接続する際に、半田９は
外部電極２の表面に形成された半田排除面には付着せ
ず、したがって、半田排除面から外にはみ出すことがな
く、半田形成面１１とランド８とが、チップ部品１の大
きさ内で半田接続されることとなり、半田の量や形状も
ばらつきなく、安定した信頼性の高い半田接続が可能と
なる。FIG. 2 shows a mounted state in which the chip component 1 of the embodiment is mounted on a circuit board 7 and soldered. Circuit board 7 for mounting and connecting this chip component 1
On the side, a land 8 as a conductor layer is formed in a size that does not protrude from the chip component 1. On this land 8, the chip component 1 is placed with the solder forming surface 11 facing the land 8.
Is mounted on the land 8, and the solder film formed on the solder forming surface 11 is melted by an appropriate heating means or the like, and the solder forming surface 11 and the land 8 are connected by soldering. When the chip component 1 and the substrate 7 are connected by soldering as described above, the solder 9 does not adhere to the solder exclusion surface formed on the surface of the external electrode 2 and therefore may protrude from the solder exclusion surface. Instead, the solder forming surface 11 and the lands 8 are connected by soldering within the size of the chip component 1, so that the amount and shape of the solder are not varied and stable and reliable soldering is possible.
【００１７】次に、本発明に係るチップ部品の製造方法
例を図面に基づいて説明する。図３〜図５は第１の製造
方法を示すもので、まず、チップ部品１の底面電極５の
局部領域、例えば円形の白抜き部（図３の（ａ））にマ
スクとして機能する低融点（６０℃程度）のパラフィン
系ワックス１３の融液をディスペンサ等によって塗布す
る。このワックス１３を塗布したチップ部品１を半田レ
ジスト１２に常温で浸漬して引き上げた後、レジスト１
２を乾燥硬化する。この状態が図４の（ａ）に示されて
いる。このチップ部品１を熱風等によって加熱して、ワ
ックス１３を除去すると、図４の（ｂ）に示すように局
部領域の電極表面１６が露出されて、半田形成面１１を
得る。この半田形成面１１の周りは半田になじまない素
材である半田レジスト１２の半田排除面となる。次い
で、このチップ部品を溶融している半田浴中に浸漬して
引き上げると図５に示すように、露出した電極表面１６
に半田９が付着形成される。Next, an example of a method for manufacturing a chip component according to the present invention will be described with reference to the drawings. FIGS. 3 to 5 show a first manufacturing method. First, a low melting point functioning as a mask in a local region of the bottom electrode 5 of the chip component 1, for example, a circular white portion (FIG. 3A). A melt of the paraffin wax 13 (about 60 ° C.) is applied by a dispenser or the like. The chip component 1 coated with the wax 13 is immersed in the solder resist 12 at room temperature and pulled up.
2 is dried and cured. This state is shown in FIG. When the chip 13 is heated by hot air or the like to remove the wax 13, the electrode surface 16 in the local region is exposed as shown in FIG. The periphery of the solder forming surface 11 becomes a solder removal surface of a solder resist 12 which is a material that does not adapt to solder. Next, when this chip component is immersed in a molten solder bath and pulled up, as shown in FIG.
Solder 9 is formed on the substrate.
【００１８】本実施形態例では、チップ部品１の底面電
極５の半田形成面１１の周りを半田排除面としたので、
チップ部品を半田浴中に浸漬して引き上げるとき、半田
形成面に付着した半田は半田排除面を通って流出するこ
とがなく、半田形成面上に定量の半田９が溜められた状
態となるので、半田量を一定量にコントロールすること
ができる。In this embodiment, the area around the solder forming surface 11 of the bottom electrode 5 of the chip component 1 is used as a solder removing surface.
When the chip component is immersed in the solder bath and pulled up, the solder attached to the solder forming surface does not flow out through the solder removing surface, and a certain amount of solder 9 is stored on the solder forming surface. The amount of solder can be controlled to a constant amount.
【００１９】次に、チップ部品の第２の製造方法を図６
に基づいて説明する。この例は半田レジスト１２の替わ
りに半田９になじまない金属層を利用して半田排除面を
形成するもので、まず、チップ部品１の両端側に設けた
一対の外部電極２の表面に半田９になじまない金属、例
えばクロム１４等をメッキして電極表面に半田排除面を
形成する。次いで、底面電極５の局部領域、つまり、半
田排除面の局部領域に半田９になじむ金属、例えば銅又
はニッケル等の金属層１５を形成して半田形成面１１を
作り、この半田形成面１１を半田浴にディップして、半
田形成面１１上に半田９を形成し、チップ部品１を作製
する。Next, a second method of manufacturing a chip component will be described with reference to FIG.
It will be described based on. In this example, a solder excluding surface is formed by using a metal layer which does not fit into the solder 9 instead of the solder resist 12. First, the surface of the pair of external electrodes 2 provided on both ends of the chip component 1 is attached to the surface of the solder 9. A solder-removing surface is formed on the surface of the electrode by plating a metal that does not fit, for example, chrome 14 or the like. Next, a metal layer 15, such as copper or nickel, which is compatible with the solder 9, is formed in a local region of the bottom electrode 5, that is, a local region of the solder removal surface, to form a solder forming surface 11, and the solder forming surface 11 is formed. The chip 9 is formed by dipping in a solder bath to form the solder 9 on the solder forming surface 11.
【００２０】本発明は、上記実施形態例に限定されるこ
とはなく、様々な実施の態様を採り得る。例えば上記各
例では底面電極５の局部領域に半田形成面を形成した
が、底面電極の全面を半田形成面としてもよい。この場
合においても底面電極以外の電極部分は半田排除面とな
っているので、半田が半田排除面側にはみ出し付着して
フィレットが生じることがなく、チップ部品を良好に基
板側のランドに接続することができる。The present invention is not limited to the above embodiment, but can adopt various embodiments. For example, although the solder forming surface is formed in the local region of the bottom electrode 5 in each of the above examples, the entire surface of the bottom electrode may be used as the solder forming surface. Also in this case, since the electrode portion other than the bottom electrode is a solder exclusion surface, the solder does not protrude and adhere to the solder exclusion surface side so that no fillet is generated, and the chip component is connected to the land on the board side satisfactorily. be able to.
【００２１】また、前述の図３の例では底面電極５の局
部領域のマスク材としてパラフィン系低融点ワックス１
３を用いたが、高融点ワックスやこれに類似の撥水性マ
スク材を用いてもよい。In the example shown in FIG. 3, a paraffin-based low melting point wax 1 is used as a mask material for a local region of the bottom electrode 5.
Although 3 was used, a high melting point wax or a similar water-repellent mask material may be used.
【００２２】また、図６の例では半田排除金属としてク
ロム１４を用いたが、これを半田９になじまない金属で
あれば、その他の金属又は金属化合物を用いてもよい。Further, in the example of FIG. 6, chromium 14 is used as the solder exclusion metal, but any other metal or metal compound may be used as long as the metal does not fit into the solder 9.
【００２３】さらに、図６の例ではクロム１４をメッキ
によって金属層を形成したが、半田９になじまない金属
層を蒸着等によって形成してもよい。Further, in the example of FIG. 6, the metal layer is formed by plating chromium 14, but a metal layer which does not fit the solder 9 may be formed by vapor deposition or the like.
【００２４】さらに、上記実施形態例では半田形成面１
１に半田９を形成したチップ部品を作製しているが、半
田９を除いたチップ部品の作製でもよく、この場合に
は、ランド８上に半田クリーム等を塗布して、半田接続
に際して加熱溶融する。Further, in the above embodiment, the solder forming surface 1
Although a chip component in which the solder 9 is formed on the chip 1 is manufactured, a chip component without the solder 9 may be manufactured. In this case, a solder cream or the like is applied on the land 8 and heated and melted at the time of solder connection. I do.
【００２５】さらに、上記実施形態例ではチップ部品１
の電極金属表面上に半田排除面を形成したが、電極を半
田になじまない導体金属によって形成して電極自体を半
田排除面とし、この半田排除面上に半田形成面を形成し
てもよい。Further, in the above embodiment, the chip component 1
Although the solder exclusion surface is formed on the electrode metal surface of the above, the electrode itself may be formed as a solder exclusion surface by forming the electrode with a conductive metal that does not adapt to solder, and the solder formation surface may be formed on this solder exclusion surface.
【００２６】[0026]
【発明の効果】本発明は、チップ部品の両端側に形成さ
れている外部電極のうち、回路基板に接続する底面電極
の領域に半田形成面を形成し、この半田形成面以外の外
部電極部には半田になじまない半田排除面を形成した構
成としたので、半田の溶融時に、溶融した半田は底面電
極の半田形成面には付着するが、半田の濡れ性に起因し
て半田排除面には付着しないことから、半田形成面から
溶融半田が流れ出て半田形成面以外の外部電極表面に半
田が漏洩付着することを防止することができる。このこ
とから、半田形成面の面積によって半田量を、また、半
田形成面の形状によって半田形状をそれぞれ制御するこ
とが可能となり、つまり、半田量および半田形状のコン
トロールが容易に可能となるので、高信頼性の半田実装
接続ができる。According to the present invention, among the external electrodes formed on both ends of a chip component, a solder forming surface is formed in a region of a bottom electrode connected to a circuit board, and an external electrode portion other than the solder forming surface is formed. Has a solder exclusion surface that is not compatible with solder, so the molten solder adheres to the solder formation surface of the bottom electrode when the solder melts, but due to the wettability of the solder, Since no solder adheres, it is possible to prevent the molten solder from flowing out from the solder forming surface and preventing the solder from leaking and attaching to the external electrode surface other than the solder forming surface. From this, the amount of solder can be controlled by the area of the solder forming surface, and the shape of the solder can be controlled by the shape of the solder forming surface.In other words, the amount of solder and the shape of the solder can be easily controlled. Highly reliable solder mounting connection is possible.
【００２７】また、上記の如く、チップ部品の外部電極
の底面電極に半田形成面を設け、この半田形成面以外の
外部電極表面を半田排除面に形成したので、半田は外部
電極のうち、底面電極の半田形成面のみに付着形成され
ることになるから、その半田形成面の半田に対応する回
路基板の領域だけに回路基板側の導体部としてのランド
を設ければよく、つまり、回路基板のランドをチップ部
品からはみ出して形成する必要がなく、回路基板のラン
ドをチップ部品からはみ出さない大きさに形成すること
ができる。Further, as described above, the solder forming surface is provided on the bottom electrode of the external electrode of the chip component, and the surface of the external electrode other than the solder forming surface is formed on the solder exclusion surface. Since the electrodes are formed only on the solder forming surface of the electrodes, it is sufficient to provide lands as conductors on the circuit board only in the region of the circuit board corresponding to the solder on the solder forming surface. It is not necessary to form the land protruding from the chip component, and the land of the circuit board can be formed in a size that does not protrude from the chip component.
【００２８】このように、チップ部品の底面電極に半田
形成面を形成し該半田形成面以外の外部電極表面を半田
排除面に形成し、回路基板のランドをチップ部品からは
み出さない大きさに形成することによって、底面電極の
半田形成面と回路基板のランドとの間に半田を挟み込む
形態でチップ部品を回路基板に半田接続実装することが
可能となる。すなわち、半田形成面と回路基板のランド
との間に挟み込まれた半田の溶融時に、溶融した半田は
半田の濡れ性に起因して半田形成面とランドだけに付着
し、半田排除面やランド周辺の回路基板表面には漏洩付
着しないので、溶融半田が半田形成面とランドの間か
ら、例えば、チップ部品の側面に形成された外部電極の
側面電極に回り込んで付着することはなく、すなわち、
チップ部品と回路基板間のみに半田を形成することがで
き、従来のように半田がチップ部品から外に大きくはみ
出してフィレット形成される形態でチップ部品を回路基
板に実装する場合に比べて、チップ部品から半田や回路
基板のランドがはみ出さない分、本発明のチップ部品を
他の回路素子との間隔を狭めて実装することができ、回
路基板の高密度実装を達成させることが可能となる。As described above, the solder forming surface is formed on the bottom electrode of the chip component, the external electrode surface other than the solder forming surface is formed on the solder exclusion surface, and the size of the land of the circuit board does not protrude from the chip component. This allows the chip component to be solder-mounted on the circuit board in a form in which the solder is sandwiched between the solder forming surface of the bottom electrode and the land of the circuit board. That is, when the solder sandwiched between the solder forming surface and the land of the circuit board is melted, the melted solder adheres only to the solder forming surface and the land due to the wettability of the solder, and the solder removing surface and the periphery of the land are melted. Since the molten solder does not adhere to the surface of the circuit board, the molten solder does not wrap around and attach to the side electrodes of the external electrodes formed on the side surfaces of the chip components, for example, between the solder forming surface and the lands.
Solder can be formed only between the chip component and the circuit board. Since the solder and the land of the circuit board do not protrude from the component, the chip component of the present invention can be mounted with a reduced distance from other circuit elements, and high-density mounting of the circuit board can be achieved. .
【００２９】さらに、本発明のチップ部品は前述したよ
うに、チップ部品の底面電極に半田形成面を形成し、こ
の半田形成面以外の電極表面を半田排除面としたので、
チップ部品を搭載接続する回路基板のランドをチップ部
品よりもはみ出して形成した場合においても、半田形成
面に付着された半田は半田接続に際し、半田形成面以外
の半田排除面となっている電極表面に付着することがな
く、溶融半田がフィレットとなってチップ部品の側面に
付着するのを防止できる。Furthermore, in the chip component of the present invention, as described above, a solder forming surface is formed on the bottom electrode of the chip component, and the electrode surface other than the solder forming surface is used as a solder exclusion surface.
Even when the lands of the circuit board on which the chip components are mounted and connected protrude from the chip components, the solder attached to the solder formation surface is the solder exclusion surface other than the solder formation surface during solder connection. Therefore, it is possible to prevent the molten solder from becoming a fillet and adhering to the side surface of the chip component.
【００３０】特に、半田形成面の周りに半田排除面を設
けたり、底面電極の外端縁部を半田排除面としこの半田
排除面よりも内側寄りに半田形成面を設けたり、底面電
極の外端縁部を全周に亙って半田になじまない半田排除
面とし半田排除面に囲まれた局部領域に半田形成面を設
ける構成とすることにより、半田接続時の溶融半田は半
田排除面によって流れがせき止められることとなるの
で、半田排除面に付着しないので半田の付着を底面電極
の領域に限定することができ、チップ部品の高密度実装
が可能となる。In particular, a solder exclusion surface is provided around the solder formation surface, a solder exclusion surface is provided at the outer edge of the bottom electrode, and a solder formation surface is provided closer to the inside than the solder exclusion surface. By making the edge part a solder removal surface that does not fit into the solder over the entire circumference and providing a solder forming surface in a local area surrounded by the solder removal surface, the molten solder at the time of solder connection is removed by the solder removal surface. Since the flow is blocked, it does not adhere to the solder exclusion surface, so that the adhesion of the solder can be limited to the area of the bottom electrode, and high-density mounting of chip components becomes possible.
【００３１】同様に、底面電極の表面を半田になじまな
い金属又は素材で被覆して半田排除面とし、底面電極の
局部領域に半田形成面を形成した構成のものや、底面電
極を半田になじまない金属で形成して半田排除面とし、
この半田排除面の上に半田形成面を形成した構成のもの
も、底面電極の半田形成面以外の部分に半田が付着する
ことがないので、半田形成面に付着する半田を一定量に
定めることができ、信頼性の高い半田接続が可能とな
る。Similarly, the surface of the bottom electrode is coated with a metal or material that does not fit into the solder to form a solder exclusion surface, and a solder forming surface is formed in a local area of the bottom electrode, or the bottom electrode is adapted to the solder. Made of non-metallic material and used as a solder removal surface,
Even in the case where the solder formation surface is formed on this solder removal surface, the solder does not adhere to the bottom electrode other than the solder formation surface. And a highly reliable solder connection is possible.
【００３２】さらに、半田形成面に半田を形成した構成
のものは、この半田を利用してチップ部品を回路基板に
半田接続することができる。この場合は、チップ部品自
身が半田を持っているので、チップ部品を回路基板のラ
ンドに載せて加熱するだけで接続作業が完了することと
なり、チップ部品の半田接続実装作業を容易化し、その
作業効率を高めることができる。しかも、チップ部品が
持つ半田の量は、半田形成面が保持できる接続に必要な
だけの少量であり、フィレットができる余分量の半田を
持つことがないので、半田接続時に溶融半田によるフィ
レット形成の懸念がなくなる。Further, in the case of a configuration in which solder is formed on a solder forming surface, a chip component can be connected to a circuit board by soldering using this solder. In this case, since the chip component itself has solder, the connection work can be completed simply by placing the chip component on the land of the circuit board and heating it. Efficiency can be increased. In addition, the amount of solder that the chip component has is small enough for the connection that the solder forming surface can hold, and there is no extra solder that can be filleted. No more concerns.
【図１】本発明に係るチップ部品の要部構成例の説明図
である。FIG. 1 is an explanatory diagram of a configuration example of a main part of a chip component according to the present invention.
【図２】同チップ部品を回路基板に搭載し半田接続した
実装状態の説明図である。FIG. 2 is an explanatory diagram of a mounting state in which the chip component is mounted on a circuit board and connected by soldering.
【図３】同チップ部品の第１の製造方法の工程におい
て、底面電極に半田形成面を形成するためのマスクを施
した状態の説明図である。FIG. 3 is an explanatory view showing a state in which a mask for forming a solder forming surface is applied to a bottom electrode in a step of a first manufacturing method of the chip component.
【図４】図３の工程後、底面電極の表面に半田レジスト
を形成する工程と、マスクを除去して半田形成面を形成
する工程の説明図である。FIG. 4 is an explanatory view of a step of forming a solder resist on the surface of the bottom electrode after the step of FIG. 3 and a step of forming a solder formation surface by removing a mask.
【図５】図４の状態からチップ部品の半田形成面に半田
膜を形成した状態の説明図である。FIG. 5 is an explanatory view of a state in which a solder film is formed on a solder forming surface of the chip component from the state of FIG. 4;
【図６】チップ部品の第２の製造方法の説明図である。FIG. 6 is an explanatory diagram of a second method for manufacturing a chip component.
【図７】従来のチップ部品の斜視図である。FIG. 7 is a perspective view of a conventional chip component.
【図８】同チップ部品と回路基板とを半田接続した状態
の説明図である。FIG. 8 is an explanatory diagram of a state where the chip component and a circuit board are connected by soldering.
【図９】チップ部品の底面電極と基板側のランドとの関
係を示す従来例の説明図である。FIG. 9 is an explanatory view of a conventional example showing a relationship between a bottom electrode of a chip component and a land on the substrate side.
１ チップ部品 ２ 外部電極 ５ 底面電極 ６ 半田フィレット ７ 回路基板 １１ 半田形成面 １２ 半田レジスト １３ ワックス １４ クロム（半田排除面） DESCRIPTION OF SYMBOLS 1 Chip component 2 External electrode 5 Bottom electrode 6 Solder fillet 7 Circuit board 11 Solder forming surface 12 Solder resist 13 Wax 14 Chrome (Solder excluding surface)
Claims (7)
外部電極を形成し、該チップ部品の両端側底面に外部電
極の一部となる底面電極を配置し、これら底面電極領域
のみにそれぞれ半田形成面を設け、この半田形成面以外
の外部電極表面を半田になじまない半田排除面としたこ
とを特徴とするチップ部品。At least one pair of external electrodes is formed on both ends of a chip component, bottom electrodes which are part of the external electrodes are arranged on the bottom surfaces of both ends of the chip component, and solder is formed only in these bottom electrode regions. A chip component comprising: a surface provided with a surface, and an external electrode surface other than the surface on which the solder is formed is a solder exclusion surface that does not adapt to solder.
面電極を形成し、この一対の底面電極領域にそれぞれ半
田形成面を設け、この半田形成面の周りを半田になじま
ない半田排除面で構成したことを特徴とするチップ部
品。At least one pair of bottom electrodes is formed on the bottom surface of the chip component, a solder forming surface is provided in each of the pair of bottom electrode regions, and the periphery of the solder forming surface is constituted by a solder excluding surface that does not adapt to solder. A chip component characterized in that:
半田排除面とし、半田形成面は外端縁部の半田排除面よ
りも内側寄りに設けられていることを特徴とする請求項
１又は請求項２に記載のチップ部品。3. The method according to claim 1, wherein an outer edge of the bottom electrode is a solder exclusion surface that does not adapt to solder, and a solder forming surface is provided closer to the inside than the solder exclusion surface of the outer edge. The chip component according to claim 1 or 2.
になじまない半田排除面とし、半田排除面に囲まれた局
部領域に半田形成面が設けられていることを特徴とする
請求項１又は請求項２に記載のチップ部品。4. An outer edge portion of the bottom electrode is a solder exclusion surface which does not adapt to solder over the entire circumference, and a solder forming surface is provided in a local area surrounded by the solder exclusion surface. The chip component according to claim 1 or 2, wherein
又は素材で被覆して半田排除面とし、底面電極の局部領
域に半田になじむ金属で半田形成面を形成したことを特
徴とする請求項１又は請求項２に記載のチップ部品。5. The method according to claim 1, wherein a surface of the bottom electrode is coated with a metal or a material which does not fit into the solder to form a solder exclusion surface, and a local area of the bottom electrode is formed with a solder forming surface of a metal compatible with the solder. The chip component according to claim 1 or 2.
して半田排除面とし、この半田排除面の上に半田形成面
を形成したことを特徴とする請求項１又は請求項２に記
載のチップ部品。6. The method according to claim 1, wherein the bottom electrode is formed of a metal that does not blend with solder to form a solder exclusion surface, and a solder formation surface is formed on the solder exclusion surface. Chip parts.
特徴とする請求項１乃至請求項６の何れか１つに記載の
チップ部品。7. The chip component according to claim 1, wherein a solder is formed on the surface on which the solder is to be formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10314099A JPH11251177A (en) | 1998-10-16 | 1998-10-16 | Chip component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10314099A JPH11251177A (en) | 1998-10-16 | 1998-10-16 | Chip component |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3201353A Division JP2897088B2 (en) | 1991-07-16 | 1991-07-16 | Manufacturing method and mounting structure of chip parts |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11251177A true JPH11251177A (en) | 1999-09-17 |
Family
ID=18049236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10314099A Pending JPH11251177A (en) | 1998-10-16 | 1998-10-16 | Chip component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11251177A (en) |
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| US10418191B2 (en) * | 2015-03-20 | 2019-09-17 | Murata Manufacturing Co., Ltd. | Electronic component with outer electrode including sintered layers, glass layer, and metal layers and method for producing the same |
| JP2015188111A (en) * | 2015-06-25 | 2015-10-29 | Tdk株式会社 | Electronic part |
| JP2015228506A (en) * | 2015-07-22 | 2015-12-17 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
| JP2016178337A (en) * | 2016-06-10 | 2016-10-06 | Tdk株式会社 | Electronic component |
| JP2018056190A (en) * | 2016-09-26 | 2018-04-05 | 株式会社村田製作所 | Manufacturing method of laminated electronic component |
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