JP2000164450A - Multilayer capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer capacitor which is constituted in such a way that the designed capacitance of its laminate itself does not fluctuate much, by making parasitic capacitances induced between internal electrode layers and the wiring of a mounting substrate as small as possible. SOLUTION: The multilayer capacitor 1 is constituted by arranging internal electrode layers 2 among the dielectric layers of a laminate 12 formed by laminating a plurality of rectangular dielectric layers upon another and, at the same time, forming external electrodes 5 on both end faces of the laminate 12. A capacitance interrupting electrode 3 composed at least of three or more insular conductive films arranged in parallel is arranged from one external electrode 5 to the other external electrode 5 between the dielectric layers on the outside of the outermost internal electrode layer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multilayer capacitor. In particular, it belongs to a surface mount type multilayer capacitor capable of accurately determining the effective capacitance at the time of mounting.

[0002]

2. Description of the Related Art As shown in FIG. 9, a multilayer capacitor is formed by alternately stacking internal electrode layers 2 having different potentials with a rectangular dielectric layer made of ceramic or the like interposed therebetween.
Is connected to one of the pair of external electrodes 5 and 5 formed on the end surface of the first electrode. Each external electrode 5 is mounted on the mounting board 6 by being bonded to the electrode pad 8 of the mounting board 6 by a bonding member 7 such as solder.

Conventionally, in such a mounting method of a multilayer capacitor, an internal electrode layer of one potential and an electrode pad on a mounting board connected to the internal electrode layer of the other potential or a wiring conductor connected thereto are connected. A parasitic capacitance (hereinafter, referred to as a parasitic capacitance) occurs.

[0004] The parasitic capacitance causes parasitic noise, and is significantly affected particularly in a high frequency region of 1 GHz or more. Therefore, in the technique described in Japanese Patent Application Laid-Open No. 9-129498, a pair of electrodes 2a and 2b each having a short length connected to an external electrode are provided between dielectric layers outside the internal electrode layer 2 as shown in FIG. Had been formed.

[0005]

Problems to be Solved by the Invention
No. 498, the parasitic capacitance can be reduced to some extent, but the parasitic capacitance still exists between the wiring 18 existing between the electrode pads 8 on the mounting substrate 6 and the internal electrode layer 2. .

Therefore, an object of the present invention is to minimize the parasitic capacitance generated between the internal electrode layer and the wiring of the mounting substrate and to have a capacitance substantially equal to the designed capacitance of the laminate itself. An object of the present invention is to provide a multilayer capacitor.

[0007]

In order to achieve the object, a multilayer capacitor according to the present invention has a structure in which an internal electrode layer is arranged between dielectric layers of a laminate formed by laminating a plurality of rectangular dielectric layers. A multilayer capacitor formed by forming external electrodes connected to the internal electrode layers on a pair of end surfaces of the multilayer body, between the dielectric layers located outside the outermost internal electrode layer, from one external electrode to the other. A capacitance cutoff electrode having at least three or more island-shaped conductor films is arranged before reaching the external electrode.

Accordingly, the capacitance blocking electrode blocks a parasitic capacitance generated between the internal electrode layer and the electrode pad or the wiring conductor on the mounting board.

In addition, since the capacitance cut-off electrode is formed by arranging a plurality of island-shaped conductor films in parallel so as to be divided at least at two or more locations between the external electrodes, a line capacitance component is formed at each of the divided locations. Then, they are equivalent in circuit to those connected in series. For this reason, even if a parasitic capacitance occurs between the capacitance cutoff electrode and the wiring conductor of the mounting board, the change in the capacitance formed by the internal electrode layers in the laminate is small. This change in capacitance becomes smaller as the number of island-shaped conductor films of the capacitance cutoff electrode increases.

It is preferable that the capacitance cut-off electrodes are formed on both outermost layers of the internal electrode layers, that is, not only on the lower part but also on the upper part during mounting. By doing so, it can be implemented without discrimination of front and back.

The distance from the external electrode connection position of the divided capacitance blocking electrode to the first dividing point, that is, the length m of the island-shaped conductive film connected to the external electrode extends parallel to the capacitance blocking electrode of the external electrodes. It is better to make it slightly longer than the length n of the part where it exists. Since the external electrodes have the same polarity as the electrode pads on the mounting substrate, no parasitic capacitance is generated at least up to the first breaking point, and the parasitic capacitance generated between the capacitance cut-off electrode and the electrode pad is reduced accordingly. Because you can do it.

It is desirable that the capacitance cutoff electrode of the multilayer capacitor of the present invention is constituted by a plurality of divided electrodes via a dielectric layer. However, with respect to the dividing part, the dividing part of the first dividing electrode and the dividing part of the second dividing electrode do not overlap each other. Then, except for the divided part,
And the second dividing electrode are opposed to each other. With this configuration, unlike the above configuration in which the capacitance cutoff electrode is formed of a single dividing electrode and the capacitance component is formed between the electrode lines in the same plane, the first dividing electrode and the second dividing electrode Capacitive components are formed between the layers, and these capacitive components are connected in series. Therefore, the parasitic capacitance generated between the internal electrode layer and the wiring on the mounting board is reduced to a negligible level.

[0013]

Embodiment 1 An embodiment of a multilayer capacitor according to the present invention will be described with reference to the drawings. 1 is a cross-sectional view showing the multilayer capacitor of the first embodiment, FIG. 2 is a perspective view of the same, FIG. 3 is a plan view showing an internal electrode layer and a capacity cutoff electrode side by side, and FIG. 4 shows a state where the multilayer capacitor is mounted. FIG. 5 is a sectional view, and FIG. 5 is an equivalent circuit diagram at the time of mounting. The same parts as those in the related art are denoted by the same reference numerals.

As shown in FIG. 2, the multilayer capacitor 1 is provided with a pair of external electrodes 5 on opposite end surfaces of a rectangular parallelepiped laminate 12. Further, as shown in FIG. 4, it is joined to the electrode pad 8 of the mounting board 6 via a joining member 7 such as solder.

The laminate 12 is formed by laminating a rectangular dielectric layer made of a dielectric ceramic material such as barium titanate or strontium titanate and the internal electrode layers 2, 2,. The internal electrode layer 2 is made of a noble metal material such as palladium Pd or a palladium-silver alloy Pd-Ag, or a base metal material such as nickel Ni. And the layers connected to the external electrodes 5 (on the right side) are alternately arranged to form a capacitance component between the layers.

The external electrode 5 has a layer structure of a base conductor film 13, an intermediate film 9, and a surface film 10 in this order from the end face side of the laminated body 12. The base conductor film 13 secures the adhesion with the dielectric layer, the surface film 10 secures the adhesion with the bonding member 7, the intermediate film 9
Each plays a role of preventing solder erosion of the underlying conductor film 13. The underlying conductor film 13 is made of, for example, silver, copper, a silver-palladium alloy, or a conductive resin containing these. The intermediate film 9 is generally made of nickel, but may contain cobalt. The surface film 10 is made of, for example, solder or tin.

In the lower portion of the lowermost layer of the internal electrode layer 2, the capacitance cutoff is divided at a number of points on the way from the connection position with one external electrode 5 to the connection position with the other external electrode 5. Electrodes 3 are laid. A mark 14 is provided on the upper surface of the laminate 12 so that the capacitance cutoff electrode 3 does not become the uppermost layer during mounting. The capacity cut-off electrode 3 is composed of a plurality of island-shaped conductor films 31, 31... So that two or more divided regions x are formed from one external electrode 5 to the other external electrode 5. I have.
Further, the distance m from the connection position of the capacitance cutoff electrode 3 to the external electrode 5 to the first breaking point is longer than the length n of the portion of the external electrode 5 extending in parallel with the capacitance cutoff electrode 3. It is provided so that it becomes. Note that the width of the island-shaped conductor film 31 is desirably provided to be equal to or wider than the width of the internal electrode layer 2.

This multilayer capacitor 1 is manufactured as follows.

First, a conductive film serving as the internal electrode layer 2 is formed by printing with a conductive paste on the surface of a large ceramic green sheet of about 10 cm square serving as a dielectric layer, for example. The conductor film to be the capacitance cutoff electrode 3 is formed in the same manner. The mark 14 is printed on the surface of the ceramic green sheet that is the uppermost surface of the laminate 12.

Then, every other printed green sheet on which the internal electrode layer 2 is printed is turned by 180 degrees to connect the internal electrode layer 2 to one external electrode 5 and the internal electrode layer connected to the other external electrode 5. 2 are alternately laminated, and thermocompression-bonded at a pressure of 300 kg / cm ² and a temperature of 90 ° C. However,
The green sheet on which the conductive film serving as the capacitance blocking electrode 3 is printed is at the bottom, and the green sheet on which the mark 14 is printed is at the top. 0.5-2mm thick by being pressed together
A large number of large green sheets, for example,
Cut to a size of about 3.2 mm. As for the cutting method, when the laminate is thin, it is preferable to cut it off, and when it is thick, dicing is preferable. Thus, an unfired laminate is obtained.

After the unsintered laminate is degreased in a degreasing furnace at a temperature of 250 ° C. to 400 ° C., a predetermined atmosphere and temperature suitable for the components of the green sheet, the internal electrode layer, and the capacity cut-off electrode,
For example, if the internal electrode layer is a silver-palladium alloy,
By firing at 250 ° C. to 1300 ° C., the dielectric layer, the internal electrode layer, and the capacitance cutoff electrode are sintered and integrated to obtain the laminate 12.

Next, external electrodes 5 are formed on a pair of opposed end faces of the laminate 12. Specifically, the stacked body 12 is barrel-polished in a container containing polishing powder and water, so that the end of the internal electrode layer 2 is exposed at the end face. Then, a conductive paste to be the base conductor film 13 is applied to the end face, dried and dried at 700 ° C. to 8 ° C.
Bake at 60 ° C. When the conductive paste is made of a conductive resin, the baking step is omitted. Then, the intermediate film 9
Metal, for example, nickel, and then the surface film 1
A metal that becomes zero, for example, solder is plated.

The obtained multilayer capacitor 1 has a mark 14
Is bonded to the electrode pad 8 of the mounting board 6 by the bonding member 7 so that the upper side faces upward, thereby mounting as shown in FIG.

In the mounted state, since the capacitance cutoff electrode 3 extends from one external electrode 5 to the other external electrode 5, the parasitic capacitance between the electrode pad 8 and the surface wiring (not shown) of the mounting substrate 6 is reduced. Occurrence is prevented. In addition, since the potential from the electrode pad 8 to the first breaking point of the capacitance blocking electrode 3 is the same,
No parasitic capacitance occurs during this time. Further, as described above, since the distance m to the first break point is longer than the length n of the wraparound portion of the external electrode 5, the external electrode 5 and the internal electrode layer 2
There is no parasitic capacitance between the two. Eventually, a circuit configuration as shown in FIG. 5 is obtained, and a parasitic capacitance 11 is generated between the capacitance cutoff electrode 3 and the electrode pad 8 or the surface wiring of the mounting substrate 6. The capacitance value is reduced by the series coupling of the line capacitances 15 formed in the above.

Therefore, an effective capacity almost as designed can be obtained.

Embodiment 2 A second embodiment of the present invention will be described with reference to the sectional view shown in FIG. In the second embodiment, unlike the first embodiment, the mark 14 is not provided on the upper surface of the stacked body 12. Instead, the upper-side capacitance cutoff electrode 16 is formed on the uppermost layer side in the same pattern as the lower-side capacitance cutoff electrode 3. Otherwise, it is manufactured under the same conditions as the first embodiment. Therefore, the same operation and effects as those of the multilayer capacitor of the first embodiment can be obtained even if the multilayer capacitor is mounted without discrimination between front and back. In addition, the number of steps for printing the mark 14 can be omitted.

Embodiment 3 A third embodiment of the present invention will be described with reference to a sectional view shown in FIG. In the third embodiment, the capacitance blocking electrode 3 is formed not only in one layer but also in a plurality of layers, for example, two layers. That is, the lower capacity cut-off electrode is composed of a first split electrode (same as the same code as the capacity cut-off electrode) 3 and a second split electrode 4. Similarly, the upper capacity cut-off electrode is composed of a first split electrode (assigned the same reference numeral as the capacity cut-off electrode) 16 and a second split electrode 17. Here, as shown in FIG. 8, the lower first dividing electrode 3 includes a plurality of island-shaped conductor films 3.
Are arranged side by side, and a divided region X is formed between adjacent island-shaped conductor films 31, 31,.... In addition, the second dividing electrode 4 includes a plurality of island-shaped conductor films 4.
Are formed side by side, and a divided region Y is formed between adjacent island-shaped conductor films 41, 41. The first and second capacitance cutoff electrodes 3 and 4 are stacked in the thickness direction such that the divided regions X and Y do not overlap with each other. Therefore, the two island-shaped conductor films 41 and 41 face one island-shaped conductor film 31 via the dielectric layer, and the two interlayer capacitance components are connected in series. . Note that the same applies to the capacitance cutoff electrodes 16 and 17 on the upper side. For this reason, the capacitance component between the divided electrodes that reduces the parasitic capacitance in the first embodiment is:
Here, the inter-layer capacitance formed between the first dividing electrode 3 and the second dividing electrode 4 is connected in series. Therefore, the parasitic capacitance is further reduced. Otherwise, it is manufactured under the same conditions as the second embodiment.

[0028]

As described above, since the multilayer capacitor of the present invention hardly generates a parasitic capacitance at the time of mounting, the effective capacitance can be accurately determined. Also, almost no noise is generated.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a multilayer capacitor according to a first embodiment of the present invention.

FIG. 2 is a perspective view showing the multilayer capacitor according to the first embodiment of the present invention.

FIGS. 3A and 3B are plan views showing the internal electrode layers of the multilayer capacitor according to the first embodiment of the present invention arranged side by side; FIGS.
(B) shows the internal electrode layer, and (c) shows the capacity cutoff electrode.

FIG. 4 is a cross-sectional view showing a state in which the multilayer capacitor according to the first embodiment of the present invention is mounted on a mounting board.

FIG. 5 is an equivalent circuit diagram of a mounted state of the multilayer capacitor according to the first embodiment of the present invention.

FIG. 6 is a sectional view showing a multilayer capacitor according to a second embodiment of the present invention.

FIG. 7 is a sectional view showing a multilayer capacitor according to a third embodiment of the present invention.

FIGS. 8A and 8B are plan views showing the internal electrode layers of the multilayer capacitor according to the third embodiment of the present invention arranged side by side, wherein FIGS.
(B) shows the internal electrode layer, and (c) and (d) show the capacity cutoff electrodes.

FIG. 9 is a sectional view showing a conventional multilayer capacitor.

FIG. 10 is a sectional view showing another conventional multilayer capacitor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multilayer capacitor 2 Internal electrode layer 3 Capacitance cutoff electrode 4 Capacitance cutoff electrode 5 External electrode 6 Mounting substrate 7 Joining member 8 Electrode pad 9 Intermediate film 10 Surface film 11 Parasitic capacitance 12 Laminated body 13 Underlayer conductor film 14 Mark 15 Capacitance component 16 Capacity Cutoff electrode 17 Capacitance cutoff electrode

Claims (2)

[Claims] 1. An internal electrode layer is arranged between dielectric layers of a laminate formed by laminating a plurality of rectangular dielectric layers, and an external electrode connected to the internal electrode layer is provided on a pair of end surfaces of the laminate. In the multilayer capacitor formed, at least three or more island-shaped conductor films are arranged in parallel between one external electrode and another external electrode between dielectric layers located outside the outermost internal electrode layer. A multilayer capacitor in which a provided capacity cutoff electrode is arranged. 2. The method according to claim 1, wherein the capacitance cutoff electrode includes a first divided electrode having at least three or more island-shaped conductor films arranged in parallel between one external electrode and the other external electrode, and a second divided electrode. A first dividing electrode and a second dividing electrode are opposed to each other with a dielectric layer interposed therebetween, and each of the first dividing electrode and the second dividing electrode The multilayer capacitor according to claim 1, wherein the divided portions between the island-shaped conductor films are different.