JP6527612B2 - Multilayer ceramic capacitor - Google Patents

Multilayer ceramic capacitor Download PDF

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JP6527612B2
JP6527612B2 JP2018024908A JP2018024908A JP6527612B2 JP 6527612 B2 JP6527612 B2 JP 6527612B2 JP 2018024908 A JP2018024908 A JP 2018024908A JP 2018024908 A JP2018024908 A JP 2018024908A JP 6527612 B2 JP6527612 B2 JP 6527612B2
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capacitor
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佐々木 真一
真一 佐々木
研一 平岡
研一 平岡
増田 淳
淳 増田
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Taiyo Yuden Co Ltd
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Description

本発明は、積層セラミックコンデンサに関する。   The present invention relates to a multilayer ceramic capacitor.

積層セラミックコンデンサは、一般に、長さ、幅及び高さで規定された略直方体状のコンデンサ本体と、コンデンサ本体の長さ方向両端部に設けられた外部電極とを備えている。コンデンサ本体は、セラミックス製の第1保護部と、複数の内部電極層がセラミック層を介して積層された容量部と、セラミックス製の第2保護部と、が高さ方向に層状に並ぶように有している。また、容量部に含まれる複数の内部電極層の一部の端縁は外部電極の一方に電気的に接続され、且つ、残部の端縁は前記外部電極の他方に電気的に接続されている(後記特許文献1の図1を参照)。   A laminated ceramic capacitor generally comprises a substantially rectangular parallelepiped capacitor body defined by a length, a width and a height, and external electrodes provided at both ends in the longitudinal direction of the capacitor body. In the capacitor body, the first protective portion made of ceramic, the capacitance portion in which the plurality of internal electrode layers are stacked via the ceramic layer, and the second protective portion made of ceramic are arranged in layers in the height direction. Have. In addition, an edge of a portion of the plurality of inner electrode layers included in the capacitive portion is electrically connected to one of the outer electrodes, and an edge of the remaining portion is electrically connected to the other of the outer electrodes. (See FIG. 1 of Patent Document 1 below).

この積層セラミックコンデンサの回路基板への実装は、積層セラミックコンデンサの各外部電極の被接合面を、回路基板に設けられたパッドの表面にハンダを用いて接合することによって為されている。各外部電極の被接合面が接合されるパッドの表面形状は、一般に、各外部電極の被接合面形状よりも大きな矩形であるため、実装後の各外部電極の端面には溶融ハンダの濡れ上がりに基づくハンダフィレットが形成される(後記特許文献1の図1及び図2を参照)。   The mounting of the multilayer ceramic capacitor on a circuit board is achieved by bonding the surfaces to be bonded of the external electrodes of the multilayer ceramic capacitor to the surface of a pad provided on the circuit board using solder. Since the surface shape of the pad to which the bonded surface of each external electrode is bonded is generally a rectangle larger than the bonded surface shape of each external electrode, the end face of each external electrode after mounting is wetted by molten solder Solder fillets are formed (see FIGS. 1 and 2 of Patent Document 1 below).

この実装構造において回路基板の各パッドを通じて両外部電極に電圧、特に交流電圧が印加されると、コンデンサ本体に電歪現象に基づく伸縮(主として容量部が長さ方向に縮むような収縮及びその復元)が生じ、この伸縮に伴う応力が外部電極、ハンダ及びパッドを通じて回路基板に伝わって振動(主として両パッドの間部分が凹むような反り及びその復元)を招来し、この振動によって可聴域の音(所謂、音鳴き)を発生することがある。   In this mounting structure, when a voltage, in particular an AC voltage, is applied to both external electrodes through each pad of the circuit board, expansion and contraction based on the electrostriction phenomenon (shrinkage such as contraction of the capacitive portion mainly in the length direction) Stress caused by the expansion and contraction is transmitted to the circuit board through the external electrode, the solder and the pad to cause vibration (warpage and restoration thereof mainly resulting in a depression between the two pads), and this vibration causes audible noise (So-called sounding) may occur.

ところで、後記特許文献1には、前記音鳴きを抑制するために、「パッドの表面を基準としたハンダフィレットの高さ」を「パッドの表面とコンデンサ本体との間隔」+「コンデンサ本体の下側の保護部の厚さ」よりも低くした実装構造が記載されている(図2を参照)。   Incidentally, in Patent Document 1 described later, in order to suppress the noise, the “height of the solder fillet based on the surface of the pad” is referred to as “the distance between the surface of the pad and the capacitor body” + “under the capacitor body A mounting structure is described which is lower than the thickness of the side protection (see FIG. 2).

しかしながら、ハンダフィレットは、各外部電極の端面に対する溶融ハンダの濡れ上がりに基づいて形成されるものであるため、各外部電極の端面のハンダ濡れ性が良好であることも相まって、特別な方法を用いない限り、前記「パッドの表面を基準としたハンダフィレットの高さ」を制御することは極めて難しい。   However, since the solder fillet is formed based on the wetting of the molten solder to the end face of each external electrode, a special method is used because the solder wettability of the end face of each external electrode is good. Unless otherwise stated, it is extremely difficult to control the "height of the solder fillet with respect to the surface of the pad".

具体例を挙げて説明すれば、各外部電極の端面の高さが500μmである積層セラミックコンデンサにあっては、ハンダ量が同じであっても、実際には、各外部電極の端面の下端を基準とした場合のハンダフィレットの高さが200μmを優に超えるものや200μmに満たないものが非実装不良として発生する。   To give a specific example, in the case of a laminated ceramic capacitor in which the height of the end face of each external electrode is 500 μm, the lower end of the end face of each external electrode is actually selected, even if the amount of solder is the same. When the height of the solder fillet when used as a reference is well over 200 μm or less than 200 μm, a non-mounting defect occurs.

即ち、後記特許文献1に記載されている実装構造は「パッドの表面を基準としたハンダフィレットの高さ」を制御する特別な方法を採用したものではないため、実際上、「パッドの表面を基準としたハンダフィレットの高さ」を「パッドの表面とコンデンサ本体との間隔」+「コンデンサ本体の下側の保護部の厚さ」よりも低くすることは極めて難しく、故に音鳴き抑制に対する実用性は極めて低い。   That is, since the mounting structure described in Patent Document 1 below does not adopt a special method for controlling "the height of the solder fillet with respect to the surface of the pad", in fact, "the surface of the pad It is extremely difficult to make the standard solder fillet height lower than the distance between the surface of the pad and the capacitor body + the thickness of the protective portion on the lower side of the capacitor body. Sex is very low.

特開2013−046069号公報JP, 2013-046069, A

本発明の目的は、実装状態における音鳴き抑制に対し実用性の高い積層セラミックコンデンサを提供することにある。   An object of the present invention is to provide a laminated ceramic capacitor having high practicability for suppressing noise in a mounted state.

前記目的を達成するため、本発明は、長さ、幅及び高さで規定された略直方体状のコンデンサ本体と、前記コンデンサ本体の長さ方向両端部に設けられた外部電極とを備えた積層セラミックコンデンサであって、前記コンデンサ本体は、(1)セラミックス製の第1保護部と、(2)複数の内部電極層がセラミック層を介して積層された容量部と、(3)セラミックス製の電歪緩和部と、(4)複数の内部電極層がセラミック層を介して積層された特性調整部と、(5)セラミックス製の第2保護部と、が高さ方向に層状に並ぶように有しており、前記容量部に含まれる複数の内部電極層の一部の端縁は前記外部電極の一方に電気的に接続され、且つ、残部の端縁は前記外部電極の他方に電気的に接続されており、前記特性調整部に含まれる複数の内部電極層の一部の端縁は前記外部電極の一方に電気的に接続され、且つ、残部の端縁は前記外部電極の他方に電気的に接続されており、前記容量部の厚さをT2とし、前記電歪緩和部の厚さをT3とし、前記特性調整部の厚さをT4としたとき、該T2、T3及びT4はT2>T3>T4の条件を満足している。   In order to achieve the above object, the present invention is a laminate comprising a substantially rectangular parallelepiped capacitor body defined by a length, a width and a height, and external electrodes provided at both ends in the longitudinal direction of the capacitor body. A ceramic capacitor, wherein the capacitor body comprises (1) a first protective portion made of a ceramic, (2) a capacitive portion in which a plurality of internal electrode layers are stacked via a ceramic layer, and (3) made of a ceramic The electrostriction alleviating part, (4) the characteristic adjusting part in which the plurality of internal electrode layers are stacked via the ceramic layer, and (5) the second protective part made of ceramic are arranged in layers in the height direction. And an edge of a portion of the plurality of inner electrode layers included in the capacitive portion is electrically connected to one of the outer electrodes, and an edge of the remaining portion is electrically connected to the other of the outer electrodes. Connected to and included in the characteristic adjustment unit The edge of a portion of the number of internal electrode layers is electrically connected to one of the outer electrodes, and the edge of the remaining portion is electrically connected to the other of the outer electrodes, and the thickness of the capacitor portion Assuming that the length is T2, the thickness of the electrostrictive relaxation portion is T3, and the thickness of the characteristic adjustment portion is T4, the T2, T3 and T4 satisfy the condition of T2> T3> T4.

本発明によれば、実装状態における音鳴き抑制に対し実用性の高い積層セラミックコンデンサを提供することができる。   According to the present invention, it is possible to provide a laminated ceramic capacitor having high practicability with respect to the suppression of noise in the mounted state.

図1は本発明を適用した積層セラミックコンデンサ(第1実施形態)の上面図である。FIG. 1 is a top view of a multilayer ceramic capacitor (first embodiment) to which the present invention is applied. 図2は図1のS−S線に沿う縦断面図である。FIG. 2 is a longitudinal sectional view taken along the line S-S in FIG. 図3は図1及び図2に示した積層セラミックコンデンサを回路基板に実装した構造を示す部分縦断面図である。FIG. 3 is a partial longitudinal sectional view showing a structure in which the multilayer ceramic capacitor shown in FIGS. 1 and 2 is mounted on a circuit board. 図4は効果確認用サンプルの仕様と特性を示す図である。FIG. 4 is a diagram showing the specifications and characteristics of the effect confirmation sample. 図5は本発明を適用した積層セラミックコンデンサ(第2実施形態)の図2対応の縦断面図である。FIG. 5 is a longitudinal cross-sectional view corresponding to FIG. 2 of the laminated ceramic capacitor (second embodiment) to which the present invention is applied. 図6は本発明を適用した積層セラミックコンデンサ(第3実施形態)の図2対応の縦断面図である。FIG. 6 is a longitudinal sectional view corresponding to FIG. 2 of the laminated ceramic capacitor (third embodiment) to which the present invention is applied. 図7は本発明を適用した積層セラミックコンデンサ(第4実施形態)の図2対応の縦断面図である。FIG. 7 is a longitudinal cross-sectional view corresponding to FIG. 2 of a laminated ceramic capacitor (fourth embodiment) to which the present invention is applied. 図8は本発明を適用した積層セラミックコンデンサ(第5実施形態)の図2対応の縦断面図である。FIG. 8 is a longitudinal sectional view corresponding to FIG. 2 of the laminated ceramic capacitor (fifth embodiment) to which the present invention is applied. 図9は本発明を適用した積層セラミックコンデンサ(第6実施形態)の図2対応の縦断面図である。FIG. 9 is a longitudinal sectional view corresponding to FIG. 2 of a laminated ceramic capacitor (sixth embodiment) to which the present invention is applied. 図10は本発明を適用した積層セラミックコンデンサ(第7実施形態)の図2対応の縦断面図である。FIG. 10 is a longitudinal sectional view corresponding to FIG. 2 of the laminated ceramic capacitor (seventh embodiment) to which the present invention is applied.

《第1実施形態》
図1及び図2は本発明を適用した積層セラミックコンデンサ10-1(第1実施形態)を示す。この積層セラミックコンデンサ10-1は、長さL、幅W及び高さHで規定された略直方体状のコンデンサ本体11と、コンデンサ本体11の長さ方向両端部に設けられた外部電極12とを備えている。
First Embodiment
1 and 2 show a laminated ceramic capacitor 10-1 (first embodiment) to which the present invention is applied. The multilayer ceramic capacitor 10-1 includes a substantially rectangular parallelepiped capacitor body 11 defined by a length L, a width W, and a height H, and external electrodes 12 provided at both ends in the longitudinal direction of the capacitor body 11. Have.

コンデンサ本体11は、(1)セラミックス製の第1保護部11aと、(2)複数の内部電極層11b1がセラミック層11b2を介して積層された容量部11bと、(3)セラミックス製の電歪緩和部11cと、(4)複数の内部電極層11d1がセラミック層11d2を介して積層された特性調整部11dと、(5)セラミックス製の第2保護部11eと、が高さ方向で層状に並ぶように有している。   The capacitor body 11 includes (1) a first protective portion 11a made of ceramic, (2) a capacitance portion 11b in which a plurality of internal electrode layers 11b1 are stacked via the ceramic layer 11b2, and (3) an electrostriction made of ceramic The relaxation portion 11c, (4) the characteristic adjustment portion 11d in which the plurality of internal electrode layers 11d1 are stacked via the ceramic layer 11d2, and (5) the second protective portion 11e made of ceramic are layered in the height direction. Have to line up.

容量部11bに含まれる複数(図中は24層)の内部電極層11b1は、各々の輪郭形状が略等しい矩形であり、各々の厚さも略等しい。また、隣接する内部電極層11b1の間に存するセラミック層11b2(隣接する内部電極層11b1に挟まれた部分と挟まれていない長さ方向両側部分を含む層、図中は23層)は、各々の輪郭形状が略等しく、且つ、内部電極層11b1の輪郭形状よりも大きな矩形であり、各々の厚さも略等しい。容量部11bに含まれる24層の内部電極層11b1は長さ方向に交互にずれていて、図2の上から奇数番目に当たる12層の端縁は外部電極12の一方(図2の左側)に電気的に接続され、且つ、図2の上から偶数番目に当たる12層の端縁は外部電極12の他方(図2の右側)に電気的に接続されている。   The plurality of (24 layers in the drawing) internal electrode layers 11b1 included in the capacitive portion 11b have rectangular shapes whose outlines are substantially equal, and their thicknesses are also substantially equal. Further, ceramic layers 11b2 (layers including both side portions in the length direction not sandwiched by portions sandwiched between adjacent internal electrode layers 11b1), which are between adjacent internal electrode layers 11b1, and 23 layers in the figure are respectively The outline shape of is substantially equal and is a rectangle larger than the outline shape of the internal electrode layer 11b1, and the thickness of each is also substantially equal. The 24 layers of internal electrode layers 11b1 included in the capacitor portion 11b are alternately shifted in the length direction, and the edge of the 12 layers which is the odd-numbered from the top in FIG. 2 is one of the external electrodes 12 (left side in FIG. 2) The edges of the 12 layers which are electrically connected and which are even-numbered from the top of FIG. 2 are electrically connected to the other of the outer electrodes 12 (right side of FIG. 2).

特性調整部11dに含まれる複数(図中は2層)の内部電極層11d1は、各々の輪郭形状が略等しい矩形であり、各々の厚さも略等しい。因みに、各内部電極層11d1の輪郭形状は前記内部電極層11b1と略同じであり、対向面積も前記内部電極層11b1と略同じである。また、隣接する内部電極層11d1の間に存するセラミック層11d2(隣接する内部電極層11d1に挟まれた部分と挟まれていない長さ方向両側部分を含む層、図中は1層)は、輪郭形状が内部電極層11d1の輪郭形状よりも大きな矩形である。因みに、セラミック層11d2の輪郭形状は前記セラミック層11b2と略同じであり、厚さも前記セラミック層11b2と略同じである。特性調整部11dに含まれる2層の内部電極層11d1は長さ方向に交互にずれていて、図2の上から奇数番目に当たる1層の端縁は外部電極12の一方(図2の左側)に電気的に接続され、且つ、図2の上から偶数番目に当たる1層の端縁は外部電極12の他方(図2の右側)に電気的に接続されている。   The plurality of (two layers in the drawing) internal electrode layers 11d1 included in the characteristic adjustment unit 11d have rectangular shapes whose outlines are substantially equal, and their thicknesses are also substantially equal. Incidentally, the contour shape of each internal electrode layer 11d1 is substantially the same as the internal electrode layer 11b1, and the opposing area is also substantially the same as the internal electrode layer 11b1. Further, the ceramic layer 11d2 (a layer including both side portions in the length direction not sandwiched by the portion sandwiched by the adjacent internal electrode layers 11d1) between the adjacent internal electrode layers 11d1 has a contour The shape is a rectangle larger than the contour shape of the internal electrode layer 11d1. Incidentally, the contour shape of the ceramic layer 11d2 is substantially the same as that of the ceramic layer 11b2, and the thickness is also substantially the same as that of the ceramic layer 11b2. The two layers of internal electrode layers 11d1 included in the characteristic adjustment section 11d are alternately shifted in the length direction, and the edge of one of the layers which is odd from the top in FIG. 2 is one of the external electrodes 12 (left side in FIG. 2) The edge of one of the layers which is electrically connected to and even-numbered from the top of FIG. 2 is electrically connected to the other of the external electrodes 12 (right side of FIG. 2).

容量部11bに含まれる24層の内部電極層11b1と、特性調整部11dに含まれる2層の内部電極層11d1は、組成が略同じ導体から成る。この導体には、好ましくはニッケル、銅、パラジウム、白金、銀、金、これらの合金等を主成分した良導体を使用できる。因みに、ここでの「組成が略同じ導体」は、組成が同じ導体の他、焼結度合等の関係から組成が許容範囲内で若干異なる導体を指す。   The twenty-four-layer internal electrode layer 11b1 included in the capacitive part 11b and the two-layer internal electrode layer 11d1 included in the characteristic adjustment part 11d are made of conductors having substantially the same composition. As the conductor, preferably, a good conductor based on nickel, copper, palladium, platinum, silver, gold, an alloy thereof or the like can be used. Incidentally, the term "conductors having substantially the same composition" as used herein refers to conductors having the same composition but also conductors having slightly different compositions within the allowable range due to the relationship such as the degree of sintering.

また、容量部11bに含まれる23層のセラミック層11b2と、特性調整部11dに含まれる1層のセラミック層11d2は、第1保護部11a、電歪緩和部11c及び第2保護部11eを含め、組成が略同じで誘電率も略同じセラミックスから成る。このセラミックスには、好ましくはチタン酸バリウム、チタン酸ストロンチウム、チタン酸カルシウム、チタン酸マグネシウム、ジルコン酸カルシウム、チタン酸ジルコン酸カルシウム、ジルコン酸バリウム、酸化チタン等を主成分とした誘電体セラミックス、より好ましくはε>1000又はクラス2(高誘電率系)の誘電体セラミックスを使用できる。因みに、ここでの「組成が略同じで誘電率も略同じセラミックス」は、組成と誘電率が同じセラミックスの他、焼結度合等の関係から組成と誘電率の少なくとも一方が許容範囲内で若干異なるセラミックスを指す。   In addition, the 23 ceramic layers 11b2 included in the capacitive portion 11b and the single ceramic layer 11d2 included in the characteristic adjustment portion 11d include the first protective portion 11a, the electrostriction alleviating portion 11c and the second protective portion 11e. The composition is substantially the same, and the dielectric constant is also substantially the same. Dielectric ceramics mainly composed of barium titanate, strontium titanate, calcium titanate, magnesium titanate, calcium zirconate, calcium zirconate titanate, barium zirconate, titanium oxide, etc. Preferably, dielectric ceramics of ε> 1000 or class 2 (high dielectric constant system) can be used. By the way, “Ceramics with almost the same composition and dielectric constant are almost the same” here is a ceramic with the same composition and dielectric constant but with a slight difference of at least one of the composition and dielectric constant from the relation of sintering degree etc. Point to different ceramics.

図1及び図2から分かるように、コンデンサ本体11の高さLと幅Wと高さHはL>H>Wの条件を満足している。また、容量部11bの厚さT2と電歪緩和部11cの厚さT3と特性調整部11dの厚さT4はT2>T3>T4の条件を満足している。さらに、容量部11bの厚さT2と電歪緩和部11cの厚さT3と特性調整部11dの厚さT4と第2保護部11eの厚さT5はT2>T3>T5>T4の条件を満足している。さらに、電歪緩和部11cの厚さT3と特性調整部11dの厚さT4と第2保護部11eの厚さT5とコンデンサ本体11の高さHは、好ましくは0.25≦(T3+T4+T5)/H≦0.4の条件を満足している。さらに、容量部11bの厚さT2と電歪緩和部11cの厚さT3と特性調整部11dの厚さT4とコンデンサ本体11の幅Wは、好ましくは(T2+T3+T4)>Wの条件を満足している。さらに、第1保護部11eの厚さT1は、第2保護部11eの厚さT5と同じか、或いは、第2保護部11eの厚さT5よりも薄くても良いため、第1保護部11eの厚さT1と第2保護部11eの厚さT5はT1≦T5の条件を満足している。これら条件の意義については後に詳述する。   As can be seen from FIGS. 1 and 2, the height L, width W and height H of the capacitor body 11 satisfy the condition of L> H> W. Further, the thickness T2 of the capacitive portion 11b, the thickness T3 of the electrostriction alleviating portion 11c, and the thickness T4 of the characteristic adjustment portion 11d satisfy the conditions of T2> T3> T4. Furthermore, the thickness T2 of the capacitive portion 11b, the thickness T3 of the electrostriction alleviating portion 11c, the thickness T4 of the characteristic adjustment portion 11d, and the thickness T5 of the second protective portion 11e satisfy the conditions of T2> T3> T5> T4. doing. Furthermore, the thickness T3 of the electrostrictive relaxation portion 11c, the thickness T4 of the characteristic adjustment portion 11d, the thickness T5 of the second protective portion 11e, and the height H of the capacitor body 11 are preferably 0.25 ≦ (T3 + T4 + T5) / The condition of H ≦ 0.4 is satisfied. Furthermore, the thickness T2 of the capacitive portion 11b, the thickness T3 of the electrostriction alleviating portion 11c, the thickness T4 of the characteristic adjusting portion 11d, and the width W of the capacitor body 11 preferably satisfy the condition of (T2 + T3 + T4)> W. There is. Furthermore, the thickness T1 of the first protective portion 11e may be the same as the thickness T5 of the second protective portion 11e, or may be thinner than the thickness T5 of the second protective portion 11e. The thickness T1 of the second protective portion 11e and the thickness T5 of the second protective portion 11e satisfy the condition of T1 ≦ T5. The significance of these conditions will be described in detail later.

一方、各外部電極12は、コンデンサ本体11の長さ方向端面と該端面と隣接する4側面の一部を覆うように設けられている。図示を省略したが、各外部電極12はコンデンサ本体11の外面に密着した下地膜と、該下地膜の外面に密着した表面膜との2層構造、或いは、下地膜と表面膜との間に少なくとも1つの中間膜を有する多層構造を有している。下地膜は例えば焼き付け膜から成り、該焼き付け膜には、好ましくはニッケル、銅、パラジウム、白金、銀、金、これらの合金等を主成分した良導体を使用できる。表面膜は例えばメッキ膜から成り、該メッキ膜には、好ましくはスズ、パラジウム、金、亜鉛、これらの合金等を主成分とした良導体を使用できる。中間膜は例えばメッキ膜から成り、該メッキ膜には、好ましくは白金、パラジウム、金、銅、ニッケル、これらの合金等を主成分とした良導体を使用できる。   On the other hand, each external electrode 12 is provided so as to cover a longitudinal end face of the capacitor body 11 and a part of four side faces adjacent to the end face. Although not shown, each external electrode 12 has a two-layer structure of a base film in close contact with the outer surface of the capacitor body 11 and a surface film in close contact with the outer surface of the base film, or between the base film and the surface film. It has a multilayer structure having at least one intermediate film. The base film is made of, for example, a baked film, and preferably used is a good conductor mainly made of nickel, copper, palladium, platinum, silver, gold, alloys thereof and the like. The surface film is made of, for example, a plating film, and preferably, a good conductor mainly composed of tin, palladium, gold, zinc, an alloy of these, or the like can be used for the plating film. The intermediate film is made of, for example, a plating film, and preferably, a good conductor mainly composed of platinum, palladium, gold, copper, nickel, an alloy thereof or the like can be used for the plating film.

ここで、図1及び図2に示した積層セラミックコンデンサ10-1の好ましい製造例を紹介する。第1保護部11aと容量部11bのセラミック層11b2と電歪緩和部11cと特性調整部11dのセラミック層11d2と第2保護部11eがチタン酸バリウムを主成分とし、容量部11bの内部電極層11b1と特性調整部11dの内部電極層11d1がニッケルを主成分とする場合には、先ず、チタン酸バリウム粉末とエタノール(溶剤)とポリビニルブチラール(バインダ)と分散剤等の添加剤を含むセラミックスラリーを準備すると共に、ニッケル粉末とターピネオール(溶剤)とエチルセルロース(バインダ)と分散剤等の添加剤を含む電極ペーストを準備する。   Here, a preferred manufacturing example of the laminated ceramic capacitor 10-1 shown in FIGS. 1 and 2 will be introduced. The first protective portion 11a, the ceramic layer 11b2 of the capacitor portion 11b, the electrostriction reducing portion 11c, the ceramic layer 11d2 of the characteristic adjusting portion 11d and the second protective portion 11e are mainly composed of barium titanate, and the internal electrode layer of the capacitor portion 11b First, when the internal electrode layer 11d1 of 11b1 and the characteristic adjustment unit 11d contains nickel as a main component, first, a ceramic slurry containing barium titanate powder, ethanol (solvent), polyvinyl butyral (binder), and additives such as a dispersing agent And prepare an electrode paste containing nickel powder, terpineol (solvent), ethyl cellulose (binder), and additives such as a dispersant.

そして、ダイコータ等の塗工装置と乾燥装置を用いて、キャリアフィルム上にセラミックスラリーを塗工し乾燥して、第1グリーンシートを作製する。加えて、スクリーン印刷機等の印刷装置と乾燥装置を用いて、第1グリーンシート上に電極ペーストを千鳥状又はマトリクス状に印刷し乾燥して、内部電極層用パターン群が形成された第2グリーンシートを作製する。   Then, using a coating apparatus such as a die coater or the like and a drying apparatus, the ceramic slurry is coated on the carrier film and dried to prepare a first green sheet. In addition, using a printing apparatus such as a screen printing machine and a drying apparatus, the electrode paste is printed in a zigzag or matrix on the first green sheet and dried to form a second internal electrode layer pattern group Make a green sheet.

そして、打ち抜き刃及びヒータを有する吸着ヘッド等の積層装置を用いて、第1グリーンシートから打ち抜いた単位シートを所定数に至るまで積み重ねて熱圧着して、第2保護部11eに対応した部位を作製する。続いて、第2グリーンシートから打ち抜いた単位シート(内部電極層用パターン群を含む)を所定数に至るまで積み重ねて熱圧着して、特性調整部11dに対応した部位を作製する。続いて、第1グリーンシートから打ち抜いた単位シートを所定数に至るまで積み重ねて熱圧着して電歪緩和部11cに対応した部位を作製する。続いて、第2グリーンシートから打ち抜いた単位シート(内部電極層用パターン群を含む)を所定数に至るまで積み重ねて熱圧着して、容量部11bに対応した部位を作製する。続いて、第1グリーンシートから打ち抜いた単位シートを所定数に至るまで積み重ねて熱圧着して、第1保護部11aに対応した部位を作製する。そして、熱間静水圧プレス機等の本圧着装置を用いて、積み重ねて熱圧着したものを最終的に本圧着して、未焼成積層シートを作製する。   Then, using a stacking device such as a suction head having a punching blade and a heater, unit sheets punched from the first green sheet are stacked to a predetermined number and thermocompression-bonded, and a portion corresponding to the second protective portion 11e Make. Subsequently, unit sheets (including the internal electrode layer pattern group) punched out of the second green sheet are stacked up to a predetermined number and thermocompression-bonded to produce a portion corresponding to the characteristic adjustment portion 11 d. Subsequently, unit sheets punched from the first green sheet are stacked up to a predetermined number and thermocompression-bonded to produce a portion corresponding to the electrostriction alleviating portion 11c. Subsequently, unit sheets (including the pattern group for internal electrode layer) punched out of the second green sheet are stacked up to a predetermined number and thermocompression-bonded to produce a portion corresponding to the capacity portion 11b. Subsequently, unit sheets punched from the first green sheet are stacked up to a predetermined number and thermocompression-bonded to produce a portion corresponding to the first protective portion 11a. Then, using an actual pressure bonding apparatus such as a hot isostatic press, the ones that have been stacked and thermocompression-bonded are finally finally pressure-bonded to produce an unfired laminated sheet.

そして、ダイシング機等の切断装置を用いて、未焼成積層シートを格子状に切断して、コンデンサ本体11に対応した未焼成チップを作製する。そして、トンネル型焼成炉等の焼成装置を用いて、多数の未焼成チップを還元性雰囲気下、或いは、低酸素分圧雰囲気下で、チタン酸バリウム及びニッケルに応じた温度プロファイルで焼成(脱バインダ処理と焼成処理を含む)を行って、コンデンサ本体11に対応した焼成チップを作製する。   Then, using a cutting device such as a dicing machine, the unfired laminated sheet is cut into a grid shape to produce unfired chips corresponding to the capacitor body 11. Then, using a firing apparatus such as a tunnel-type firing furnace, firing a large number of unfired chips in a reducing atmosphere or under a low oxygen partial pressure atmosphere with a temperature profile according to barium titanate and nickel The treatment and the firing treatment are carried out) to produce a fired chip corresponding to the capacitor body 11.

そして、ローラ塗布機等の塗布装置を用いて、焼成チップの長さ方向両端部に電極ペースト(内部電極層用の電極ペーストを流用)を塗布し、前記同様の雰囲気下で焼き付け処理を行って下地膜を形成し、その上に表面膜、或いは、中間膜と表面膜を電解メッキ等のメッキ処理で形成して、外部電極を作製する。因みに、下地膜は、未焼成チップの長さ方向両端部に電極ペーストを塗布して乾燥した後、これを未焼成チップと同時焼成することによって作製しても良い。   Then, using a coating apparatus such as a roller coating machine, apply electrode paste (for electrode paste for internal electrode layer) to both ends in the lengthwise direction of the fired chip, and perform baking processing in the same atmosphere as described above. A base film is formed, and a surface film, or an intermediate film and a surface film are formed thereon by plating such as electrolytic plating to produce an external electrode. Incidentally, the base film may be prepared by applying and drying the electrode paste on both end portions in the lengthwise direction of the unfired chip and then co-firing the unfired chip with the electrode paste.

図3は図1及び図2に示した積層セラミックコンデンサ10-1を回路基板21に実装した構造を示す。回路基板21は積層セラミックコンデンサ10-1の各外部電極12に対応した導電性のパッド21aを備えており、各外部電極12の被接合面(コンデンサ本体11の4側面の一部を覆う部分の下面)はハンダ22を用いて各パッド21aの表面に接合されている。各外部電極12の被接合面が接合されるパッド21aの表面形状は、各外部電極12の被接合面形状よりも大きな矩形であるため、実装後の各外部電極12の端面12aには溶融ハンダの濡れ上がりに基づくハンダフィレット22aが形成される。因みに、図3に示したHfは、コンデンサ本体11の高さ方向下面を基準としたハンダフィレット22aの最上点の高さを示す。   FIG. 3 shows a structure in which the multilayer ceramic capacitor 10-1 shown in FIGS. 1 and 2 is mounted on the circuit board 21. As shown in FIG. The circuit board 21 is provided with conductive pads 21 a corresponding to the respective external electrodes 12 of the multilayer ceramic capacitor 10-1, and the bonding surfaces of the respective external electrodes 12 (a part of the portion covering the four side surfaces of the capacitor main body 11) The lower surface is bonded to the surface of each pad 21 a using a solder 22. The surface shape of the pad 21a to which the bonding surface of each external electrode 12 is bonded is a rectangle larger than the bonding surface shape of each external electrode 12, so molten solder is applied to the end surface 12a of each external electrode 12 after mounting. The solder fillet 22a is formed based on the wetting of the solder. Incidentally, Hf shown in FIG. 3 indicates the height of the uppermost point of the solder fillet 22 a with reference to the lower surface in the height direction of the capacitor body 11.

ここで、図1及び図2に示した積層セラミックコンデンサ10-1の好ましい実装例を紹介する。先ず、回路基板21の各パッド21a上に適量のクリームハンダを塗布する。そして、塗布されたクリームハンダに各外部電極12の被接合面が接するように積層セラミックコンデンサ10-1を搭載する。そして、リフローハンダ付け法等の熱処理によって、クリームハンダを一端溶融してから硬化させ、各外部電極12の被接合面をハンダ22を介して各パッド21aの表面に接合する。   Here, a preferred mounting example of the multilayer ceramic capacitor 10-1 shown in FIGS. 1 and 2 will be introduced. First, an appropriate amount of cream solder is applied on each pad 21 a of the circuit board 21. Then, the laminated ceramic capacitor 10-1 is mounted such that the bonding surfaces of the external electrodes 12 are in contact with the applied cream solder. Then, the cream solder is melted at one end and then hardened by heat treatment such as reflow soldering, and the bonding surfaces of the external electrodes 12 are bonded to the surfaces of the pads 21 a via the solder 22.

図4は図1及び図2に示した積層セラミックコンデンサ10-1によって得られる効果を確認するための用意したサンプル1〜6(積層セラミックコンデンサ)の仕様と、比較のために用意したサンプルR(積層セラミックコンデンサ)の仕様と、各サンプル1〜6及びRを回路基板21に実装した状態で測定した特性(音鳴きとESL)を示す。因みに、サンプル1〜6及びRは前記製造例に準じて作製されたものであり、特性は前記実装例に準じて作製された実装構造(図3を参照)にて測定されたものである。   FIG. 4 shows the specifications of Samples 1 to 6 (multilayer ceramic capacitors) prepared for confirming the effects obtained by the laminated ceramic capacitor 10-1 shown in FIGS. 1 and 2 and Sample R prepared for comparison. The specifications of the multilayer ceramic capacitor and the characteristics (noise and ESL) measured in a state where each of the samples 1 to 6 and R is mounted on the circuit board 21 are shown. Incidentally, Samples 1 to 6 and R are produced according to the above-mentioned production example, and the characteristics are measured by the mounting structure (see FIG. 3) produced according to the above-mentioned mounting example.

〈サンプル1の仕様詳細〉
コンデンサ本体11の長さLが1000μm、幅Wが500μm、高さHが702μm。第1保護部11aの厚さT1が25μm、容量部11bの厚さT2が450μm、電歪緩和部11cの厚さT3が200μm、特性調整部11dの厚さT4が2μm、第2保護部11eの厚さT5が25μm。第1保護部11aと容量部11bのセラミック層11b2と電歪緩和部11cと特性調整部11dのセラミック層11d2と第2保護部11eの主成分がチタン酸バリウム、容量部11bの内部電極層11b1と特性調整部11dの内部電極層11d1の主成分がニッケル。容量部11bに含まれる内部電極層11b1が350層、内部電極層11b1の厚さが0.7μm、セラミック層11b2の厚さが0.6μm。特性調整部11dに含まれる内部電極層11d1が2層、内部電極層11d1の0.7μm、セラミック層11d2の厚さが0.6μm。各外部電極12の厚さが10μm、コンデンサ本体11の4側面の一部を覆う部分の長さが230μm。各外部電極12はニッケルを主成分とする下地膜と、銅を主成分とする中間膜と、スズを主成分とする表面膜の3層構造。
<Specification details of sample 1>
The capacitor body 11 has a length L of 1000 μm, a width W of 500 μm, and a height H of 702 μm. The thickness T1 of the first protective portion 11a is 25 μm, the thickness T2 of the capacitive portion 11b is 450 μm, the thickness T3 of the electrostrictive relaxation portion 11c is 200 μm, the thickness T4 of the characteristic adjustment portion 11d is 2 μm, and the second protective portion 11e Thickness T5 is 25 μm. The first protective portion 11a, the ceramic layer 11b2 of the capacitor portion 11b, the electrostrictive relaxation portion 11c, the ceramic layer 11d2 of the characteristic adjusting portion 11d and the second protective portion 11e are barium titanate, and the internal electrode layer 11b1 of the capacitor portion 11b The main component of the internal electrode layer 11d1 of the characteristic adjustment section 11d is nickel. The internal electrode layer 11b1 included in the capacitor portion 11b has 350 layers, the thickness of the internal electrode layer 11b1 is 0.7 μm, and the thickness of the ceramic layer 11b2 is 0.6 μm. The two internal electrode layers 11d1 included in the characteristic adjustment portion 11d, 0.7 μm of the internal electrode layer 11d1, and 0.6 μm of the ceramic layer 11d2. The thickness of each external electrode 12 is 10 μm, and the length covering a part of the four side surfaces of the capacitor body 11 is 230 μm. Each external electrode 12 has a three-layer structure of a base film mainly composed of nickel, an intermediate film mainly composed of copper, and a surface film mainly composed of tin.

〈サンプル2〜6の仕様詳細〉
サンプル2の仕様は、電歪緩和部11cの厚さT3を290μmに増加し、コンデンサ本体11の高さHを792μmとした以外は前記サンプル1と同じ。サンプル3の仕様は、電歪緩和部11cの厚さT3を380μmに増加し、コンデンサ本体11の高さHを882μmとした以外は前記サンプル1と同じ。サンプル4の仕様は、電歪緩和部11cの厚さT3を130μmに減少し、コンデンサ本体11の高さHを632μmとした以外は前記サンプル1と同じ。サンプル5の仕様は、電歪緩和部11cの厚さT3を60μmに減少し、コンデンサ本体11の高さHを562μmとした以外は前記サンプル1と同じ。サンプル6の仕様は、第2保護部11eの厚さT5を45μmに増加し、コンデンサ本体11の高さHを722μmとした以外は前記サンプル1と同じ。
<Specification details of samples 2 to 6>
The specifications of the sample 2 are the same as the sample 1 except that the thickness T3 of the electrostriction alleviating portion 11c is increased to 290 μm and the height H of the capacitor body 11 is set to 792 μm. The specifications of the sample 3 are the same as the sample 1 except that the thickness T3 of the electrostriction alleviating portion 11c is increased to 380 μm and the height H of the capacitor main body 11 is set to 882 μm. The specifications of the sample 4 are the same as the sample 1 except that the thickness T3 of the electrostriction alleviating portion 11c is reduced to 130 μm and the height H of the capacitor main body 11 is set to 632 μm. The specifications of the sample 5 are the same as the sample 1 except that the thickness T3 of the electrostriction alleviating portion 11c is reduced to 60 μm and the height H of the capacitor main body 11 is set to 562 μm. The specifications of the sample 6 are the same as the sample 1 except that the thickness T5 of the second protective portion 11 e is increased to 45 μm and the height H of the capacitor body 11 is set to 722 μm.

〈サンプルRの仕様詳細〉
コンデンサ本体11から電歪緩和部11cと特性調整部11dを無くして、コンデンサ本体11の高さHを500μmとした以外は前記サンプル1と同じ。このサンプルRはサンプル1〜6のような電歪緩和部11c及び特性調整部11dを有しないことから、前記製造例からこれらを作製する工程を除外して作製されている。
<Specification details of sample R>
The same as the sample 1 except that the electrostriction alleviating portion 11 c and the characteristic adjusting portion 11 d are eliminated from the capacitor main body 11 and the height H of the capacitor main body 11 is 500 μm. Since this sample R does not have the electrostriction relaxation part 11c and the characteristic adjustment part 11d like the samples 1-6, it is produced excluding the process of producing these from the said manufacture example.

〈実装構造の仕様詳細〉
回路基板21の厚さが150μm、各パッド21aの厚さが15μm。各パッド21aの長さが400μm、幅が600μm、長さ方向間隔が400μm。回路基板21の主成分がエポキシ樹脂、各パッド22の主成分が銅。ハンダ22がスズ−アンチモン系ハンダ、クリームハンダの塗布量が厚さ換算で50μm。ハンダフィレット22aの最上点の高さHfは100〜300μm。先に述べたように、ハンダフィレット22aは外部電極12の端面12aにおける溶融ハンダの濡れ上がりに基づくものであるため、最上点の高さHfに前記のような範囲が生じるが、該範囲内であれば実装不良にはならない。
<Specification details of mounting structure>
The thickness of the circuit board 21 is 150 μm, and the thickness of each pad 21 a is 15 μm. Each pad 21a has a length of 400 μm, a width of 600 μm, and a distance in the lengthwise direction of 400 μm. The main component of the circuit board 21 is epoxy resin, and the main component of each pad 22 is copper. The solder 22 is a tin-antimony solder, and the amount of cream solder applied is 50 μm in terms of thickness. The height Hf of the uppermost point of the solder fillet 22a is 100 to 300 μm. As described above, since the solder fillet 22a is based on wetting of the molten solder at the end face 12a of the external electrode 12, the above-described range occurs in the height Hf of the uppermost point, but within this range If it does, it will not become a mounting defect.

〈音鳴きの測定方法〉
各サンプル1〜6及びRを用いた実装構造(図3を参照)を10個作製し、回路基板21の各パッド21aを通じて両外部電極12に交流電圧5Vを周波数を0〜1MHzに上げながら印加し、このときに発生した可聴域の音の強さを、TYPe−3560−B130(ブリュエル・ケア・ジャパン製)を用いて、防音・無響室(横浜音環境システムズ製)の中で個別に測定した。因みに、図4中の「音鳴き(db)」は、各10個の実装構造における音鳴きの強さの平均値である。
<Measurement method of sound noise>
Ten mounting structures (see FIG. 3) using each of the samples 1 to 6 and R are fabricated and applied while raising the frequency to 5 to 1 MHz to both external electrodes 12 through each pad 21a of the circuit board 21 And the intensity of the sound in the audible range generated at this time using the TYPe-3560-B130 (made by BRUEEL CARE JAPAN) individually in the soundproof and anechoic room (made by Yokohama Sound Environment Systems). It was measured. By the way, "sounding (db)" in FIG. 4 is an average value of the sounding strength in each of ten mounting structures.

〈ESL(等価直列インダクタンス)の測定方法〉
各サンプル1〜6及びRを用いた実装構造(図3を参照)を10個作製し、回路基板21の各パッド21aを通じて両外部電極12にオシレーションレベルを0dbmとして周波数を1MHz〜3GHzの範囲で印加し、このときに発生したESL(ESL特性)を、4991A(アジレント・テクノロジー製)を用いて個別に測定した。因みに、図4中の「ESL(nH)」は、各10個の実装構造における1000MHzのESLの平均値である。
<Method of measuring ESL (equivalent series inductance)>
Ten mounting structures (see FIG. 3) using each of the samples 1 to 6 and R are manufactured, and an oscillation level of 0 dbm is applied to both external electrodes 12 through each pad 21a of the circuit board 21 in a frequency range of 1 MHz to 3 GHz. The ESL (ESL characteristic) generated at this time was individually measured using 4991A (manufactured by Agilent Technologies). Incidentally, “ESL (nH)” in FIG. 4 is an average value of 1000 MHz ESL in each of 10 mounting structures.

各サンプル1〜6及びRを用いた実装構造にあっては、回路基板21の各パッド21aを通じて両外部電極12に電圧、特に交流電圧が印加されると、コンデンサ本体11に電歪現象に基づく伸縮(主として容量部11bが長さ方向に縮むような収縮及びその復元)が生じる。しかしながら、サンプル1〜6のコンデンサ本体11は、何れも、容量部11bの下側に電歪緩和部11cと特性調整部11dと第2保護部11eを有しているため、該容量部11bに生じた伸縮に伴う応力の下方伝達を電歪緩和部11cと特性調整部11dと第2保護部11eによって徐々に減衰することができる。依って、ハンダフィレット22aの最上点の高さHfに拘わらず、実装状態において前記伸縮に伴う応力が回路基板21に伝わることを軽減して音鳴きを抑制することができる。   In the mounting structure using each of the samples 1 to 6 and R, when a voltage, in particular an AC voltage, is applied to the two external electrodes 12 through the pads 21 a of the circuit board 21, the capacitor body 11 is based on electrostriction. Expansion and contraction (contraction and restoration such that the capacity portion 11b contracts in the longitudinal direction) occur. However, since each of the capacitor bodies 11 of Samples 1 to 6 has the electrostriction alleviation portion 11c, the characteristic adjustment portion 11d and the second protection portion 11e on the lower side of the capacitance portion 11b, the capacitance portion 11b The downward transmission of the stress caused by the expansion and contraction can be gradually attenuated by the electrostrictive relaxation portion 11c, the characteristic adjustment portion 11d, and the second protective portion 11e. Therefore, regardless of the height Hf of the uppermost point of the solder fillet 22a, it is possible to reduce the transfer of the stress accompanying the expansion and contraction to the circuit board 21 in the mounted state, and to suppress the noise.

また、各サンプル1〜6及びRを用いた実装構造にあっては、コンデンサ本体11の容量部11bと第2保護部11eとの間に電歪緩和部11cが介在するため、該容量部11bとパッド21aとの高さ間隔がサンプルRよりも大きくなるが故にESLが増加する。しかしながら、サンプル1〜6のコンデンサ本体11は、何れも、電歪緩和部11cと第2保護部11eとの間に2層の内部電極層11d1を含む特性調整部11dが介在しているため、該2層の内部電極層11d1を電流ルートとして利用してインピーダンスを低減することができる。依って、ハンダフィレット22aの最上点の高さHfに拘わらず、実装状態における低ESL化を実現することができる。   Further, in the mounting structure using each of the samples 1 to 6 and R, since the electrostriction alleviating portion 11c is interposed between the capacitance portion 11b of the capacitor main body 11 and the second protective portion 11e, the capacitance portion 11b The ESL increases because the height interval between and the pad 21a becomes larger than the sample R. However, in each of the capacitor bodies 11 of Samples 1 to 6, since the characteristic adjustment portion 11d including the two-layer internal electrode layer 11d1 is interposed between the electrostriction alleviation portion 11c and the second protection portion 11e, The impedance can be reduced by utilizing the two internal electrode layers 11d1 as a current route. Thus, regardless of the height Hf of the uppermost point of the solder fillet 22a, it is possible to realize low ESL in the mounted state.

以下、図4に示した各サンプル1〜6及びRの仕様と特性(音鳴きとESL)を考慮の上で、図1及び図2に示した積層セラミックコンデンサ10-1によって得られる効果について説明する。   Hereinafter, in consideration of the specifications and characteristics (sound noise and ESL) of each of the samples 1 to 6 and R shown in FIG. 4, the effect obtained by the laminated ceramic capacitor 10-1 shown in FIGS. 1 and 2 will be described. Do.

第1に、サンプル1〜6の「音鳴き(db)」の値はサンプルRの「音鳴き(db)」の値よりも低く、しかも、サンプル1〜6の「ESL(nH)」の値はサンプルRの「ESL(nH)」の値と殆ど差が無い。サンプル1〜6は、何れも、「容量部11bの厚さT2>電歪緩和部11cの厚さT3>特性調整部11dの厚さT4」の条件を満足しているため、この条件を満足していれば音鳴き抑制に有効であり、しかも、低ESL化に適していると言える。また、サンプル1〜6は、何れも、「容量部11bの厚さT2>電歪緩和部11cの厚さT3>第2保護部11eの厚さT5>特性調整部11dの厚さT4」の条件も満足しているため、この条件を満足していても同様のことが言える。   First, the value of "sounds (db)" of samples 1 to 6 is lower than the value of "sounds (db)" of sample R, and the value of "ESL (nH)" of samples 1 to 6 There is almost no difference from the value of “ESL (nH)” of sample R. All of the samples 1 to 6 satisfy the condition of “the thickness T2 of the capacitive portion 11 b> the thickness T3 of the electrostriction alleviating portion 11c> the thickness T4 of the characteristic adjusting portion 11d”. If it is done, it is effective for sound noise suppression and it can be said that it is suitable for low ESL. In each of the samples 1 to 6, “the thickness T2 of the capacitive portion 11 b> the thickness T3 of the electrostrictive relaxation portion 11c> the thickness T5 of the second protective portion 11e> the thickness T4 of the characteristic adjustment portion 11d”. Since the condition is also satisfied, the same can be said even if this condition is satisfied.

第2に、サンプル1〜4及び6の「音鳴き(db)」の値は理想値である25dbを下回っている。サンプル1〜4及び6は、何れも、「0.25≦(電歪緩和部11cの厚さT3+特性調整部11dの厚さT4+第2保護部11eの厚さT5)/コンデンサ本体11の高さH≦0.4」の条件の満足していることから、音鳴き抑制を重視する場合には、前記「容量部11bの厚さT2>電歪緩和部11cの厚さT3>特性調整部11dの厚さT4」の条件に加えて「0.25≦(電歪緩和部11cの厚さT3+特性調整部11dの厚さT4+第2保護部11eの厚さT5)/コンデンサ本体11の高さH≦0.4」の条件を満足していることが好ましいと言える。   Second, the values of "Sound (db)" of Samples 1 to 4 and 6 are less than the ideal value of 25 db. In each of the samples 1 to 4 and 6, “0.25 ≦ (thickness T3 of the electrostriction alleviating portion 11c + thickness T4 of the characteristic adjusting portion 11d + thickness T5 of the second protective portion 11e) / height of the capacitor main body 11” Since the condition of “H ≦ 0.4” is satisfied, in the case where importance is attached to the suppression of noise, “the thickness T2 of the capacitive portion 11b> the thickness T3 of the electrostriction alleviating portion 11c> the characteristic adjusting portion In addition to the condition of thickness T4 of 11 d, “0.25 ≦ (thickness T3 of electrostrictive relaxation portion 11 c + thickness T4 of characteristic adjustment portion 11 d + thickness T5 of second protective portion 11 e) / height of capacitor main body 11 It can be said that it is preferable to satisfy the condition of “H ≦ 0.4”.

第3に、サンプル1〜6は、何れも、「(容量部11bの厚さT2+電歪緩和部11cの厚さT3+第2保護部11eの厚さT5)>コンデンサ本体11の幅W」の条件も満足しているため、前記「容量部11bの厚さT2>電歪緩和部11cの厚さT3>特性調整部11dの厚さT4」の条件に加えて「(容量部11bの厚さT2+電歪緩和部11cの厚さT3+第2保護部11eの厚さT5)>コンデンサ本体11の幅W」の条件を満足していれば、音鳴き抑制に有効であり、しかも、低ESL化に適していると言える。   Thirdly, in all of the samples 1 to 6, "(thickness T2 of the capacitive portion 11b + thickness T3 of the electrostriction relaxation portion 11c + thickness T5 of the second protective portion 11e)> width W of the capacitor main body 11" Since the condition is also satisfied, in addition to the condition “the thickness T2 of the capacitive portion 11 b> the thickness T3 of the electrostriction alleviating portion 11> the thickness T4 of the characteristic adjustment portion 11d”, “the thickness of the capacitive portion 11b is If the condition of T2 + thickness T3 of the second protective portion 11 e> width W of the second protection portion 11> width W of the capacitor body 11 is satisfied, it is effective for suppressing noise, and moreover, ESL reduction It is suitable for

第4に、サンプル6は、サンプル1〜5に比べて、第2保護部11eの厚さT5が2倍ほど厚いが、「音鳴き(db)」の値と「ESL(nH)」の値はサンプル1を用いた実装構造と殆ど変わらない。つまり、前記「容量部11bの厚さT2>電歪緩和部11cの厚さT3>特性調整部11dの厚さT4」の条件に加えて「第1保護部11aの厚さT1≦第2保護部11eの厚さT5」の条件を満足していれば、音鳴き抑制に有効であり、しかも、低ESL化に適していると言える。因みに、第2保護部11eの厚さT5を第1保護部11aの厚さT1よりも厚くした場合の利点としては、製造時の焼成工程で、特性調整部11dに含まれる2層の内部電極層11d1のうちの最も外側の内部電極層11d1が酸化して導電性が損なわれることを防止して、2層の内部電極層11d1による電流ルートの確保を確実に行える点を挙げることができる。   Fourth, although the thickness T5 of the second protective portion 11 e is twice as thick as that of the samples 1 to 5 in the sample 6, the value of the “sound crunching (db)” and the value of the “ESL (nH)” Is almost the same as the mounting structure using sample 1. That is, in addition to the condition of "the thickness T2 of the capacitive portion 11b> the thickness T3 of the electrostriction alleviating portion 11> the thickness T4 of the characteristic adjusting portion 11d", the "thickness T1 of the first protective portion 11a ≦ the second protection" If the condition of the thickness T5 of the portion 11e is satisfied, it can be said that it is effective for suppressing noise and that it is suitable for lowering ESL. Incidentally, as an advantage in the case where the thickness T5 of the second protective portion 11e is larger than the thickness T1 of the first protective portion 11a, the two-layer internal electrodes included in the characteristic adjustment portion 11d in the firing step at the time of manufacture It is possible to prevent the conductivity of the outermost internal electrode layer 11d1 of the layer 11d1 from being oxidized and lose its conductivity, and to secure the current route by the two internal electrode layers 11d1.

第5に、サンプル1〜6は、何れも、「コンデンサ本体11の長さL>コンデンサ本体11の高さH>コンデンサ本体11の幅W」の条件を満足していることから、捉え方を変えると、前記「容量部11bの厚さT2>電歪緩和部11cの厚さT3>特性調整部11dの厚さT4」の条件に加えて「コンデンサ本体11の長さL>コンデンサ本体11の高さH>コンデンサ本体11の幅W」の条件を満足していれば、音鳴き抑制に有効であり、しかも、低ESL化に適していると言える。   Fifth, all of the samples 1 to 6 satisfy the condition of "length L of capacitor body 11> height H of capacitor body 11> width W of capacitor body 11". In addition to the condition “the thickness T2 of the capacitive portion 11b> the thickness T3 of the electrostriction alleviating portion 11> the thickness T4 of the characteristic adjusting portion 11d”, the length L of the capacitor main body 11 of the capacitor main body 11 is changed. If the condition of the height H> the width W of the capacitor body 11 is satisfied, it is effective for suppressing the noise generation and it can be said that it is suitable for reducing the ESL.

このように、図1及び図2に示した積層セラミックコンデンサ10-1は、実装状態における音鳴き抑制に対し実用性が極めて高いことに加え、高周波回路のインピーダンス低減やノイズ除去等に有用な低ESL化を確実に実現することができる。   Thus, in addition to the fact that the laminated ceramic capacitor 10-1 shown in FIGS. 1 and 2 has extremely high practicability with respect to the suppression of noise in the mounted state, it is useful for reducing the impedance of high frequency circuits and removing noise. The ESL can be realized reliably.

《第2実施形態》
図5は本発明を適用した積層セラミックコンデンサ10-2(第2実施形態)を示す。この積層セラミックコンデンサ10-2は、図1及び図2に示した積層セラミックコンデンサ10-1(第1実施形態)と、特性調整部11d-2に含まれる内部電極層11d1を4層に増加し、図5の上から奇数番目に当たる2層の端縁を外部電極12の一方(図5の左側)に電気的に接続し、且つ、図5の上から偶数番目に当たる2層の端縁を外部電極12の他方(図5の右側)に電気的に接続した点で異なる。
Second Embodiment
FIG. 5 shows a multilayer ceramic capacitor 10-2 (second embodiment) to which the present invention is applied. In this multilayer ceramic capacitor 10-2, the number of layers of the multilayer ceramic capacitor 10-1 (first embodiment) shown in FIGS. 1 and 2 and the internal electrode layer 11d1 included in the characteristic adjustment portion 11d-2 is increased to four. 5, the edges of the two layers which are odd from the top of FIG. 5 are electrically connected to one of the external electrodes 12 (the left side of FIG. 5), and the edges of the two layers which are even from the top of FIG. It differs in that it is electrically connected to the other side (right side of FIG. 5) of the electrode 12.

この積層セラミックコンデンサ10-2は、第1実施形態の欄で説明した好ましい製造例における積層工程で特性調整部11d-2に対応した部位を作製する際に、第2グリーンシートから打ち抜いた単位シートの積み重ね数を2から4に増加することによって製造することができる。因みに、この積層セラミックコンデンサ10-2の好ましい実装例及び実装構造は、第1実施形態の欄で説明した実装例及び実装構造(図3を参照)と同じである。   This multilayer ceramic capacitor 10-2 is a unit sheet punched out of the second green sheet when producing a portion corresponding to the characteristic adjustment portion 11d-2 in the laminating step in the preferred manufacturing example described in the section of the first embodiment. Can be manufactured by increasing the number of stacks of 2 to 4. Incidentally, the preferred mounting example and mounting structure of the multilayer ceramic capacitor 10-2 are the same as the mounting example and mounting structure (see FIG. 3) described in the section of the first embodiment.

図5に示した積層セラミックコンデンサ10-2は、製造時の焼成工程で、特性調整部11d-2に含まれる4層の内部電極層11d1のうちの最も外側の内部電極層11d1が酸化して導電性が損なわれた場合でも、残りの内部電極層11d1によって電流ルートを確実に確保して所期のインピーダンス低減を確実に行うことができる。この効果は特性調整部11d-2に含まれる内部電極層11d1を3層とした場合や5層以上とした場合でも同様に得ることができるが、特性調整部11d-2は容量確保を目的としたものではないため、内部電極層11d1は3層又は4層が好ましい。他の効果は図1及び図2に示した積層セラミックコンデンサ10-1によって得られる効果と同様であるため、その説明を省略する。   In the laminated ceramic capacitor 10-2 shown in FIG. 5, the outermost internal electrode layer 11d1 of the four internal electrode layers 11d1 included in the characteristic adjustment portion 11d-2 is oxidized in the firing step during manufacturing. Even when the conductivity is lost, the remaining internal electrode layer 11d1 can ensure the current route to reliably reduce the desired impedance. This effect can be obtained similarly even when the number of internal electrode layers 11d1 included in the characteristic adjustment unit 11d-2 is three or five or more, but the characteristic adjustment unit 11d-2 is intended to secure a capacity. In the internal electrode layer 11d1, three or four layers are preferable. The other effects are the same as the effects obtained by the laminated ceramic capacitor 10-1 shown in FIGS. 1 and 2, and thus the description thereof is omitted.

《第3実施形態》
図6は本発明を適用した積層セラミックコンデンサ10-3(第3実施形態)を示す。この積層セラミックコンデンサ10-3は、図1及び図2に示した積層セラミックコンデンサ10-1(第1実施形態)と、特性調整部11d-3に含まれる2層の内部電極層11d1のうち、図6の上から奇数番目に当たる1層の端縁を外部電極12の他方(図6の右側)に電気的に接続し、且つ、図6の上から偶数番目に当たる1層の端縁を外部電極12の一方(図6の左側)電気的に接続した点で異なる。即ち、電歪緩和部11cを介して向き合う容量部11bの内部電極層11b1の端縁と特性調整部11d-3の内部電極層11d1の端縁は、外部電極12の一方及び他方のうちの同じ側の外部電極12に電気的に接続されている。
Third Embodiment
FIG. 6 shows a laminated ceramic capacitor 10-3 (third embodiment) to which the present invention is applied. The multilayer ceramic capacitor 10-3 includes the multilayer ceramic capacitor 10-1 (first embodiment) shown in FIG. 1 and FIG. 2 and the two internal electrode layers 11d1 included in the characteristic adjustment section 11d-3. The edge of one layer which is odd from the top of FIG. 6 is electrically connected to the other of the external electrode 12 (right side of FIG. 6), and the edge of one layer which is even from the top of FIG. It differs in that one of the twelve (the left side in FIG. 6) is electrically connected. That is, the edge of the internal electrode layer 11b1 of the capacitor portion 11b facing through the electrostriction alleviating portion 11c and the edge of the internal electrode layer 11d1 of the characteristic adjustment portion 11d-3 are the same among one and the other of the external electrode 12 It is electrically connected to the external electrode 12 on the side.

この積層セラミックコンデンサ10-3は、第1実施形態の欄で説明した好ましい製造例における積層工程で特性調整部11d-3に対応した部位を作製する際に、第2グリーンシートから打ち抜いた単位シートの積み重ね向きを180度変えることによって製造することができる。因みに、この積層セラミックコンデンサ10-3の好ましい実装例及び実装構造は、第1実施形態の欄で説明した実装例及び実装構造(図3を参照)と同じである。   This multilayer ceramic capacitor 10-3 is a unit sheet punched out of the second green sheet when producing a portion corresponding to the characteristic adjusting portion 11d-3 in the laminating step in the preferred manufacturing example described in the section of the first embodiment. It can be manufactured by changing the stacking direction of. Incidentally, the preferred mounting example and mounting structure of the multilayer ceramic capacitor 10-3 are the same as the mounting example and mounting structure (see FIG. 3) described in the section of the first embodiment.

図6に示した積層セラミックコンデンサ10-3は、実装状態における電圧印加時において、電歪緩和部11cを介して向き合う容量部11bの内部電極層11b1と特性調整部11d-3の内部電極層11d1とが同一極性となるため、とりわけ電歪緩和層11cの厚さT3が薄い場合にこれら内部電極層11b1及び11d1によって電歪緩和層11cに電界が形成されて電歪を生じることを回避して、所期の音鳴き抑制を確実に行うことができる。他の効果は図1及び図2に示した積層セラミックコンデンサ10-1によって得られる効果と同様であるため、その説明を省略する。   In the multilayer ceramic capacitor 10-3 shown in FIG. 6, when a voltage is applied in the mounted state, the internal electrode layer 11b1 of the capacitive portion 11b and the internal electrode layer 11d1 of the characteristic adjustment portion 11d-3 face each other via the electrostriction alleviating portion 11c. Therefore, in particular when the thickness T3 of the electrostriction alleviating layer 11c is small, the internal electrode layers 11b1 and 11d1 avoid that an electric field is formed in the electrostriction alleviating layer 11c to cause electrostriction. The desired noise suppression can be reliably performed. The other effects are the same as the effects obtained by the laminated ceramic capacitor 10-1 shown in FIGS. 1 and 2, and thus the description thereof is omitted.

尚、図6に示した積層セラミックコンデンサ10-3に、第2実施形態の欄で説明した思想(特性調整部に含まれる内部電極層を3層又は4層とする思想)を採用しても良い。   Even if the idea described in the section of the second embodiment (the idea that the internal electrode layers included in the characteristic adjusting portion are made three or four layers) is adopted for the laminated ceramic capacitor 10-3 shown in FIG. good.

《第4実施形態》
図7は本発明を適用した積層セラミックコンデンサ10-4(第4実施形態)を示す。この積層セラミックコンデンサ10-4は、図1及び図2に示した積層セラミックコンデンサ10-1(第1実施形態)と、特性調整部11d-4に含まれる2層の内部電極層11d1’の対向面積を、容量部11bに含まれる24層の内部電極層11b1の対向面積よりも小さくした点で異なる。
Fourth Embodiment
FIG. 7 shows a laminated ceramic capacitor 10-4 (fourth embodiment) to which the present invention is applied. In the multilayer ceramic capacitor 10-4, the multilayer ceramic capacitor 10-1 (first embodiment) shown in FIGS. 1 and 2 and the two internal electrode layers 11d1 'included in the characteristic adjustment section 11d-4 are opposed to each other. The difference is that the area is made smaller than the facing area of the 24 layers of internal electrode layers 11b1 included in the capacitive portion 11b.

この積層セラミックコンデンサ10-4は、第1実施形態の欄で説明した好ましい製造例における積層工程で特性調整部11d-4に対応した部位を作製する際に、第2グリーンシートの内部電極層用パターン群よりも長さが短いパターン群が形成された第3グリーンシートを用いることによって製造することができる。因みに、この積層セラミックコンデンサ10-4の好ましい実装例及び実装構造は、第1実施形態の欄で説明した実装例及び実装構造(図3を参照)と同じである。   This multilayer ceramic capacitor 10-4 is for the internal electrode layer of the second green sheet when producing a portion corresponding to the characteristic adjustment portion 11d-4 in the laminating step in the preferred manufacturing example described in the section of the first embodiment. It can manufacture by using the 3rd green sheet in which the pattern group whose length is shorter than a pattern group was formed. Incidentally, the preferred mounting example and mounting structure of the multilayer ceramic capacitor 10-4 are the same as the mounting example and mounting structure (see FIG. 3) described in the section of the first embodiment.

図7に示した積層セラミックコンデンサ10-4は、特性調整部11d-4に含まれる2層の内部電極層11d1’の対向面積が容量部11bに含まれる24層の内部電極層11b1の対向面積よりも小さいため、特性調整部11d-4に形成される容量を極力低減して該特性調整部11d-4を電流ルートの確保に重点を置いたものとすることができる。他の効果は図1及び図2に示した積層セラミックコンデンサ10-1によって得られる効果と同様であるため、その説明を省略する。   In the multilayer ceramic capacitor 10-4 shown in FIG. 7, the opposing area of the two layers of internal electrode layers 11d1 'included in the characteristic adjustment part 11d-4 is the opposing area of the 24 layers of internal electrode layers 11b1 included in the capacitive part 11b. Since the capacitance is smaller than the above, it is possible to reduce the capacitance formed in the characteristic adjustment unit 11d-4 as much as possible and place emphasis on securing the current route. The other effects are the same as the effects obtained by the laminated ceramic capacitor 10-1 shown in FIGS. 1 and 2, and thus the description thereof is omitted.

尚、図7に示した積層セラミックコンデンサ10-4に、第2実施形態の欄で説明した思想(特性調整部に含まれる内部電極層を3層又は4層とする思想)を採用しても良い。   Even if the idea described in the section of the second embodiment (the idea that the internal electrode layers included in the characteristic adjusting portion are made to be three or four layers) is adopted for the laminated ceramic capacitor 10-4 shown in FIG. good.

《第5実施形態》
図8は本発明を適用した積層セラミックコンデンサ10-5(第5実施形態)を示す。この積層セラミックコンデンサ10-5は、図1及び図2に示した積層セラミックコンデンサ10-1(第1実施形態)と、電歪緩和部11c-5が、第1保護部11a、容量部11bに含まれる23層のセラミック層11b2、特性調整部11dに含まれる1層のセラミック層11d2及び第2保護部11eと組成を異する低誘電率のセラミックスから成る点で異なる。
Fifth Embodiment
FIG. 8 shows a laminated ceramic capacitor 10-5 (fifth embodiment) to which the present invention is applied. In this multilayer ceramic capacitor 10-5, the multilayer ceramic capacitor 10-1 (first embodiment) shown in FIG. 1 and FIG. 2 and the electrostriction alleviating portion 11c-5 are the first protective portion 11a and the capacitive portion 11b. The present embodiment is different in that it is composed of a low dielectric constant ceramic whose composition is different from that of the 23 layers of the ceramic layer 11b2 contained and the one layer of the ceramic layer 11d2 and the second protective portion 11e contained in the characteristic adjustment portion 11d.

この積層セラミックコンデンサ10-5は、第1実施形態の欄で説明した好ましい製造例におけるシート作製工程で第1グリーンシートと組成を異する低誘電率の第4グリーンシートを作製し、積層工程で電歪緩和部11c-5に対応した部位を作製する際に該第4グリーンシートから打ち抜いた単位シートを所定数に至るまで積み重ねて熱圧着することによって製造することができる。第4グリーンシートは、第1グリーンシート用セラミックスラリーで用いられているセラミックスの種類を低誘電率のものに変えたセラミックスラリーや、セラミックスの種類を変えずに低誘電率化に適した副成分(例えばMg等のアルカリ土類金属元素の化合物やMn等の遷移金属元素の化合物)を添加又は該副成分の含有量を増加したセラミックスラリー等を用いて作製することができる。因みに、この積層セラミックコンデンサ10-5の好ましい実装例及び実装構造は、第1実施形態の欄で説明した実装例及び実装構造(図3を参照)と同じである。   In this laminated ceramic capacitor 10-5, a low dielectric constant fourth green sheet having a composition different from that of the first green sheet is produced in the sheet producing step in the preferred production example described in the section of the first embodiment. When producing a portion corresponding to the electrostriction alleviating portion 11c-5, it can be manufactured by stacking unit sheets punched out of the fourth green sheet up to a predetermined number and thermocompression bonding. The fourth green sheet is a ceramic slurry obtained by changing the type of ceramics used in the ceramic slurry for the first green sheet to one having a low dielectric constant, and a subcomponent suitable for lowering the dielectric constant without changing the type of ceramics. (For example, a compound of an alkaline earth metal element such as Mg or a compound of a transition metal element such as Mn) can be added or manufactured using a ceramic slurry or the like in which the content of the subcomponents is increased. Incidentally, the preferred mounting example and mounting structure of the multilayer ceramic capacitor 10-5 are the same as the mounting example and mounting structure (see FIG. 3) described in the section of the first embodiment.

図8に示した積層セラミックコンデンサ10-5は、電歪緩和部11c-5の誘電率が、第1保護部11a、容量部11bに含まれる23層のセラミック層11b2、特性調整部11dに含まれる1層のセラミック層11d2及び第2保護部11eの誘電率よりも低いため、実装状態における電圧印加時において電歪緩和層11cに生じ得る電歪を極力低減して、所期の音鳴き抑制を確実に行うことができる。他の効果は図1及び図2に示した積層セラミックコンデンサ10-1によって得られる効果と同様であるため、その説明を省略する。   In the multilayer ceramic capacitor 10-5 shown in FIG. 8, the dielectric constant of the electrostriction alleviating portion 11c-5 is included in the first protective portion 11a, the 23 layers of the ceramic layer 11b2 included in the capacitive portion 11b, and the characteristic adjustment portion 11d. Is lower than the dielectric constant of the first ceramic layer 11d2 and the second protective portion 11e, electrostriction that may occur in the Can be done reliably. The other effects are the same as the effects obtained by the laminated ceramic capacitor 10-1 shown in FIGS. 1 and 2, and thus the description thereof is omitted.

尚、図8に示した積層セラミックコンデンサ10-5に、第2〜第4実施形態の欄で説明した思想(特性調整部に含まれる内部電極層を3層又は4層とする思想や、特性調整部に含まれる内部電極層の向きを変える思想や、特性調整部に含まれる内部電極層の対向面積を減少させる思想)を適宜採用しても良い。   In the multilayer ceramic capacitor 10-5 shown in FIG. 8, the idea described in the section of the second to fourth embodiments (the idea that the internal electrode layer included in the characteristic adjusting portion is three or four layers, or the characteristic) The idea of changing the orientation of the internal electrode layer included in the adjustment unit, or the idea of reducing the facing area of the internal electrode layer included in the characteristic adjustment portion may be adopted as appropriate.

《第6実施形態》
図9は本発明を適用した積層セラミックコンデンサ10-6(第6実施形態)を示す。この積層セラミックコンデンサ10-6は、図1及び図2に示した積層セラミックコンデンサ10-1(第1実施形態)と、特性調整部11d-6に含まれる1層のセラミック層11d2’が、第1保護部11a、容量部11bに含まれる23層のセラミック層11b2、電歪緩和部11c及び第2保護部11eと組成を異する低誘電率のセラミックスから成る点で異なる。
Sixth Embodiment
FIG. 9 shows a laminated ceramic capacitor 10-6 (sixth embodiment) to which the present invention is applied. In this multilayer ceramic capacitor 10-6, the multilayer ceramic capacitor 10-1 (first embodiment) shown in FIG. 1 and FIG. 2 and one ceramic layer 11d2 'included in the characteristic adjustment section The first embodiment differs from the first embodiment in that it is made of low dielectric constant ceramics having a composition different from that of the 23 protective layer 11b2 included in the protective portion 11a and the capacitive portion 11b, the electrostrictive portion 11c and the second protective portion 11e.

この積層セラミックコンデンサ10-6は、第1実施形態の欄で説明した好ましい製造例におけるシート作製工程で第1グリーンシートと組成を異する低誘電率の第4グリーンシートを作製して該第4グリーンシート上に内部電極層用パターン群を形成した第5グリーンシートを作製し、積層工程で特性調整部11d-6を作製する際に第2グリーンシートから打ち抜いた単位シート(内部電極層用パターン群を含む)を積み重ねて熱圧着し、続けて第5グリーンシートから打ち抜いた単位シート(内部電極層用パターン群を含む)を積み重ねて熱圧着することによって製造することができる。第4グリーンシートの作製例については第5実施形態の欄で述べた通りであるため、その説明を省略する。因みに、この積層セラミックコンデンサ10-5の好ましい実装例及び実装構造は、第1実施形態の欄で説明した実装例及び実装構造(図3を参照)と同じである。   This multilayer ceramic capacitor 10-6 is manufactured by forming a fourth green sheet with a low dielectric constant which differs in composition from the first green sheet in the sheet manufacturing process in the preferred manufacturing example described in the section of the first embodiment. A fifth green sheet in which a pattern group for internal electrode layer is formed on a green sheet is produced, and a unit sheet (pattern for internal electrode layer) punched out from the second green sheet when producing the characteristic adjustment section 11d-6 in the laminating step It can manufacture by laminating | stacking and thermocompression-bonding the group, and laminating | stacking and thermocompression-bonding the unit sheet (inclusive of the pattern group for internal electrode layers) which followed and was pierced from the 5th green sheet. The production example of the fourth green sheet is as described in the section of the fifth embodiment, and thus the description thereof is omitted. Incidentally, the preferred mounting example and mounting structure of the multilayer ceramic capacitor 10-5 are the same as the mounting example and mounting structure (see FIG. 3) described in the section of the first embodiment.

図9に示した積層セラミックコンデンサ10-6は、特性調整部11d-6に含まれる1層のセラミック層11d2’の誘電率が、第1保護部11a、容量部11bに含まれる23層のセラミック層11b2、電歪緩和部11c及び第2保護部11eの誘電率よりも低いため、実装状態における電圧印加時において特性調整部11d-6に生じ得る電歪を極力低減して、所期の音鳴き抑制を確実に行うことができる。他の効果は図1及び図2に示した積層セラミックコンデンサ10-1によって得られる効果と同様であるため、その説明を省略する。   In the multilayer ceramic capacitor 10-6 shown in FIG. 9, the dielectric constant of one layer of the ceramic layer 11d2 'included in the characteristic adjustment portion 11d-6 is a 23-layer ceramic included in the first protective portion 11a and the capacitive portion 11b. Since the dielectric constant of the layer 11b2, the electrostriction alleviating portion 11c, and the second protective portion 11e is lower than that of the layer 11b 2, the electrostriction that may occur in the characteristic adjustment portion 11d-6 during voltage application in the mounted state is reduced as much Squeak suppression can be performed reliably. The other effects are the same as the effects obtained by the laminated ceramic capacitor 10-1 shown in FIGS. 1 and 2, and thus the description thereof is omitted.

尚、図9に示した積層セラミックコンデンサ10-6に、第2〜第4実施形態の欄で説明した思想(特性調整部に含まれる内部電極層を3層又は4層とする思想や、特性調整部に含まれる内部電極層の向きを変える思想や、特性調整部に含まれる内部電極層の対向面積を減少させる思想)を適宜採用しても良い。また、図9に示した積層セラミックコンデンサ10-6に、第5実施形態の欄で説明した思想(電歪緩和部11cを低誘電率化する思想)を採用しても良い。   In the laminated ceramic capacitor 10-6 shown in FIG. 9, the idea described in the section of the second to fourth embodiments (the idea that the internal electrode layer included in the characteristic adjusting portion is three or four layers, or the characteristic) The idea of changing the orientation of the internal electrode layer included in the adjustment unit, or the idea of reducing the facing area of the internal electrode layer included in the characteristic adjustment portion may be adopted as appropriate. Further, the concept described in the section of the fifth embodiment (thought to reduce the dielectric constant of the electrostriction alleviating portion 11c) may be adopted for the laminated ceramic capacitor 10-6 shown in FIG.

《第7実施形態》
図10は本発明を適用した積層セラミックコンデンサ10-7(第7実施形態)を示す。この積層セラミックコンデンサ10-7は、図1及び図2に示した積層セラミックコンデンサ10-1(第1実施形態)と、第1保護部11a-7と第2保護部11e-7が、容量部11bに含まれる23層のセラミック層11b2、電歪緩和部11c及び特性調整部11dに含まれる1層のセラミック層11d2と組成を異する低誘電率のセラミックスから成る点で異なる。
Seventh Embodiment
FIG. 10 shows a laminated ceramic capacitor 10-7 (seventh embodiment) to which the present invention is applied. In this laminated ceramic capacitor 10-7, the laminated ceramic capacitor 10-1 (first embodiment) shown in FIG. 1 and FIG. 2 and the first protective portion 11a-7 and the second protective portion 11e-7 It differs from the ceramic layer 11b of 23 layers included in 11b, the ceramic layer 11d of one layer included in the electrostriction alleviation portion 11c, and the characteristic adjustment portion 11d and in the point of being composed of low dielectric constant ceramics different in composition.

この積層セラミックコンデンサ10-7は、第1実施形態の欄で説明した好ましい製造例におけるシート作製工程で第1グリーンシートと組成を異する低誘電率の第4グリーンシートを作製し、積層工程で第1保護部11a-7と第2保護部11e-7を作製する際に第4グリーンシートから打ち抜いた単位シートを積み重ねて熱圧着することによって製造することができる。第4グリーンシートの作製例については第5実施形態の欄で述べた通りであるため、その説明を省略する。因みに、この積層セラミックコンデンサ10-7の好ましい実装例及び実装構造は、第1実施形態の欄で説明した実装例及び実装構造(図3を参照)と同じである。   This multilayer ceramic capacitor 10-7 produces a low dielectric constant fourth green sheet having a composition different from that of the first green sheet in the sheet producing step in the preferred production example described in the section of the first embodiment, and When producing 1st protection part 11a-7 and 2nd protection part 11e-7, it can manufacture by laminating | stacking and thermocompression-bonding the unit sheet punched out from the 4th green sheet. The production example of the fourth green sheet is as described in the section of the fifth embodiment, and thus the description thereof is omitted. Incidentally, the preferred mounting example and mounting structure of the multilayer ceramic capacitor 10-7 are the same as the mounting example and mounting structure (see FIG. 3) described in the section of the first embodiment.

図10に示した積層セラミックコンデンサ10-7は、第1保護部11a-7と第2保護部11e-7の誘電率が、容量部11bに含まれる23層のセラミック層11b2、電歪緩和部11c及び特性調整部11dに含まれる1層のセラミック層11d2の誘電率よりも低いため、実装状態における電圧印加時において第1保護部11a-7と第2保護部11e-7に生じ得る電歪を極力低減して、所期の音鳴き抑制を確実に行うことができる。他の効果は図1及び図2に示した積層セラミックコンデンサ10-1によって得られる効果と同様であるため、その説明を省略する。   In the multilayer ceramic capacitor 10-7 shown in FIG. 10, the dielectric constant of the first protective portion 11a-7 and the second protective portion 11e-7 is the ceramic layer 11b2 of 23 layers included in the capacitor portion 11b, and the electrostrictive relaxation portion Electrostriction that may occur in the first protective portion 11a-7 and the second protective portion 11e-7 at the time of voltage application in the mounted state, since the dielectric constant of the ceramic layer 11d2 included in the layer 11c and the characteristic adjusting portion 11d is lower Can be reduced as much as possible, and the desired noise suppression can be reliably performed. The other effects are the same as the effects obtained by the laminated ceramic capacitor 10-1 shown in FIGS. 1 and 2, and thus the description thereof is omitted.

尚、図10に示した積層セラミックコンデンサ10-7に、第2〜第4実施形態の欄で説明した思想(特性調整部に含まれる内部電極層を3層又は4層とする思想や、特性調整部に含まれる内部電極層の向きを変える思想や、特性調整部に含まれる内部電極層の対向面積を減少させる思想)を適宜採用しても良い。また、図10に示した積層セラミックコンデンサ10-7に、第5及び第6実施形態の欄で説明した思想(電歪緩和部11cを低誘電率化する思想や、特性調整部11dに含まれるセラミック層11d2を低誘電率化する思想)を適宜採用しても良い。   In the laminated ceramic capacitor 10-7 shown in FIG. 10, the idea described in the section of the second to fourth embodiments (the idea that the internal electrode layer included in the characteristic adjusting portion is three or four layers, or the characteristic) The idea of changing the orientation of the internal electrode layer included in the adjustment unit, or the idea of reducing the facing area of the internal electrode layer included in the characteristic adjustment portion may be adopted as appropriate. Further, the idea described in the fifth and sixth embodiments (into the idea of reducing the dielectric constant of the electrostriction alleviating portion 11c, and the characteristic adjusting portion 11d) of the multilayer ceramic capacitor 10-7 shown in FIG. The idea of lowering the dielectric constant of the ceramic layer 11d2 may be adopted as appropriate.

《他の実施形態》
(1)第1〜第7実施形態の欄及び図面には、コンデンサ本体11の容量部11bとして24層又は350層の内部電極層11b1を有するものを示したが、容量部11bに含まれる内部電極層11b1の層数に特段の制限は無い。
Other Embodiments
(1) In the columns and drawings of the first to seventh embodiments, the capacitor portion 11b of the capacitor main body 11 is shown to have the 24 or 350-layer internal electrode layer 11b1, but the inside included in the capacitor portion 11b There is no particular limitation on the number of electrode layers 11b1.

(2)第1〜第7実施形態の欄及び図面には、コンデンサ本体11として長さL>高さ>幅Wのものを例示したが、容量部11bに含まれる内部電極層11b1の層数等との関係から該容量部11bの厚さT2を薄くできる場合には、コンデンサ本体11を長さL>高さ=幅Wの条件、或いは、長さL>幅W>高さの条件を満足するものとすることもできる。   (2) In the columns and drawings of the first to seventh embodiments, the capacitor body 11 of length L> height> width W is exemplified, but the number of internal electrode layers 11b1 included in the capacitor portion 11b If the thickness T2 of the capacitor portion 11b can be reduced from the relationship with the etc., the condition of length L> height = width W or the condition of length L> width W> height is satisfied. It can also be satisfactory.

10-1,10-2,10-3,10-4,10-5,10-6,10-7…積層セラミックコンデンサ、11…コンデンサ本体、11a,11a-7…第1保護部、11b…容量部、11b1…内部電極層、11b2…セラミック層、11c,11c-5…電歪緩和部、11d,11d-2,11d-3,11d-4,11d-6…特性調整部、11d1,11d1’…内部電極層、11d2,11d2’…セラミック層、11e,11e-7…第2保護部、L…コンデンサ本体の長さ、W…コンデンサ本体の幅、H…コンデンサ本体の高さ、T1…第1保護部の厚さ、T2…容量部の厚さ、T3…電歪緩和部の厚さ、T4…特性調整部の厚さ、T5…第2保護部の厚さ。   10-1, 10-2, 10-3, 10-4, 10-5, 10-6, 10-7 ... laminated ceramic capacitors, 11 ... capacitor body, 11a, 11a-7 ... first protective portion, 11b ... Capacitance part, 11b1 ... internal electrode layer, 11b2 ... ceramic layer, 11c, 11c-5 ... electrostrictive relaxation part, 11d, 11d-2, 11d-3, 11d-4, 11d-6 ... characteristic adjustment part, 11d1, 11d1 Internal electrode layer 11d2, 11d2 'Ceramic layer 11e, 11e-7 Second protective portion L Length of capacitor body W Width of capacitor body H Height of capacitor body T1 T1 Thickness of first protective portion, T2: Thickness of capacitive portion, T3: Thickness of electrostrictive relaxation portion, T4: Thickness of characteristic adjustment portion, T5: Thickness of second protective portion.

Claims (12)

長さ、幅及び高さで規定された略直方体状のコンデンサ本体と、前記コンデンサ本体の長さ方向両端部に設けられた外部電極とを備えた積層セラミックコンデンサであって、
前記コンデンサ本体は、(1)セラミックス製の第1保護部と、(2)複数の内部電極層がセラミック層を介して積層された容量部と、(3)セラミックス製の電歪緩和部と、(4)複数の内部電極層がセラミック層を介して積層された特性調整部と、(5)セラミックス製の第2保護部と、が高さ方向に層状に並ぶように有しており、
前記容量部に含まれる複数の内部電極層の一部の端縁は前記外部電極の一方に電気的に接続され、且つ、残部の端縁は前記外部電極の他方に電気的に接続されており、
前記特性調整部に含まれる複数の内部電極層の一部の端縁は前記外部電極の一方に電気的に接続され、且つ、残部の端縁は前記外部電極の他方に電気的に接続されており、
前記容量部の厚さをT2とし、前記電歪緩和部の厚さをT3とし、前記特性調整部の厚さをT4としたとき、該T2、T3及びT4はT2>T3>T4の条件を満足しており、
前記第1保護部と前記容量部に含まれるセラミック層と前記電歪緩和部と前記特性調整部に含まれるセラミック層と前記第2保護部のうち、前記電歪緩和部は、前記第1保護部、前記容量部に含まれるセラミック層、前記特性調整部に含まれるセラミック層及び前記第2保護部と組成を異する低誘電率のセラミックスから成る、
積層セラミックコンデンサ。
A multilayer ceramic capacitor comprising a substantially rectangular parallelepiped capacitor body defined by a length, a width, and a height, and external electrodes provided at both ends in the lengthwise direction of the capacitor body,
The capacitor main body includes (1) a first protective portion made of ceramic, (2) a capacitance portion in which a plurality of internal electrode layers are stacked via the ceramic layer, and (3) an electrostrictive relaxation portion made of ceramic. (4) A characteristic adjustment section in which a plurality of internal electrode layers are stacked via a ceramic layer, and (5) a second protective section made of ceramic are arranged in layers in the height direction,
An edge of a portion of the plurality of inner electrode layers included in the capacitance portion is electrically connected to one of the outer electrodes, and an edge of the remaining portion is electrically connected to the other of the outer electrodes. ,
An edge of a part of the plurality of inner electrode layers included in the characteristic adjustment portion is electrically connected to one of the outer electrodes, and an edge of the remaining portion is electrically connected to the other of the outer electrodes. Yes,
Assuming that the thickness of the capacitance portion is T2, the thickness of the electrostriction alleviating portion is T3, and the thickness of the characteristic adjustment portion is T4, the conditions of T2, T3 and T4 satisfy T2>T3> T4. I am satisfied
Among the ceramic layer included in the first protective portion, the capacitor portion, the electrostrictive alleviating portion, the ceramic layer included in the characteristic adjusting portion, and the second protective portion, the electrostrictive alleviating portion is the first protective portion. Part, a ceramic layer included in the capacity part, a ceramic layer included in the characteristic adjustment part, and a low dielectric ceramic having a composition different from that of the second protective part
Multilayer ceramic capacitor.
長さ、幅及び高さで規定された略直方体状のコンデンサ本体と、前記コンデンサ本体の長さ方向両端部に設けられた外部電極とを備えた積層セラミックコンデンサであって、
前記コンデンサ本体は、(1)セラミックス製の第1保護部と、(2)複数の内部電極層がセラミック層を介して積層された容量部と、(3)セラミックス製の電歪緩和部と、(4)複数の内部電極層がセラミック層を介して積層された特性調整部と、(5)セラミックス製の第2保護部と、が高さ方向に層状に並ぶように有しており、
前記容量部に含まれる複数の内部電極層の一部の端縁は前記外部電極の一方に電気的に接続され、且つ、残部の端縁は前記外部電極の他方に電気的に接続されており、
前記特性調整部に含まれる複数の内部電極層の一部の端縁は前記外部電極の一方に電気的に接続され、且つ、残部の端縁は前記外部電極の他方に電気的に接続されており、
前記容量部の厚さをT2とし、前記電歪緩和部の厚さをT3とし、前記特性調整部の厚さをT4としたとき、該T2、T3及びT4はT2>T3>T4の条件を満足しており、
前記第1保護部と前記容量部に含まれるセラミック層と前記電歪緩和部と前記特性調整部に含まれるセラミック層と前記第2保護部のうち、前記特性調整部に含まれるセラミック層は、前記第1保護部、前記容量部に含まれるセラミック層、前記電歪緩和部及び前記第2保護部と組成を異にする低誘電率のセラミックスから成る、
積層セラミックコンデンサ。
A multilayer ceramic capacitor comprising a substantially rectangular parallelepiped capacitor body defined by a length, a width, and a height, and external electrodes provided at both ends in the lengthwise direction of the capacitor body,
The capacitor main body includes (1) a first protective portion made of ceramic, (2) a capacitance portion in which a plurality of internal electrode layers are stacked via the ceramic layer, and (3) an electrostrictive relaxation portion made of ceramic. (4) A characteristic adjustment section in which a plurality of internal electrode layers are stacked via a ceramic layer, and (5) a second protective section made of ceramic are arranged in layers in the height direction,
An edge of a portion of the plurality of inner electrode layers included in the capacitance portion is electrically connected to one of the outer electrodes, and an edge of the remaining portion is electrically connected to the other of the outer electrodes. ,
An edge of a part of the plurality of inner electrode layers included in the characteristic adjustment portion is electrically connected to one of the outer electrodes, and an edge of the remaining portion is electrically connected to the other of the outer electrodes. Yes,
Assuming that the thickness of the capacitance portion is T2, the thickness of the electrostriction alleviating portion is T3, and the thickness of the characteristic adjustment portion is T4, the conditions of T2, T3 and T4 satisfy T2>T3> T4. I am satisfied
Among the ceramic layer contained in the first protective portion, the capacitive portion, the ceramic layer contained in the electrostriction alleviating portion, the ceramic layer contained in the characteristic adjusting portion, and the ceramic layer contained in the characteristic adjusting portion of the second protective portion, The first protective portion, the ceramic layer included in the capacitive portion, and the low dielectric constant ceramic whose composition is different from that of the electrostriction alleviating portion and the second protective portion.
Multilayer ceramic capacitor.
長さ、幅及び高さで規定された略直方体状のコンデンサ本体と、前記コンデンサ本体の長さ方向両端部に設けられた外部電極とを備えた積層セラミックコンデンサであって、
前記コンデンサ本体は、(1)セラミックス製の第1保護部と、(2)複数の内部電極層がセラミック層を介して積層された容量部と、(3)セラミックス製の電歪緩和部と、(4)複数の内部電極層がセラミック層を介して積層された特性調整部と、(5)セラミックス製の第2保護部と、が高さ方向に層状に並ぶように有しており、
前記容量部に含まれる複数の内部電極層の一部の端縁は前記外部電極の一方に電気的に接続され、且つ、残部の端縁は前記外部電極の他方に電気的に接続されており、
前記特性調整部に含まれる複数の内部電極層の一部の端縁は前記外部電極の一方に電気的に接続され、且つ、残部の端縁は前記外部電極の他方に電気的に接続されており、
前記容量部の厚さをT2とし、前記電歪緩和部の厚さをT3とし、前記特性調整部の厚さをT4としたとき、該T2、T3及びT4はT2>T3>T4の条件を満足しており、
前記第1保護部と前記容量部に含まれるセラミック層と前記電歪緩和部と前記特性調整部に含まれるセラミック層と前記第2保護部のうち、前記電歪緩和部と前記特性調整部に含まれるセラミック層は、前記第1保護部、前記容量部に含まれるセラミック層及び前記第2保護部と組成を異にする低誘電率のセラミックスから成る、
積層セラミックコンデンサ。
A multilayer ceramic capacitor comprising a substantially rectangular parallelepiped capacitor body defined by a length, a width, and a height, and external electrodes provided at both ends in the lengthwise direction of the capacitor body,
The capacitor main body includes (1) a first protective portion made of ceramic, (2) a capacitance portion in which a plurality of internal electrode layers are stacked via the ceramic layer, and (3) an electrostrictive relaxation portion made of ceramic. (4) A characteristic adjustment section in which a plurality of internal electrode layers are stacked via a ceramic layer, and (5) a second protective section made of ceramic are arranged in layers in the height direction,
An edge of a portion of the plurality of inner electrode layers included in the capacitance portion is electrically connected to one of the outer electrodes, and an edge of the remaining portion is electrically connected to the other of the outer electrodes. ,
An edge of a part of the plurality of inner electrode layers included in the characteristic adjustment portion is electrically connected to one of the outer electrodes, and an edge of the remaining portion is electrically connected to the other of the outer electrodes. Yes,
Assuming that the thickness of the capacitance portion is T2, the thickness of the electrostriction alleviating portion is T3, and the thickness of the characteristic adjustment portion is T4, the conditions of T2, T3 and T4 satisfy T2>T3> T4. I am satisfied
Of the ceramic layer included in the first protective portion, the capacitive portion, the electrostrictive alleviating portion, the ceramic layer included in the characteristic adjusting portion, and the second protective portion, the electrostrictive alleviating portion and the characteristic adjusting portion The ceramic layer contained is made of a ceramic having a low dielectric constant different in composition from the first protective portion, the ceramic layer contained in the capacitive portion, and the second protective portion.
Multilayer ceramic capacitor.
前記第2保護部の厚さをT5としたとき、前記T2、T3及びT4と該T5はT2>T3>T5>T4の条件を満足している、
請求項1〜3の何れか1項に記載の積層セラミックコンデンサ。
When the thickness of the second protective portion is T5, the T2, T3 and T4 and the T5 satisfy the condition of T2>T3>T5> T4.
The multilayer ceramic capacitor according to any one of claims 1 to 3.
前記コンデンサ本体の高さをHとし、前記第2保護部の厚さをT5としたとき、前記T3及びT4と該H及びT5は0.25≦(T3+T4+T5)/H≦0.4の条件を満足している、
請求項1〜4の何れか1項に記載の積層セラミックコンデンサ。
Assuming that the height of the capacitor body is H and the thickness of the second protective portion is T5, the T3 and T4 and the H and T5 satisfy the condition of 0.25 ≦ (T3 + T4 + T5) /H≦0.4. Is pleased,
The multilayer ceramic capacitor according to any one of claims 1 to 4.
前記コンデンサ本体の幅をWとしたとき、前記T2、T3及びT4と該Wは(T2+T3+T4)>Wの条件を満足している、
請求項1〜5の何れか1項に記載の積層セラミックコンデンサ。
When the width of the capacitor body is W, the T2, T3 and T4 and the W satisfy the condition of (T2 + T3 + T4)> W,
The multilayer ceramic capacitor according to any one of claims 1 to 5.
前記第1保護部の厚さをT1とし、前記第2保護部の厚さをT5としたとき、該T1及びT5はT1≦T5の条件を満足している、
請求項1〜6の何れか1項に記載の積層セラミックコンデンサ。
When the thickness of the first protective portion is T1 and the thickness of the second protective portion is T5, the T1 and T5 satisfy the condition of T1 ≦ T5.
The multilayer ceramic capacitor according to any one of claims 1 to 6.
前記特性調整部に含まれる複数の内部電極層の数は少なくとも2層である、
請求項1〜7の何れか1項に記載の積層セラミックコンデンサ。
The number of the plurality of internal electrode layers included in the characteristic adjustment unit is at least two.
The multilayer ceramic capacitor according to any one of claims 1 to 7.
前記コンデンサ本体の長さをLとし、幅をWとし、高さをHとしたとき、該L、W及びHはL>H>Wの条件を満足している、
請求項1〜8の何れか1項に記載の積層セラミックコンデンサ。
When the length of the capacitor body is L, the width is W, and the height is H, the L, W and H satisfy the condition of L>H> W,
The multilayer ceramic capacitor according to any one of claims 1 to 8.
前記電歪緩和部を介して向き合う前記容量部の内部電極層の端縁と前記特性調整部の内部電極層の端縁は、前記外部電極の一方及び他方のうちの異なる側の外部電極にそれぞれ接続されている、
請求項1〜9の何れか1項に記載の積層セラミックコンデンサ。
The edge of the internal electrode layer of the capacitor and the edge of the internal electrode layer of the characteristic adjustment portion facing each other through the electrostriction alleviating portion are respectively connected to the external electrodes on one side and the other side of the external electrode. It is connected,
The multilayer ceramic capacitor according to any one of claims 1 to 9.
前記電歪緩和部を介して向き合う前記容量部の内部電極層の端縁と前記特性調整部の内部電極層の端縁は、前記外部電極の一方及び他方のうちの同じ側の外部電極に接続されている、
請求項1〜10の何れか1項に記載の積層セラミックコンデンサ。
The edge of the internal electrode layer of the capacitor and the edge of the internal electrode of the characteristic adjustment portion facing each other through the electrostriction alleviating portion are connected to the external electrode on one and the other of the external electrodes. Being
The multilayer ceramic capacitor according to any one of claims 1 to 10.
前記特性調整部に含まれる複数の内部電極層の対向面積は、前記容量部に含まれる複数の内部電極層の対向面積よりも小さい、
請求項1〜11の何れか1項に記載の積層セラミックコンデンサ。
The facing area of the plurality of internal electrode layers included in the characteristic adjusting unit is smaller than the facing area of the plurality of internal electrode layers included in the capacitor unit.
A multilayer ceramic capacitor according to any one of claims 1 to 11.
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