JPH06244050A - Manufacture of laminated ceramic capacitor and laminated green body therefor - Google Patents

Manufacture of laminated ceramic capacitor and laminated green body therefor

Info

Publication number
JPH06244050A
JPH06244050A JP5026686A JP2668693A JPH06244050A JP H06244050 A JPH06244050 A JP H06244050A JP 5026686 A JP5026686 A JP 5026686A JP 2668693 A JP2668693 A JP 2668693A JP H06244050 A JPH06244050 A JP H06244050A
Authority
JP
Japan
Prior art keywords
dielectric
laminated
capacitor
ceramic
green body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5026686A
Other languages
Japanese (ja)
Inventor
Joji Koga
譲二 古賀
Yuichi Kumano
裕一 熊野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP5026686A priority Critical patent/JPH06244050A/en
Publication of JPH06244050A publication Critical patent/JPH06244050A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a method for manufacturing a laminated ceramic capacitor and laminated green body without increasing the number of processes in laminating wherein the thickness of the part where there are internal electrodes is almost equal to that of the part where no internal electrode exists and no delamination or degradation at thermal shock levels will occur. CONSTITUTION:The title ceramic capacitor is one with external electrodes 12 baked on the ends of a bare chip 11 obtained by firing a laminated green body. The laminated green body consists of a lower cover dielectric section 13 obtained by laminating a plurality of ceramic dielectric layers; capacitor section 14 obtained by alternately laminating ceramic dielectric layers 17 and internal electrodes 18 on the upper face of the dielectric section 13; and upper cover dielectric section 15 obtained by a plurality of ceramic dielectric layers on the upper face of the capacitor section. In addition a dielectric section 16 for correcting distortion in lamination, composed of ceramic dielectric layer 17 only, is placed within the laminated capacitor section 14.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は誘電体磁器組成物を用い
た積層セラミックコンデンサ及びその積層グリーン体の
製造方法に関する。更に詳しくは乾式積層法又は湿式積
層法に適用し得る積層グリーン体の製造方法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated ceramic capacitor using a dielectric ceramic composition and a method for producing a laminated green body thereof. More specifically, it relates to a method for producing a laminated green body that can be applied to a dry laminating method or a wet laminating method.

【0002】[0002]

【従来の技術】近年、ラジオ、マイクロカセットレコー
ダ、電子チューナ、ビデオカメラ等の超小型化、薄型軽
量電子機器の発展に伴い、回路素子として使用されるコ
ンデンサの小型、大容量化が強く要求されるようになっ
てきた。これらの要求を満足する部品として積層セラミ
ックコンデンサが知られている。この積層セラミックコ
ンデンサを製造するには、最初に、例えば誘電体磁器粉
末、有機バインダ、可塑剤及び有機溶剤を混合して誘電
体スラリーを調製し、このスラリーをドクターブレード
法、スクリーン印刷法等の手段によりシート化する。次
いでこの誘電体シートを複数枚積層して下カバー誘電体
部を形成し、この下カバー誘電体部の上面にセラミック
誘電体層と内部電極とを交互に積層してコンデンサ部を
形成する。ここで内部電極は誘電体シートで作られたセ
ラミック誘電体層の上面に間隔をあけて導電性ペースト
をスクリーン印刷し乾燥して形成される。次にコンデン
サ部の上面に誘電体シートを複数枚積層して上カバー誘
電体部を形成する。下カバー誘電体部とコンデンサ部と
上カバー誘電体部をプレスして積層グリーン体にした
後、積層した内部電極の単位で積層グリーン体をチップ
状に切断する。続いてチップ体を脱バインダ処理した
後、焼成してベアチップとし、最後にベアチップの端面
に外部電極を形成する。
2. Description of the Related Art In recent years, with miniaturization of radios, microcassette recorders, electronic tuners, video cameras, etc., and development of thin and lightweight electronic equipment, there has been a strong demand for miniaturization and large capacity of capacitors used as circuit elements. It started to come. A monolithic ceramic capacitor is known as a component that satisfies these requirements. In order to manufacture this laminated ceramic capacitor, first, for example, a dielectric ceramic powder, an organic binder, a plasticizer and an organic solvent are mixed to prepare a dielectric slurry, and this slurry is subjected to a doctor blade method, a screen printing method or the like. A sheet is formed by means. Then, a plurality of the dielectric sheets are laminated to form a lower cover dielectric portion, and a ceramic dielectric layer and internal electrodes are alternately laminated on the upper surface of the lower cover dielectric portion to form a capacitor portion. Here, the internal electrodes are formed by screen-printing a conductive paste on the upper surface of a ceramic dielectric layer made of a dielectric sheet with a gap and drying the paste. Next, a plurality of dielectric sheets are laminated on the upper surface of the capacitor section to form an upper cover dielectric section. After pressing the lower cover dielectric part, the capacitor part, and the upper cover dielectric part into a laminated green body, the laminated green body is cut into chips in units of the laminated internal electrodes. Subsequently, the chip body is subjected to binder removal processing, and then baked to form a bare chip, and finally an external electrode is formed on the end face of the bare chip.

【0003】一方、コンデンサの小型、大容量化の要求
は最近更に強く、この要求を満たすためには積層数の増
大や誘電体層の薄層化が必要不可欠である。しかし、上
記の方法により大容量の積層セラミックコンデンサを製
造した場合に、積層数が増大すると、図6に示すように
積層後において内部電極の厚さの関係から内部電極1を
形成している部分2の厚さaが内部電極1を形成してい
ない部分3の厚さbより大きくなる。この状態で加熱圧
着により多層に積層しようとすると、内部電極の形成部
分2の厚さaと形成していない部分3の厚さbの差によ
り内部電極の形成されていない部分3が圧力不足にな
る。このためその境界には歪みが生じ、層間の密着性が
劣り、焼成時に内部電極と誘電体層間で内部ストレスに
より剥離現象(デラミネーション)や微小クラック等の
欠陥が発生する場合がある。これらの欠陥は、コンデン
サを予熱なしではんだ槽に浸漬する程度のサーマルショ
ックを与えたときにコンデンサを劣化させ、また耐湿寿
命を短くしてコンデンサとしての信頼性を低下させる問
題点があった。
On the other hand, demands for miniaturization and large capacity of capacitors have been further strengthened recently, and in order to meet these demands, it is indispensable to increase the number of laminated layers and thin dielectric layers. However, when a large-capacity monolithic ceramic capacitor is manufactured by the above method, if the number of laminated layers increases, the portion where the internal electrode 1 is formed due to the thickness of the internal electrode after the lamination as shown in FIG. The thickness a of 2 becomes larger than the thickness b of the portion 3 where the internal electrode 1 is not formed. In this state, if the layers are laminated by thermocompression bonding, the pressure in the portion 3 where the internal electrode is not formed becomes insufficient due to the difference between the thickness a of the portion 2 where the internal electrode is formed and the thickness b of the portion 3 where the internal electrode is not formed. Become. Therefore, the boundary is distorted, the adhesion between the layers is poor, and defects such as peeling phenomenon (delamination) and minute cracks may occur between the internal electrodes and the dielectric layer during firing due to internal stress. These defects have a problem that the capacitor deteriorates when it is subjected to a thermal shock to the extent that it is immersed in a solder bath without preheating, and the moisture-proof life is shortened to lower the reliability of the capacitor.

【0004】この点を解決するため、コンデンサ部を形
成する際に、内部電極の上に重ねるセラミック誘電体シ
ートを内部電極の部分だけ打抜くか、或いはその部分だ
け薄くする方法が提案されている(特開昭53−423
53)。また図5に示すようにベースフィルム5上に導
電性ペーストを間隔をあけて印刷乾燥して複数の内部電
極6を形成し、このベースフィルム5上の内部電極6の
間及び内部電極6の端部に誘電体ペーストを印刷乾燥し
て内部電極の厚みと同程度の厚み調整用誘電体層7を形
成した後、厚み調整用誘電体層7及び内部電極6の上に
誘電体スラリーによる重ね用誘電体層8を形成する積層
セラミックコンデンサ用グリーンシートの製造方法が提
案されている(特開平3−74820)。上記製造方法
の場合に、導電性ペーストの印刷パターンと誘電体ペー
ストの印刷パターンは写真フィルムのネガティブとポジ
ティブの関係になる。
In order to solve this problem, there has been proposed a method of punching out only a portion of the internal electrode or thinning the portion of the ceramic dielectric sheet to be overlaid on the internal electrode when forming the capacitor portion. (JP-A-53-423
53). Further, as shown in FIG. 5, a conductive paste is printed and dried on the base film 5 at intervals to form a plurality of internal electrodes 6, and the internal electrodes 6 between the internal electrodes 6 and the ends of the internal electrodes 6 are formed. After the dielectric paste is printed and dried on the portion to form a thickness adjusting dielectric layer 7 having a thickness approximately equal to the thickness of the internal electrode, the dielectric slurry for thickness adjustment and the internal electrode 6 are overlaid with a dielectric slurry. A method for manufacturing a green sheet for a laminated ceramic capacitor, which forms the dielectric layer 8, has been proposed (JP-A-3-74820). In the case of the above manufacturing method, the printing pattern of the conductive paste and the printing pattern of the dielectric paste have a negative and positive relationship with the photographic film.

【0005】[0005]

【発明が解決しようとする課題】しかし、これらの方法
によれば、セラミック誘電体層と内部電極との境界部に
おけるストレスを緩和することができる反面、積層時の
工程数が増加し、現状設備を大幅に改造する必要があっ
た。特に、図5に示される方法は、誘電体スラリーと誘
電体ペーストは同一組成であるため、換言すれば誘電体
スラリーに含まれる有機バインダ及び溶剤と、誘電体ペ
ーストに含まれる有機バインダ及び溶剤とはそれぞれ同
一であって相溶性があるため、積層状態において誘電体
スラリーの溶剤は誘電体ペーストのバインダの一部を溶
解し、誘電体ペーストの溶剤も誘電体スラリーのバイン
ダの一部を溶解しやすい。その結果、厚み調整用誘電体
層7と重ね用誘電体層8が密着度が高まり、積層グリー
ン体の脱バインダ時に内部電極を形成した導電性ペース
トのバインダが脱しにくくなる。内部電極の脱バインダ
が妨げられると、脱バインダ時に発生した気泡が積層グ
リーン体の焼成後にそのままベアチップ内部に残り、デ
ラミネーション、クラック等が発生したり、コンデンサ
の耐熱衝撃性が低下するなどの問題が新たに起きる。
However, according to these methods, the stress at the boundary between the ceramic dielectric layer and the internal electrode can be relieved, but the number of steps for stacking is increased, and the existing equipment is used. Had to be significantly remodeled. Particularly, in the method shown in FIG. 5, since the dielectric slurry and the dielectric paste have the same composition, in other words, the organic binder and the solvent contained in the dielectric slurry, the organic binder and the solvent contained in the dielectric paste, Since they are the same and compatible with each other, the solvent of the dielectric slurry dissolves a part of the binder of the dielectric paste in the stacked state, and the solvent of the dielectric paste also dissolves a part of the binder of the dielectric slurry. Cheap. As a result, the degree of adhesion between the thickness adjusting dielectric layer 7 and the stacking dielectric layer 8 is increased, and the binder of the conductive paste on which the internal electrodes are formed is less likely to be removed when the binder is removed from the laminated green body. If the removal of the binder from the internal electrodes is disturbed, the bubbles generated during the removal of the binder will remain inside the bare chip as they are after firing the laminated green body, causing delamination, cracks, etc., and reducing the thermal shock resistance of the capacitor. Happens anew.

【0006】本発明の目的は、積層時の工程数を増加さ
せずに、積層後において電極層を形成している部分の厚
さが電極層を形成していない部分の厚さと同程度にな
り、積層グリーン体の脱バインダ時に内部電極の脱バイ
ンダを妨げず、デラミネーションやサーマルショックレ
ベルでの劣化を生じない積層セラミックコンデンサ及び
その積層グリーン体の製造方法を提供することにある。
An object of the present invention is to make the thickness of a portion where an electrode layer is formed after laminating to be approximately the same as the thickness of a portion where an electrode layer is not formed, without increasing the number of steps during lamination. An object of the present invention is to provide a laminated ceramic capacitor and a method for manufacturing the laminated green body, which does not hinder the removal of the binder from the internal electrodes when the binder is removed from the laminated green body and does not cause deterioration at the delamination or thermal shock level.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、図1及び図2に示すように、本発明の積層セラミッ
クコンデンサ10は、積層グリーン体20を焼成してな
るベアチップ11と、このベアチップ11の端面に焼付
けられた外部電極12とを備え、この積層グリーン体が
複数のセラミック誘電体層を積層してなる下カバー誘電
体部13と、この下カバー誘電体部13の上面に形成さ
れセラミック誘電体層17と内部電極18とを交互に積
層してなるコンデンサ部14と、このコンデンサ部14
の上面に形成され複数のセラミック誘電体層を積層して
なる上カバー誘電体部15とを備える。その特徴ある構
成は、コンデンサ部14の積層内部にセラミック誘電体
層17のみからなる積層歪み調整用誘電体部16が1又
は2以上設けられたことにある。
In order to achieve the above object, as shown in FIGS. 1 and 2, a monolithic ceramic capacitor 10 of the present invention comprises a bare chip 11 formed by firing a laminated green body 20, and An external electrode 12 burned on the end surface of the bare chip 11 is provided, and the laminated green body is formed on the lower cover dielectric portion 13 formed by laminating a plurality of ceramic dielectric layers, and on the upper surface of the lower cover dielectric portion 13. A capacitor portion 14 formed by alternately laminating the ceramic dielectric layers 17 and the internal electrodes 18, and the capacitor portion 14
And an upper cover dielectric portion 15 formed on the upper surface of the above by laminating a plurality of ceramic dielectric layers. The characteristic configuration is that one or more dielectric strain adjusting dielectric portions 16 made of only the ceramic dielectric layer 17 are provided inside the capacitor portion 14.

【0008】また、本発明の乾式法による積層グリーン
体の製造方法は、図4に示すように誘電体スラリーを成
膜乾燥してなるセラミックグリーンシート17を繰返し
積層して下カバー誘電体部13を形成する工程と、この
下カバー誘電体部13の上面にグリーンシートのセラミ
ック誘電体層17とこの誘電体層の上面に導電性ペース
トを間隔をあけて印刷乾燥してなる内部電極18とを交
互に積層してコンデンサ部14を形成する工程と、この
コンデンサ部14の上面にグリーンシート17を繰返し
積層して上カバー誘電体部15を形成する工程とを含
む。その特徴ある構成は、コンデンサ部14の形成工程
において、所定数のセラミック誘電体層17と内部電極
18とを交互に積層し、この積層体の上面にグリーンシ
ートのセラミック誘電体層17のみを繰返し積層して積
層歪み調整用誘電体部16を形成し、この積層歪み調整
用誘電体部16の上面に所定数のセラミック誘電体層1
7と内部電極18とを交互に積層することにある。図4
に示すように、下カバー誘電体部13、コンデンサ部1
4、積層歪み調整用誘電体部16、コンデンサ部14及
び上カバー誘電体部15は上プレス21と下プレス22
により圧着され、積層グリーン体20になる。
In the method of manufacturing a laminated green body according to the dry method of the present invention, the lower cover dielectric portion 13 is formed by repeatedly laminating ceramic green sheets 17 formed by film-forming and drying a dielectric slurry as shown in FIG. And a step of forming a green sheet ceramic dielectric layer 17 on the upper surface of the lower cover dielectric portion 13, and an internal electrode 18 formed by printing and drying a conductive paste on the upper surface of the dielectric layer at intervals. The method includes a step of alternately stacking to form the capacitor section 14, and a step of repeatedly stacking the green sheet 17 on the upper surface of the capacitor section 14 to form the upper cover dielectric section 15. Its characteristic configuration is that a predetermined number of ceramic dielectric layers 17 and internal electrodes 18 are alternately laminated in the step of forming the capacitor section 14, and only the green sheet ceramic dielectric layers 17 are repeated on the upper surface of this laminated body. The lamination distortion adjusting dielectric portion 16 is formed by stacking, and a predetermined number of the ceramic dielectric layers 1 are formed on the upper surface of the lamination distortion adjusting dielectric portion 16.
7 and the internal electrodes 18 are alternately laminated. Figure 4
As shown in, the lower cover dielectric part 13 and the capacitor part 1
4, the dielectric distortion adjusting dielectric part 16, the capacitor part 14 and the upper cover dielectric part 15 are an upper press 21 and a lower press 22.
Then, the laminated green body 20 is obtained.

【0009】また、本発明の湿式法による積層グリーン
体の製造方法は、誘電体スラリーを繰返し塗布乾燥して
下カバー誘電体部13を形成する工程と、この下カバー
誘電体部13の上面に前記誘電体スラリーを塗布乾燥し
てなるセラミック誘電体層17とこの誘電体層の上面に
導電性ペーストを間隔をあけて印刷乾燥してなる内部電
極18とを交互に積層してコンデンサ部14を形成する
工程と、このコンデンサ部14の上面に前記誘電体スラ
リーを繰返し塗布乾燥して上カバー誘電体部15を形成
する工程とを含む。その特徴ある構成は、コンデンサ部
14の形成工程において、所定数のセラミック誘電体層
17と内部電極18とを交互に積層し、この積層体の上
面に前記誘電体スラリーのみを繰返し塗布乾燥して積層
歪み調整用誘電体部16を形成し、この積層歪み調整用
誘電体部16の上面に所定数のセラミック誘電体層17
と内部電極18とを交互に積層することにある。
The method for manufacturing a laminated green body according to the wet method of the present invention comprises a step of repeatedly applying and drying a dielectric slurry to form a lower cover dielectric portion 13, and a step of forming an upper surface of the lower cover dielectric portion 13. A ceramic dielectric layer 17 formed by applying and drying the dielectric slurry and an internal electrode 18 formed by printing and drying a conductive paste at intervals on the upper surface of the dielectric layer are alternately laminated to form a capacitor section 14. The process includes a step of forming the upper cover dielectric portion 15 by repeatedly applying and drying the dielectric slurry on the upper surface of the capacitor portion 14. Its characteristic configuration is that a predetermined number of ceramic dielectric layers 17 and internal electrodes 18 are alternately laminated in the step of forming the capacitor section 14, and only the dielectric slurry is repeatedly applied and dried on the upper surface of this laminated body. The dielectric distortion adjusting dielectric portion 16 is formed, and a predetermined number of ceramic dielectric layers 17 are formed on the upper surface of the dielectric distortion adjusting dielectric portion 16.
And the internal electrodes 18 are alternately laminated.

【0010】[0010]

【作用】コンデンサ部14の積層内部にセラミック誘電
体層17のみからなる積層歪み調整用誘電体部16を設
けることにより、図4に示した内部電極18が形成され
る部分の厚さと内部電極18が形成されない部分の厚さ
との差が減少する。これにより積層グリーン体20のセ
ラミック誘電体層と内部電極との境界部におけるストレ
スを緩和することができる。この積層歪み調整用誘電体
部16の数は、図1及び図2に示すような1つに限ら
ず、コンデンサ部15の内部電極18の積層数に応じ
て、2つ以上でもよい。また積層歪み調整用誘電体部1
6を構成するセラミック誘電体層17の数も内部電極1
8の積層数に応じて決められる。更に図1及び図2に示
すように、積層歪み調整用誘電体部16の上面及び下面
の内部電極18,18をベアチップ11の両端面に形成
された左右の外部電極12,12にそれぞれ接続して静
電容量を増やすように構成するばかりでなく、図3に示
すように、積層歪み調整用誘電体部16の上面及び下面
の内部電極18,18を一方の外部電極12に接続して
静電容量を増やさないように構成することもできる。
By providing the dielectric distortion adjusting dielectric portion 16 consisting only of the ceramic dielectric layer 17 inside the laminated portion of the capacitor portion 14, the thickness of the portion where the internal electrode 18 shown in FIG. The difference from the thickness of the part where no ridge is formed is reduced. Thereby, the stress at the boundary between the ceramic dielectric layer of the laminated green body 20 and the internal electrode can be relieved. The number of the dielectric distortion adjusting dielectric portions 16 is not limited to one as shown in FIGS. 1 and 2, and may be two or more depending on the number of laminated internal electrodes 18 of the capacitor portion 15. Also, the dielectric portion 1 for adjusting the stacking distortion
The number of ceramic dielectric layers 17 constituting 6 is also the internal electrode 1
It is determined according to the number of laminated layers of 8. Further, as shown in FIGS. 1 and 2, the internal electrodes 18 and 18 on the upper and lower surfaces of the dielectric distortion adjusting dielectric portion 16 are connected to the left and right external electrodes 12 and 12 formed on both end surfaces of the bare chip 11, respectively. In addition to increasing the capacitance by increasing the capacitance, the internal electrodes 18, 18 on the upper and lower surfaces of the dielectric distortion adjusting dielectric portion 16 are connected to one external electrode 12 as shown in FIG. It can also be configured so as not to increase the capacitance.

【0011】[0011]

【実施例】次に本発明の実施例を比較例とともに説明す
る。本発明はこの実施例に限定されるものではない。 <実施例>鉛系誘電体粉末[Pb(Mg1/3Nb2/3)O
3]を主成分とする誘電体材料をポリビニルブチラール
樹脂、フタル酸ジブチル、トルエン、エチルアルコール
からなる樹脂溶液中に加えて、ボールミルにより粉砕混
練し、誘電体スラリーを調製した。このスラリーを40
0メッシュのふるいに通して65cmHgの真空圧で脱
泡した。次いでドクターブレード法によりこのスラリー
を成膜乾燥して厚さ25μmのセラミックグリーンシー
トを作製し、たて200mm×よこ200mmの大きさ
に切断した。このグリーンシートは図4に示す下カバー
誘電体部13、コンデンサ部14のセラミック誘電体
層、積層歪み調整用誘電体部16及び上カバー誘電体部
15を形成するために用いられる。
EXAMPLES Next, examples of the present invention will be described together with comparative examples. The invention is not limited to this example. <Example> Lead-based dielectric powder [Pb (Mg 1/3 Nb 2/3 ) O
3 ] as a main component was added to a resin solution containing polyvinyl butyral resin, dibutyl phthalate, toluene and ethyl alcohol, and the mixture was pulverized and kneaded by a ball mill to prepare a dielectric slurry. 40 this slurry
It was degassed with a vacuum pressure of 65 cmHg through a 0 mesh sieve. Next, the slurry was formed into a film by a doctor blade method and dried to prepare a ceramic green sheet having a thickness of 25 μm, which was cut into a size of 200 mm × width 200 mm. This green sheet is used to form the lower cover dielectric portion 13, the ceramic dielectric layer of the capacitor portion 14, the stacking distortion adjusting dielectric portion 16 and the upper cover dielectric portion 15 shown in FIG.

【0012】即ち、図4に示すようにグリーンシート1
7を8層積み重ねて厚さ200μmの下カバー誘電体部
13を形成した。次いでこの誘電体部13の上面にグリ
ーンシート17と内部電極18を交互にそれぞれ26層
積み重ねてコンデンサ部14を形成した。内部電極18
はグリーンシート17の上面に導電性ペーストを所定の
矩形パターンで間隔をあけてスクリーン印刷し、乾燥し
て形成した。この例では内部電極の形状はたて1.3m
m×よこ3.1mmであって、1枚のグリーンシート1
7の上面に合計2964個形成した。導電性ペーストは
Ag/Pd=70/30のものを用いた。次にコンデン
サ部14の上面に内部電極を印刷しないグリーンシート
17のみを7層積み重ねて積層歪み調整用誘電体部16
を形成した後、この誘電体部16の上面に再度グリーン
シート17と内部電極18を交互にそれぞれ26層積み
重ねてコンデンサ部14を形成した。このコンデンサ部
14の上面にグリーンシート17を8層積み重ねて厚さ
200μmの上カバー誘電体部15を形成した。
That is, as shown in FIG. 4, the green sheet 1
8 layers 7 were stacked to form a lower cover dielectric portion 13 having a thickness of 200 μm. Next, 26 layers of green sheets 17 and internal electrodes 18 were alternately stacked on the upper surface of the dielectric portion 13 to form a capacitor portion 14. Internal electrode 18
Was formed by screen-printing a conductive paste in a predetermined rectangular pattern on the upper surface of the green sheet 17 at intervals and drying. In this example, the shape of the internal electrode is 1.3 m
m x width 3.1 mm, one green sheet 1
A total of 2964 pieces were formed on the upper surface of No. 7. The conductive paste used was Ag / Pd = 70/30. Next, 7 layers of only the green sheet 17 on which the internal electrodes are not printed are stacked on the upper surface of the capacitor section 14 to stack the dielectric distortion adjusting section 16
After forming the above, the green sheet 17 and the internal electrode 18 were alternately stacked again on the upper surface of the dielectric portion 16 to form 26 layers each to form the capacitor portion 14. Eight layers of green sheets 17 were stacked on the upper surface of the capacitor portion 14 to form an upper cover dielectric portion 15 having a thickness of 200 μm.

【0013】上記下カバー誘電体部13、コンデンサ部
14、積層歪み調整用誘電体部16、コンデンサ部14
及び上カバー誘電体部15を上プレス21と下プレス2
2により圧着して積層グリーン体20を作製した。この
ときの内部電極18の積層状況は、積層歪み調整用誘電
体部16の上下面の内部電極18,18の位置が互いに
ずれるようにした。続いて積層グリーン体20をたて
2.1mm×よこ4.0mmの大きさのチップ状に切断
した後、このチップ体を600℃で1時間加熱して脱バ
インダ処理し、更に1060℃で2時間焼成した。この
ベアチップをバレル研磨してその両端面に内部電極を露
出させた後、外部電極を形成して図1及び図2に示すよ
うなチップ型積層セラミックコンデンサ10を作製し
た。
The lower cover dielectric part 13, the capacitor part 14, the stacking distortion adjusting dielectric part 16, and the capacitor part 14.
And the upper cover dielectric portion 15 with the upper press 21 and the lower press 2
Then, the laminated green body 20 was manufactured by pressure bonding with 2. The lamination state of the internal electrodes 18 at this time was such that the positions of the internal electrodes 18, 18 on the upper and lower surfaces of the dielectric distortion adjusting dielectric portion 16 were displaced from each other. Subsequently, the laminated green body 20 is vertically cut into chips each having a size of 2.1 mm × horizontal 4.0 mm, and the chip bodies are heated at 600 ° C. for 1 hour to remove the binder, and further at 1060 ° C. for 2 hours. Burned for hours. This bare chip was barrel-polished to expose the internal electrodes on both end faces thereof, and then external electrodes were formed to fabricate a chip type monolithic ceramic capacitor 10 as shown in FIGS. 1 and 2.

【0014】<比較例>積層歪み調整用誘電体部16を
形成せず、また積層数を変えた以外は上記実施例と同一
のグリーンシート及び導電性ペーストを用いて、実施例
と同様にチップ型積層セラミックコンデンサを作製し
た。ここで下カバー誘電体部及び上カバー誘電体部はそ
れぞれグリーンシートを12層積み重ねて厚さ300μ
mにし、コンデンサ部はグリーンシートと内部電極をそ
れぞれ51層積み重ねた。
<Comparative Example> The same green sheet and conductive paste as in the above-described embodiment were used, except that the dielectric distortion adjusting dielectric portion 16 was not formed and the number of laminated layers was changed. A type monolithic ceramic capacitor was produced. Here, the lower cover dielectric part and the upper cover dielectric part each have 12 layers of green sheets stacked to have a thickness of 300 μm.
In the capacitor part, 51 layers of green sheets and internal electrodes were stacked.

【0015】<チップコンデンサの内部構造観察>実施
例と比較例のチップコンデンサの断面をそれぞれ20個
ずつ顕微鏡写真で観察したところ、コンデンサ部のセラ
ミック誘電体層と内部電極との境界部において比較例の
チップコンデンサが4個クラックが発生していたのに対
して、実施例のチップコンデンサには全くクラックが発
生していなかった。
<Observation of Internal Structure of Chip Capacitor> When 20 cross-sections of each of the chip capacitors of the example and the comparative example were observed with a micrograph, a comparative example was obtained at the boundary between the ceramic dielectric layer of the capacitor part and the internal electrode. 4 chip capacitors were cracked, whereas the chip capacitors of the examples were not cracked at all.

【0016】<サーマルショック試験>実施例と比較例
のチップコンデンサをサーマルショック試験によりそれ
ぞれ評価した。即ちチップコンデンサを1個ずつピンセ
ットでつかみ、これを予熱せずに300℃のSn63/
Pb37の共晶はんだ槽に3秒間浸漬した後、引上げ
た。実施例及び比較例のチップコンデンサをそれぞれ1
00個ずつ試験し、チップコンデンサにクラックが発生
しているか否かを顕微鏡で調べた。その結果、比較例の
チップコンデンサが3個クラックが発生していたのに対
して、実施例のチップコンデンサには全くクラックが発
生していなかった。また実施例のチップコンデンサは4
00℃のサーマルショック試験でもクラックは全く発生
しなかった。
<Thermal Shock Test> The chip capacitors of Examples and Comparative Examples were evaluated by a thermal shock test. That is, grab the chip capacitors one by one with tweezers and use Sn63 /
It was immersed in a eutectic solder bath of Pb37 for 3 seconds and then pulled up. Each of the chip capacitors of Examples and Comparative Examples is 1
It was tested by 00 pieces each, and it was examined by a microscope whether or not cracks were generated in the chip capacitor. As a result, the chip capacitors of the comparative example had three cracks, whereas the chip capacitors of the examples had no cracks at all. Also, the chip capacitor of the embodiment is 4
No cracks occurred at all in the thermal shock test at 00 ° C.

【0017】<耐湿負荷試験>実施例と比較例のチップ
コンデンサをそれぞれ20個ずつ耐湿負荷試験により評
価した。即ちチップコンデンサに対して+85℃の温度
で85%の相対湿度下、50Vの直流電圧を印加して1
000時間後の劣化の有無を調べた。比較例のチップコ
ンデンサは1000時間以内に5個不良が発生したのに
対して、実施例のチップコンデンサは1130時間にお
いても全く不良品は発生しなかった。
<Moisture Resistance Load Test> 20 chip capacitors of each of Examples and Comparative Examples were evaluated by a humidity resistance load test. That is, a DC voltage of 50 V is applied to the chip capacitor at a temperature of + 85 ° C. and a relative humidity of 85% to
The presence or absence of deterioration after 000 hours was examined. The chip capacitors of the comparative example had 5 defects within 1000 hours, whereas the chip capacitors of the examples did not have any defective products even after 1130 hours.

【0018】なお、上記例では乾式積層法によりグリー
ン体を作製したが、本発明の製造方法は、上記例に限ら
ず、湿式積層法にも適用することができる。
In the above example, the green body was manufactured by the dry laminating method, but the manufacturing method of the present invention is not limited to the above example, but can be applied to the wet laminating method.

【0019】[0019]

【発明の効果】以上述べたように、本発明によれば、コ
ンデンサ部の積層内部に内部電極を印刷形成しない積層
歪み調整用誘電体部を設けることにより、積層グリーン
体の内部電極が形成される部分の厚さと内部電極が形成
されない部分の厚さとの差が減少し、積層グリーン体に
成形したときの内部歪みが減少する。この結果、積層時
の工程数を増加させずに、積層グリーン体の脱バインダ
時に内部電極の脱バインダを妨げず、デラミネーション
やサーマルショックレベルでの劣化を生じず、信頼性の
高い積層セラミックコンデンサが得られる。
As described above, according to the present invention, the internal electrode of the laminated green body is formed by providing the laminated distortion adjusting dielectric portion in which the internal electrode is not formed by printing inside the laminated portion of the capacitor portion. The difference between the thickness of the portion where the internal electrode is not formed and the thickness of the portion where the internal electrode is not formed is reduced, and the internal strain when the green body is molded is reduced. As a result, a reliable multilayer ceramic capacitor that does not increase the number of steps during stacking, does not interfere with the removal of the internal electrodes during binder removal of the laminated green body, does not cause deterioration at delamination and thermal shock levels, and is highly reliable. Is obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】要部を断面で示す本発明の積層セラミックコン
デンサの斜視図。
FIG. 1 is a perspective view of a monolithic ceramic capacitor of the present invention showing a main part in cross section.

【図2】図1のA−A線断面図。FIG. 2 is a sectional view taken along line AA of FIG.

【図3】図2に対応する本発明の別の積層セラミックコ
ンデンサの断面図。
FIG. 3 is a sectional view of another monolithic ceramic capacitor of the present invention corresponding to FIG.

【図4】本発明の乾式積層法により積層グリーン体を積
層する状況を示す構成図。
FIG. 4 is a configuration diagram showing a situation in which laminated green bodies are laminated by the dry laminating method of the present invention.

【図5】従来の乾式積層法により積層するためのグリー
ン体の製造を説明する断面図。
FIG. 5 is a cross-sectional view illustrating the manufacture of a green body for stacking by a conventional dry stacking method.

【図6】従来の積層グリーン体の断面図。FIG. 6 is a cross-sectional view of a conventional laminated green body.

【符号の説明】[Explanation of symbols]

10 積層セラミックコンデンサ 11 ベアチップ 12 外部電極 13 下カバー誘電体部 14 コンデンサ部 15 上カバー誘電体部 16 積層歪み調整用誘電体部 17 セラミック誘電体層 18 内部電極 20 積層グリーン体 10 Multilayer Ceramic Capacitor 11 Bare Chip 12 External Electrode 13 Lower Cover Dielectric Part 14 Capacitor Part 15 Upper Cover Dielectric Part 16 Laminate Distortion Adjusting Dielectric Part 17 Ceramic Dielectric Layer 18 Internal Electrode 20 Multilayer Green Body

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 積層グリーン体(20)を焼成してなるベア
チップ(11)と、前記ベアチップ(11)の端面に焼付けられ
た外部電極(12)とを備え、 前記積層グリーン体(20)が複数のセラミック誘電体層を
積層してなる下カバー誘電体部(13)と、前記下カバー誘
電体部(13)の上面に形成されセラミック誘電体層(17)と
内部電極(18)とを交互に積層してなるコンデンサ部(14)
と、前記コンデンサ部(14)の上面に形成され複数のセラ
ミック誘電体層を積層してなる上カバー誘電体部(15)と
を備えた積層セラミックコンデンサにおいて、 前記コンデンサ部(14)の積層内部にセラミック誘電体層
のみからなる積層歪み調整用誘電体部(16)が1又は2以
上設けられたことを特徴とする積層セラミックコンデン
サ。
1. A bare chip (11) formed by firing a laminated green body (20), and an external electrode (12) baked on an end face of the bare chip (11), wherein the laminated green body (20) is A lower cover dielectric part (13) formed by laminating a plurality of ceramic dielectric layers, a ceramic dielectric layer (17) formed on the upper surface of the lower cover dielectric part (13), and an internal electrode (18). Capacitor parts that are laminated alternately (14)
And a top cover dielectric part (15) formed by stacking a plurality of ceramic dielectric layers formed on the upper surface of the capacitor part (14), wherein the inside of the capacitor part (14) is laminated. A monolithic ceramic capacitor, characterized in that one or two or more dielectric distortion adjusting dielectric parts (16) consisting only of a ceramic dielectric layer are provided.
【請求項2】 誘電体スラリーを成膜乾燥してなるセラ
ミックグリーンシート(17)を繰返し積層して下カバー誘
電体部(13)を形成する工程と、 前記下カバー誘電体部(13)の上面に前記グリーンシート
のセラミック誘電体層(17)とこの誘電体層の上面に導電
性ペーストを間隔をあけて印刷乾燥してなる内部電極(1
8)とを交互に積層してコンデンサ部(14)を形成する工程
と、 前記コンデンサ部(14)の上面に前記グリーンシート(17)
を繰返し積層して上カバー誘電体部(15)を形成する工程
とを含む積層グリーン体の製造方法において、 前記コンデンサ部(14)の形成工程では、所定数のセラミ
ック誘電体層(17)と内部電極(18)とを交互に積層し、こ
の積層体の上面に前記グリーンシートのセラミック誘電
体層(17)のみを繰返し積層して積層歪み調整用誘電体部
(16)を形成し、この積層歪み調整用誘電体部(16)の上面
に所定数のセラミック誘電体層(17)と内部電極(18)とを
交互に積層することを特徴とする積層グリーン体の製造
方法。
2. A step of repeatedly laminating ceramic green sheets (17) formed by film-forming and drying a dielectric slurry to form a lower cover dielectric part (13), and a step of forming the lower cover dielectric part (13). The ceramic dielectric layer (17) of the green sheet on the upper surface and the internal electrode (1) formed by printing and drying a conductive paste on the upper surface of the dielectric layer at intervals.
And 8) are alternately laminated to form the capacitor section (14), and the green sheet (17) is formed on the upper surface of the capacitor section (14).
In the method for manufacturing a laminated green body, which comprises repeatedly stacking to form the upper cover dielectric part (15), in the step of forming the capacitor part (14), a predetermined number of ceramic dielectric layers (17) and The internal electrodes (18) are alternately laminated, and only the ceramic dielectric layer (17) of the green sheet is repeatedly laminated on the upper surface of the laminated body to laminate lamination distortion adjusting dielectric portion.
(16) is formed, and a predetermined number of ceramic dielectric layers (17) and internal electrodes (18) are alternately laminated on the upper surface of the dielectric distortion adjusting dielectric portion (16) to form a laminated green. Body manufacturing method.
【請求項3】 誘電体スラリーを繰返し塗布乾燥して下
カバー誘電体部(13)を形成する工程と、 前記下カバー誘電体部(13)の上面に前記誘電体スラリー
を塗布乾燥してなるセラミック誘電体層(17)とこの誘電
体層の上面に導電性ペーストを間隔をあけて印刷乾燥し
てなる内部電極(18)とを交互に積層してコンデンサ部(1
4)を形成する工程と、 前記コンデンサ部(14)の上面に前記誘電体スラリーを繰
返し塗布乾燥して上カバー誘電体部(15)を形成する工程
とを含む積層グリーン体の製造方法において、 前記コンデンサ部(14)の形成工程では、所定数のセラミ
ック誘電体層(17)と内部電極(18)とを交互に積層し、こ
の積層体の上面に前記誘電体スラリーのみを繰返し塗布
乾燥して積層歪み調整用誘電体部(16)を形成し、この積
層歪み調整用誘電体部(16)の上面に所定数のセラミック
誘電体層(17)と内部電極(18)とを交互に積層することを
特徴とする積層グリーン体の製造方法。
3. A step of forming a lower cover dielectric part (13) by repeatedly applying and drying a dielectric slurry, and applying and drying the dielectric slurry on an upper surface of the lower cover dielectric part (13). A ceramic dielectric layer (17) and an internal electrode (18) formed by printing and drying a conductive paste at intervals on the upper surface of this dielectric layer are alternately laminated to form a capacitor section (1
In the method for manufacturing a laminated green body, which comprises the step of forming 4), and the step of forming the upper cover dielectric portion (15) by repeatedly applying and drying the dielectric slurry on the upper surface of the capacitor portion (14), In the step of forming the capacitor section (14), a predetermined number of ceramic dielectric layers (17) and internal electrodes (18) are alternately laminated, and only the dielectric slurry is repeatedly applied and dried on the upper surface of the laminated body. To form a dielectric distortion adjusting dielectric part (16), and a predetermined number of ceramic dielectric layers (17) and internal electrodes (18) are alternately laminated on the upper surface of the dielectric distortion adjusting dielectric part (16). A method of manufacturing a laminated green body, comprising:
JP5026686A 1993-02-16 1993-02-16 Manufacture of laminated ceramic capacitor and laminated green body therefor Pending JPH06244050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5026686A JPH06244050A (en) 1993-02-16 1993-02-16 Manufacture of laminated ceramic capacitor and laminated green body therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5026686A JPH06244050A (en) 1993-02-16 1993-02-16 Manufacture of laminated ceramic capacitor and laminated green body therefor

Publications (1)

Publication Number Publication Date
JPH06244050A true JPH06244050A (en) 1994-09-02

Family

ID=12200283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5026686A Pending JPH06244050A (en) 1993-02-16 1993-02-16 Manufacture of laminated ceramic capacitor and laminated green body therefor

Country Status (1)

Country Link
JP (1) JPH06244050A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212527A (en) * 2009-05-22 2009-09-17 Murata Mfg Co Ltd Method of manufacturing multilayer ceramic electronic capacitor
JP2010153935A (en) * 2010-04-09 2010-07-08 Murata Mfg Co Ltd Multilayered capacitor
JP2010177696A (en) * 2010-04-09 2010-08-12 Murata Mfg Co Ltd Multilayer capacitor
JP2015211210A (en) * 2014-04-30 2015-11-24 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component and method of manufacturing the same
JP2015226026A (en) * 2014-05-29 2015-12-14 太陽誘電株式会社 Multilayer ceramic capacitor
JP2018110250A (en) * 2018-02-15 2018-07-12 太陽誘電株式会社 Multilayer ceramic capacitor
JP2018110251A (en) * 2018-02-15 2018-07-12 太陽誘電株式会社 Multilayer ceramic capacitor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212527A (en) * 2009-05-22 2009-09-17 Murata Mfg Co Ltd Method of manufacturing multilayer ceramic electronic capacitor
JP2010153935A (en) * 2010-04-09 2010-07-08 Murata Mfg Co Ltd Multilayered capacitor
JP2010177696A (en) * 2010-04-09 2010-08-12 Murata Mfg Co Ltd Multilayer capacitor
JP2015211210A (en) * 2014-04-30 2015-11-24 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component and method of manufacturing the same
JP2015226026A (en) * 2014-05-29 2015-12-14 太陽誘電株式会社 Multilayer ceramic capacitor
JP2018110250A (en) * 2018-02-15 2018-07-12 太陽誘電株式会社 Multilayer ceramic capacitor
JP2018110251A (en) * 2018-02-15 2018-07-12 太陽誘電株式会社 Multilayer ceramic capacitor

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