JPH071790B2 - Method for manufacturing plug-in type semiconductor package - Google Patents
Method for manufacturing plug-in type semiconductor packageInfo
- Publication number
- JPH071790B2 JPH071790B2 JP60254188A JP25418885A JPH071790B2 JP H071790 B2 JPH071790 B2 JP H071790B2 JP 60254188 A JP60254188 A JP 60254188A JP 25418885 A JP25418885 A JP 25418885A JP H071790 B2 JPH071790 B2 JP H071790B2
- Authority
- JP
- Japan
- Prior art keywords
- external lead
- layer
- type semiconductor
- semiconductor package
- nickel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体素子を収納するプラグイン型半導体パッ
ケージの製造方法に関するものである。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a plug-in type semiconductor package that accommodates a semiconductor element.
（従来の技術） 従来、半導体素子、特に半導体集積回路素子を収納する
ためのプラグイン型半導体パッケージは第４図及び第５
図に示すようにセラミックス等の電気絶縁材料から成
り、その上面の略中央部に半導体素子を収納するための
凹部及び該凹部周辺から底面にかけて導出されたタング
ステン（Ｗ）、モリブデン（Mo）等の金属粉末から成る
メタライズ金属層12を有する絶縁基体11と、半導体素子
を外部回路に電気的に接続するための前記メタライズ金
属層12に銀ロウ等のロウ材16を介し取着された銅（Cu）
から成る多数の外部リードピン13と蓋体14とから構成さ
れており、その内部に半導体素子15が収納され、気密封
止されて半導体装置となる。(Prior Art) Conventionally, a plug-in type semiconductor package for accommodating a semiconductor element, particularly a semiconductor integrated circuit element, is shown in FIGS.
As shown in the figure, it is made of an electrically insulating material such as ceramics, and has a concave portion for accommodating a semiconductor element in the substantially central portion of its upper surface and tungsten (W), molybdenum (Mo), etc. led out from the periphery of the concave portion to the bottom surface. An insulating substrate 11 having a metallized metal layer 12 made of metal powder, and copper (Cu) attached to the metallized metal layer 12 for electrically connecting a semiconductor element to an external circuit via a brazing material 16 such as silver brazing. )
It is composed of a large number of external lead pins 13 and a lid body 14, in which a semiconductor element 15 is housed and hermetically sealed to form a semiconductor device.
この従来のプラグイン型半導体パッケージでは、外部リ
ードピン13と外部回路との電気的接続を良好となすため
に、また外部リードピン13及び該外部リードピン13を取
着するロウ材16が酸化腐蝕するのを防止するために通
常、前記外部リードピン13及びロウ材16の外表面にはニ
ッケル（Ni）及び金（Au）の良導電性で、耐蝕性に優れ
た金属から成る被覆層17が電解メッキ法もしくは無電解
メッキ法により被着されている。In this conventional plug-in type semiconductor package, in order to make good electrical connection between the external lead pin 13 and the external circuit, it is possible to prevent the external lead pin 13 and the brazing material 16 to which the external lead pin 13 is attached from being oxidized and corroded. In order to prevent this, normally, the outer lead pins 13 and the brazing material 16 have an outer surface coated with a coating layer 17 made of a metal having excellent conductivity such as nickel (Ni) and gold (Au) and excellent in corrosion resistance by an electroplating method or It is deposited by electroless plating.
（発明が解決しようとする問題点） しかし乍ら、この従来のプラグイン型半導体パッケージ
は、外部リードピンが銅（Cu）により形成されており、
銅（Cu）は極めて酸化され易い金属であることから、外
部リードピンに大気や大気中に含まれる水分等が接触す
ると該外部リードピンの表面には酸化被膜が容易に形成
されてしまう。そのためこの外部リードピンの外表面に
ニッケル（Ni）及び金（Au）をメッキ法により被着させ
た場合、外部リードピンはその表面に酸化被膜を有して
いることからメッキ金属層を強固に被着させることがで
きず、その結果、外部リードピンに半導体素子を取着収
納する際の熱や半導体素子が駆動した時に発生する熱等
が印加されるとメッキ金属層が外部リードピンの外表面
から剥離したり、接合部にフクレを発生し、外観不良を
生じるとともに外部リードピンの完全な酸化腐蝕の防止
ができないという欠点を有していた。(Problems to be solved by the invention) However, in this conventional plug-in type semiconductor package, the external lead pins are formed of copper (Cu),
Since copper (Cu) is a metal that is extremely easily oxidized, an oxide film is easily formed on the surface of the external lead pin when the external lead pin is brought into contact with the atmosphere or moisture contained in the atmosphere. Therefore, when nickel (Ni) and gold (Au) are deposited on the outer surface of this external lead pin by plating, the outer lead pin has an oxide film on its surface, so the plated metal layer is firmly deposited. As a result, the plating metal layer peels off from the outer surface of the external lead pin when heat is applied to the external lead pin when mounting or housing the semiconductor device or heat generated when the semiconductor device is driven. In addition, there is a drawback that blisters are generated at the joint portion, a poor appearance is caused, and complete oxidation and corrosion of the external lead pins cannot be prevented.
（発明の目的） 本発明は上記欠点に鑑み案出されたもので、その目的は
メッキ金属層の被着強度を大とし、外観不良を生じるこ
となく、外部リードピン及びロウ材の酸化腐蝕を完全に
防止することができるプラグイン型半導体パッケージの
製造方法を提供することにある。(Object of the invention) The present invention has been devised in view of the above-mentioned drawbacks, and its object is to increase the adhesion strength of the plated metal layer and to completely prevent the external lead pins and the brazing material from being oxidized and corroded without causing a defective appearance. Another object of the present invention is to provide a method of manufacturing a plug-in type semiconductor package that can prevent the above problems.
（問題点を解決するための手段） 本発明のプラグイン型半導体パッケージの製造方法は、
絶縁容器に設けたメタライズ金属層に、表面にニッケル
の保護層が焼付けられた銅から成る多数の外部リードピ
ンをロウ材を介して取着し、しかる後、前記少なくとも
外部リードピン及びロウ材の外表面をニッケル層で被覆
するとともに該ニッケル層表面を金属で被覆したことを
特徴とするものである。(Means for Solving Problems) A method for manufacturing a plug-in type semiconductor package of the present invention is
A large number of external lead pins made of copper having a nickel protective layer baked on the surface thereof are attached to the metallized metal layer provided on the insulating container via a brazing material, and thereafter, at least the outer surface of the external lead pin and the brazing material. Is coated with a nickel layer and the surface of the nickel layer is coated with a metal.
（実施例） 次に、本発明を添付の第１図乃至第３図に示す実施例に
基づき詳細に説明する。(Embodiment) Next, the present invention will be described in detail based on an embodiment shown in FIGS.
第１図及び第２図は本発明の製造方法によって作製され
たプラグイン型半導体パッケージの一実施例を示し、１
はアルミナセラミックス等の電気絶縁材料から成る絶縁
基体であり、２は同じく電気絶縁材料から成る蓋体であ
る。この絶縁基体１と蓋体２とで絶縁容器が構成され
る。1 and 2 show an embodiment of a plug-in type semiconductor package manufactured by the manufacturing method of the present invention.
Is an insulating base made of an electrically insulating material such as alumina ceramics, and 2 is a lid made of the same electrically insulating material. The insulating base 1 and the lid 2 constitute an insulating container.
前記絶縁基体１にはその上面中央部に半導体素子を収納
するための凹部が設けてあり、凹部底面には半導体素子
３が接着材を介して取着される。The insulating base 1 is provided with a recess for accommodating a semiconductor element in the center of its upper surface, and the semiconductor element 3 is attached to the bottom of the recess with an adhesive.
また前記絶縁基体１の凹部周辺部から底面にかけてメタ
ライズ金属層４が被着形成されており、メタライズ金属
層４の凹部周辺には半導体素子３の電極がワイヤ５を介
して電気的に接続され、また基体１底面部には外部リー
ドピン６がロウ材７を介しロウ付けされる。A metallized metal layer 4 is formed by depositing from the periphery of the recess to the bottom of the insulating substrate 1, and the electrode of the semiconductor element 3 is electrically connected to the periphery of the recess of the metallized metal layer 4 through a wire 5. External lead pins 6 are brazed to the bottom surface of the base body 1 via a brazing material 7.
前記絶縁基体１及びメタライズ金属層４は、例えばセラ
ミック生シートを複数枚準備し、それぞれの生シートの
上面及び生シートに形成し貫通孔内にタングステン等の
金属粉末から成るメタライズペーストを厚膜手法によっ
て印刷塗布し、しかる後、これらを積層するとともに焼
結一体化させることによって形成される。For the insulating substrate 1 and the metallized metal layer 4, for example, a plurality of ceramic green sheets are prepared, and a metallized paste made of a metal powder such as tungsten is formed in the through holes on the upper surface and the green sheet of each green sheet by a thick film method. It is formed by printing and coating by, and then laminating and sintering and integrating them.
前記絶縁基体１の底面に取着された外部リードピン６は
内部に収納される半導体素子３を外部回路と接続する作
用を為し、外部リードピン６を外部回路に設けたソケッ
ト等に挿入接続することによって内部に収納される半導
体素子３はメタライズ金属層４及び外部リードピン６を
介し外部回路と接続されることとなる。The external lead pin 6 attached to the bottom surface of the insulating substrate 1 has a function of connecting the semiconductor element 3 housed therein to an external circuit, and the external lead pin 6 is inserted and connected to a socket or the like provided in the external circuit. Thus, the semiconductor element 3 housed inside is connected to an external circuit through the metallized metal layer 4 and the external lead pins 6.
尚、前記外部リードピン６は銅（Cu）から成り、その外
表面にはニッケルから成る保護層6aが焼付けられてい
る。The external lead pin 6 is made of copper (Cu), and a protective layer 6a made of nickel is baked on the outer surface thereof.
また、前記外部リードピン６の外表面（実際には表面保
護層6aの外表面）及びロウ材７の外表面には外部リード
ピン６と外部回路との電気的接続を良好となすために、
また外部リードピン６及びロウ材７が酸化腐蝕するのを
防止するためにニッケル（Ni）層８と金（Cu）層９の二
層構造の被覆層10が従来周知の電解メッキ法もしくは無
電解メッキ法により被着されている。Further, in order to make good electrical connection between the external lead pins 6 and an external circuit on the outer surface of the external lead pins 6 (actually, the outer surface of the surface protection layer 6a) and the outer surface of the brazing material 7,
Further, in order to prevent the external lead pins 6 and the brazing material 7 from being oxidized and corroded, a coating layer 10 having a two-layer structure of a nickel (Ni) layer 8 and a gold (Cu) layer 9 is a conventionally known electrolytic plating method or electroless plating. Being applied by law.
かくして、このプラグイン型半導体パッケージによれ
ば、絶縁基体１の凹部底面に半導体素子３を取着固定す
るとともに該半導体素子３の各電極をワイヤ５によりメ
タライズ金属４に接続させた後、絶縁基体１と蓋体２と
をガラス、樹脂等の封止部材で取着させることによりそ
の内部に半導体素子３を気密に封止し、半導体装置とな
る。Thus, according to this plug-in type semiconductor package, the semiconductor element 3 is attached and fixed to the bottom surface of the recess of the insulating base 1 and each electrode of the semiconductor element 3 is connected to the metallized metal 4 by the wire 5, By attaching 1 and lid 2 with a sealing member such as glass or resin, semiconductor element 3 is hermetically sealed inside to form a semiconductor device.
次に、本発明のプラグイン型半導体パッケージの製造方
法について説明する。Next, a method of manufacturing the plug-in type semiconductor package of the present invention will be described.
第３図（ａ）〜（ｃ）は本発明のプラグイン型半導体パ
ッケージの製造方法の各工程毎の図である。FIGS. 3 (a) to 3 (c) are views of respective steps of the method for manufacturing the plug-in type semiconductor package of the present invention.
まず、銅（Cu）を従来周知の金属加工法により円柱状に
形成し、外部リードピン６を作製する。次に、この外部
リードピン６の外表面にニッケル（Ni）を、例えば電解
メッキ法により被着させるとともに600〜800℃の温度で
焼付け保護層6aを形成する〔第３図（ａ）〕。この保護
層6aは銅（Cu）から成る外部リードピン６の表面に酸化
被膜が形成されるのを防止する作用を為す。First, copper (Cu) is formed into a columnar shape by a conventionally known metal processing method, and the external lead pin 6 is manufactured. Next, nickel (Ni) is applied to the outer surface of the external lead pin 6 by, for example, an electrolytic plating method, and a baking protection layer 6a is formed at a temperature of 600 to 800 ° C. [FIG. 3 (a)]. The protective layer 6a has a function of preventing an oxide film from being formed on the surface of the external lead pin 6 made of copper (Cu).
前記保護層6aは、例えば硫酸ニッケル180〜300g/l、塩
化ニッケル30〜60g/l、ホウ酸20〜60g/l、から成るニッ
ケルメッキ浴中に外部リードピン６を浸漬するとともに
電流密度が２〜4A/dm2となるような電界を約３分間印加
し、外部リードピン６の外表面に約２μｍの厚みのニッ
ケルメッキ金属を析出被着させることによって形成され
る。The protective layer 6a is formed by immersing the external lead pin 6 in a nickel plating bath composed of, for example, nickel sulfate of 180 to 300 g / l, nickel chloride of 30 to 60 g / l, and boric acid of 20 to 60 g / l. It is formed by applying an electric field of 4 A / dm 2 for about 3 minutes and depositing and depositing a nickel-plated metal with a thickness of about 2 μm on the outer surface of the external lead pin 6.
次に、前記外表面ニッケル（Ni）から成る保護層6aを有
する外部リードピン６を絶縁基体１のメタライズ金属層
４にロウ材７を介して取着する〔第３図（ｂ）〕。この
時のロウ材７としては、例えば銀ロウ（銀−銅合金）が
使用され、メタライズ金属層４に銀ロウの薄板を介して
外部リードピン６を当接させ、しかる後、還元雰囲気
中、約850℃の温度に加熱し、銀ロウを溶融させること
によってメタライズ金属層４に外部リードピン６が取着
される。Next, the external lead pins 6 having the protective layer 6a made of nickel (Ni) on the outer surface are attached to the metallized metal layer 4 of the insulating substrate 1 through the brazing material 7 [FIG. 3 (b)]. As the brazing material 7 at this time, for example, silver brazing (silver-copper alloy) is used, and the external lead pin 6 is brought into contact with the metallized metal layer 4 via the thin plate of silver brazing, and then, in a reducing atmosphere, The external lead pins 6 are attached to the metallized metal layer 4 by heating to a temperature of 850 ° C. and melting the silver solder.
そして次に、前記外部リードピン６の表面（実際には保
護層6a表面）及びロウ材７表面に、例えば、電解メッキ
法によりニッケル層８と金層９の二層構造の被覆層10を
被着させ〔第３図（ｃ）〕、これによって第１図及び第
２図に示すプラグイン型半導体パッケージが完成する。Then, on the surface of the external lead pin 6 (actually the surface of the protective layer 6a) and the surface of the brazing material 7, a coating layer 10 having a two-layer structure of a nickel layer 8 and a gold layer 9 is deposited by, for example, an electrolytic plating method. Then, as shown in FIG. 3 (c), the plug-in type semiconductor package shown in FIGS. 1 and 2 is completed.
尚、前記被覆層10のうちニッケル層８はロウ材７と金層
９とがなじみが悪く、ロウ材７表面に直線金層９を強固
に被着できないこと、及び外部リードピン６の表面に保
護層6aを焼付けた際、外部リードピン６の一部が保護層
6aの表面に拡散析出し、これが金層９となじみが悪く、
金層９を直接被着させた場合、その被着強度が大きく低
下してしまうこと等から外部リードピン６及びロウ材７
表面に金層９を強固に被着させるために設けられた層で
あり、例えば外部リードピン６表面の保護層6aと同様の
メッキ浴を用いて電解メッキ法により外部リードピン６
表面（実際には保護層6a表面）及びロウ材７表面に被着
形成される。The nickel layer 8 of the coating layer 10 is not well compatible with the brazing material 7 and the gold layer 9 so that the linear gold layer 9 cannot be firmly adhered to the surface of the brazing material 7 and the surface of the external lead pin 6 is protected. When the layer 6a is baked, a part of the external lead pin 6 is a protective layer.
Diffusion-precipitated on the surface of 6a, which does not fit well with the gold layer 9,
When the gold layer 9 is directly applied, the adhesion strength of the gold layer 9 is greatly reduced.
This is a layer provided to firmly adhere the gold layer 9 on the surface, and for example, the external lead pin 6 is formed by electrolytic plating using the same plating bath as the protective layer 6a on the surface of the external lead pin 6.
It is deposited on the surface (actually the surface of the protective layer 6a) and the surface of the brazing material 7.
また、前記被覆層10のうち金層９は外部リードピン６と
外部回路との電気的絶縁を良好となすために、また外部
リードピン６及びロウ材７が酸化腐蝕するのを防止する
ために設けられた層であり、例えばシアン化第一金カリ
ウム６〜23.5g/l、リン酸一カリウム０〜90g/l、クエン
酸15〜90g/l、から成る金メッキ浴中に外部リードピン
６が取着された絶縁基体１を浸漬するとともに電流密度
が0.2〜1.0A/dm2となるような電界を約20分間印加する
ことによって外部リードピン６及びロウ材７表面に被着
したニッケル層８上に被着される。この金層９はニッケ
ル層８と極めてなじみが良いことからその被着強度は極
めて大となすことができる。In addition, the gold layer 9 of the coating layer 10 is provided for good electrical insulation between the external lead pins 6 and an external circuit, and for preventing the external lead pins 6 and the brazing material 7 from being oxidized and corroded. External lead pins 6 are attached to a gold plating bath consisting of, for example, 6 to 23.5 g / l potassium aluminium cyanide, 0 to 90 g / l monopotassium phosphate, and 15 to 90 g / l citric acid. By immersing the insulating substrate 1 and applying an electric field such that the current density becomes 0.2 to 1.0 A / dm 2 for about 20 minutes, the nickel layer 8 deposited on the surfaces of the external lead pins 6 and the brazing material 7 is deposited. To be done. Since the gold layer 9 has a very good affinity with the nickel layer 8, the adhesion strength thereof can be extremely high.
（発明の効果） かくして、本発明のプラグイン型半導体パッケージの製
造方法によれば酸化され易い銅（Cu）から成る外部リー
ドピンの表面をニッケルを焼付て成る保護層で保護した
ことから外部リードピンに大気や大気中に含まれる水分
等が接触したとしても酸化被悪を形成することは一切な
く、絶縁容器に設けたメタライズ金属層にロウ材を介し
て取着した後、外部リードピン及びロウ材の外表面にニ
ッケル（Ni）及び金（Au）等の良導電性で、耐蝕性に優
れた金属を被着したとしても、その被着強度を極めて大
となすことができ、外観不良や外部リードピンの酸化腐
蝕の原因となる被覆層の剥離やフクレを皆無となすこと
ができる。(Effect of the Invention) Thus, according to the method of manufacturing the plug-in type semiconductor package of the present invention, the surface of the external lead pin made of copper (Cu) which is easily oxidized is protected by the protective layer formed by baking nickel. Even if the atmosphere or moisture contained in the atmosphere comes into contact, it does not form an oxidative damage at all, and after attaching to the metallized metal layer provided in the insulating container via the brazing material, the external lead pins and brazing material Even if a metal with good conductivity such as nickel (Ni) and gold (Au) and excellent in corrosion resistance is deposited on the outer surface, the adhesion strength can be made extremely large, resulting in poor appearance and external lead pins. It is possible to eliminate the peeling of the coating layer and the blistering that cause the oxidative corrosion of the above.
第１図は本発明の製造方法によって作製されたプラグイ
ン型半導体パッケージの断面図、第２図は第１図の要部
拡大断面図、第３図（ａ）乃至（ｃ）は本発明の製造方
法を説明するための各工程毎の断面図、第４図は従来の
プラグイン型半導体パッケージの断面図、第５図は第４
図の要部拡大断面図である。 1:絶縁基体、2:蓋体 4:メタライズ金属層 6:外部リードピン、6a:保護層 7:ロウ材、8:ニッケル層 9:金層、10:被覆層FIG. 1 is a sectional view of a plug-in type semiconductor package manufactured by the manufacturing method of the present invention, FIG. 2 is an enlarged sectional view of an essential part of FIG. 1, and FIGS. 3 (a) to 3 (c) show the present invention. Sectional views of respective steps for explaining the manufacturing method, FIG. 4 is a sectional view of a conventional plug-in type semiconductor package, and FIG.
It is a principal part expanded sectional view of a figure. 1: Insulating substrate, 2: Lid 4: Metallized metal layer 6: External lead pin, 6a: Protective layer 7: Brazing material, 8: Nickel layer 9: Gold layer, 10: Cover layer
Claims (1)
面にニッケルの保護層が焼付けられた銅から成る多数の
外部リードピンをロウ材を介して取着し、しかる後、前
記少なくとも外部リードピン及びロウ材の外表面をニッ
ケル層、金層で順次、被覆することを特徴とするプラグ
イン型半導体パッケージの製造方法。1. A large number of external lead pins made of copper having a nickel protective layer baked on the surface thereof are attached to a metallized metal layer provided on an insulating container via a brazing material, and then at least the external lead pins and A method for manufacturing a plug-in type semiconductor package, characterized in that an outer surface of a brazing material is sequentially covered with a nickel layer and a gold layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60254188A JPH071790B2 (en) | 1985-11-12 | 1985-11-12 | Method for manufacturing plug-in type semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60254188A JPH071790B2 (en) | 1985-11-12 | 1985-11-12 | Method for manufacturing plug-in type semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62113457A JPS62113457A (en) | 1987-05-25 |
| JPH071790B2 true JPH071790B2 (en) | 1995-01-11 |
Family
ID=17261459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60254188A Expired - Lifetime JPH071790B2 (en) | 1985-11-12 | 1985-11-12 | Method for manufacturing plug-in type semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH071790B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01313969A (en) * | 1988-06-13 | 1989-12-19 | Hitachi Ltd | Semiconductor device |
| JP2967621B2 (en) * | 1991-08-27 | 1999-10-25 | 日本電気株式会社 | Method of manufacturing package for semiconductor device |
| US6835898B2 (en) | 1993-11-16 | 2004-12-28 | Formfactor, Inc. | Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures |
| US6336269B1 (en) * | 1993-11-16 | 2002-01-08 | Benjamin N. Eldridge | Method of fabricating an interconnection element |
| EP0792517B1 (en) * | 1994-11-15 | 2003-10-22 | Formfactor, Inc. | Electrical contact structures from flexible wire |
| US6727579B1 (en) | 1994-11-16 | 2004-04-27 | Formfactor, Inc. | Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures |
| JP4079527B2 (en) * | 1998-07-15 | 2008-04-23 | 富士通コンポーネント株式会社 | Partial plating method for lead pins |
| JP2003223945A (en) * | 2002-01-30 | 2003-08-08 | Tanaka Kikinzoku Kogyo Kk | LEAD PIN WITH Au-Ge SYSTEM BRAZING MATERIAL |
-
1985
- 1985-11-12 JP JP60254188A patent/JPH071790B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62113457A (en) | 1987-05-25 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |