JPS6158259A - Chip carrier - Google Patents
Chip carrierInfo
- Publication number
- JPS6158259A JPS6158259A JP17994684A JP17994684A JPS6158259A JP S6158259 A JPS6158259 A JP S6158259A JP 17994684 A JP17994684 A JP 17994684A JP 17994684 A JP17994684 A JP 17994684A JP S6158259 A JPS6158259 A JP S6158259A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- layer
- chip carrier
- metallized metal
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体素子、特に半導体集積回路素子を収納す
るＩＣパッケージに関し、より詳細には外部電気配線基
板の配線導体に外部す〜ド端・子を介することなく直接
ロウ付けし、これによって内部に収納する半導体素子を
外部電気回路と電気的に接続するように成したチップキ
ャリア（リードレスパッケージ）の改良ｌζ関するもの
である。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an IC package that houses a semiconductor device, particularly a semiconductor integrated circuit device, and more particularly relates to an IC package that houses a semiconductor device, particularly a semiconductor integrated circuit device. This invention relates to an improvement lζ of a chip carrier (leadless package) in which a semiconductor element housed inside is electrically connected to an external electric circuit by direct brazing without using a lead.
（従来の技術）
従来、半導体集積回路素子を収納するためのチップキャ
リアは第２図に示すようにセラミック、ガラス等の電気
絶縁材料から成り、その外局部、即ち側面及び底面に半
導体集積回路素子を外部電気回路に接続するためのタン
グステン図、モリブデン（ＭＯ）等の高融点金属粉末か
ら成るメタライズ金属層１２を形成した絶縁基体１１と
蓋体１３とから構成されており、絶縁基体１１と蓋体１
３から成る絶縁容器内部に集積回路素子１４が収納され
気密封止されて半導体装置となる。(Prior Art) Conventionally, a chip carrier for housing a semiconductor integrated circuit element is made of an electrically insulating material such as ceramic or glass, as shown in FIG. It is composed of an insulating base 11 and a lid 13 on which a metallized metal layer 12 made of high melting point metal powder such as tungsten and molybdenum (MO) is formed to connect the insulating base 11 and the lid to an external electric circuit. body 1
An integrated circuit element 14 is housed inside an insulating container consisting of 3 and hermetically sealed to form a semiconductor device.
この従来のチップキャリアは内部に収納した集積回路素
子１４を外部電気回路に接続するためにメタライズ金属
層１２の絶縁基体１１底面部が外部電気配線基板１５の
配線導体１６にロウ材１７を介しロウ付けされ、メタラ
イズ金属層１２の絶縁基体１１底面部にはその表面にロ
ウ付は強度を強固とするためのニッケル等の金属層がめ
っきにより被着されている。In this conventional chip carrier, in order to connect the integrated circuit element 14 housed inside to an external electrical circuit, the bottom surface of the insulating base 11 of the metallized metal layer 12 is connected to the wiring conductor 16 of the external electrical wiring board 15 via a brazing material 17. On the bottom surface of the insulating substrate 11 of the metallized metal layer 12, a metal layer of nickel or the like is plated to increase the strength by brazing.
（発明が解決しようとする問題点）
しかし乍ら、絶縁基体１１には直接めっきができないこ
と及びめっき液の循環が悪いこと等からメタライズ金属
層１２の側面で絶縁基体１１表面近傍部分にはニッケル
めっき層を被着させることができず、ニッケルめっき眉
と絶縁基体１１との間にわずかな間隙が形成される。そ
のためこの間隙の一部に大気中に含まれる水分等が付着
するとニッケルめっき層に酸素濃度の相違によるすきま
腐蝕作用を発生し、ニッケルめっき層に酸化物（錆）を
形成して変色させることがある。またこの酸化物は導電
性で、かつ拡散しやすいという性質を有していることか
ら多数のメタライズ金属！ｍ１２が近接して形成されて
いるチップキャリアにおいては前記錆の拡散により隣接
するメタライズ金属層１２間が短絡し、その結果、半導
体装置としての機能に支障を来たすという重大な欠点を
誘発する。(Problems to be Solved by the Invention) However, because the insulating substrate 11 cannot be directly plated and the circulation of the plating solution is poor, nickel is not applied to the side surface of the metallized metal layer 12 near the surface of the insulating substrate 11. The plating layer cannot be deposited, and a slight gap is formed between the nickel plating eyebrow and the insulating substrate 11. Therefore, if moisture contained in the atmosphere adheres to a part of this gap, crevice corrosion occurs in the nickel plating layer due to the difference in oxygen concentration, and oxides (rust) are formed on the nickel plating layer, causing discoloration. be. In addition, this oxide is conductive and easily diffused, so it is used as a metallization material for many people! In a chip carrier in which the metallized metal layers 12 are formed close to each other, the diffusion of the rust causes a short circuit between adjacent metallized metal layers 12, resulting in a serious drawback in that the function as a semiconductor device is impaired.
（発明の目的）
本発明者は上記欠点に鑑み種々の実験の結果、タングス
テンνす、モリブデン（Ｍｏ） 、マンガン（Ｍｎ）等
の高融点金属から成るメタライズ金属層表面１ζロウ材
（特に半田）と極めて反応性（濡れ性）の高い、化学的
に安定な白金（Ｐｔ） 、 パラジウム（ｐｉ）もし
くはそれらの合金を主成分とする金属層を形成しておく
と導電性の錆の発生を皆無とし、かつメタライズ金属層
とロウ材との濡れ性が著しく改善され、チップキャリア
の絶縁基体底面のメタライズ金属層を外部電気配線基板
の配線導体に強固にロウ付けし得ることを知見した。(Object of the Invention) In view of the above-mentioned drawbacks, the present inventor has conducted various experiments and found that the surface of a metallized metal layer made of a high melting point metal such as tungsten, molybdenum (Mo), manganese (Mn), etc. By forming a metal layer mainly composed of chemically stable platinum (Pt), palladium (pi), or their alloys, which have extremely high reactivity (wettability) with In addition, it has been found that the wettability between the metallized metal layer and the brazing material is significantly improved, and the metallized metal layer on the bottom surface of the insulating base of the chip carrier can be firmly brazed to the wiring conductor of the external electrical wiring board.
本発明は上記知見１ζ基づき、変色や半導体装置として
の機能に支障を来たすような導電性の錆の発生が皆無で
かつ外部電気配線基板の配線導体とのロウ付は強度が極
めて強固なチップキャリアを提供することをその目的と
するものである。The present invention is based on the above-mentioned knowledge 1ζ, and provides a chip carrier that is completely free of discoloration and conductive rust that may impede the function of a semiconductor device, and that has extremely strong brazing strength with wiring conductors of an external electrical wiring board. Its purpose is to provide.
（問題点を解決するための手段）
本発明は半導体素子を収納する絶縁容器の外局部に、半
導体素子と外部電気回路とを接続するためのメタライズ
金属層を形成したチップキャリアにおいて、前記メタラ
イズ金属層表面に白金、パラジウムもしくはそれらの合
金を主成分とする金属層を設けたことを特徴とするもの
である。(Means for Solving the Problems) The present invention provides a chip carrier in which a metallized metal layer for connecting the semiconductor element and an external electric circuit is formed on the outer part of an insulating container housing the semiconductor element. It is characterized in that a metal layer containing platinum, palladium, or an alloy thereof as a main component is provided on the surface of the layer.
（実施例）
次に本発明を第１図に示す実施例に基づき詳細に説明す
る。(Example) Next, the present invention will be described in detail based on an example shown in FIG.
第１図は本発明のチップキャリアの一実施例を示し、１
はセラミック、ガラス等の電気絶縁材料から成る絶縁基
体、２は同じく電気絶縁材料から成る蓋体である。この
絶縁基体１と蓋体２で半導体集積回路素子を収納する絶
縁容器を構成する。FIG. 1 shows an embodiment of the chip carrier of the present invention, 1
2 is an insulating base made of an electrically insulating material such as ceramic or glass, and 2 is a lid made of an electrically insulating material. This insulating base 1 and lid 2 constitute an insulating container for housing a semiconductor integrated circuit element.
前記絶縁基体１はその上面中央部に集積回路素子を収納
するための空所を形成する段状の凹部を有しており、凹
部底面には半導体集積回路素子５が接着材を介し取着さ
れている。The insulating substrate 1 has a stepped recess in the center of its upper surface that forms a space for accommodating an integrated circuit element, and a semiconductor integrated circuit element 5 is attached to the bottom of the recess through an adhesive. ing.
また前記絶縁基体１には凹部段状上面から側面を介し底
面にかけて導出しているメタライズ金属層３が形成され
ており、メタライズ金属層３の凹部段状上面部には集積
回路素子５の電極がワイヤ６を介し電気的に接続され、
またメタライズ金属層３の基体１底面部は外部電気配線
基板７の配線導体８番こ半田等のロウ材９を介しロウ付
けされる。Further, a metallized metal layer 3 is formed on the insulating substrate 1 and extends from the stepped top surface of the recess through the side surfaces and the bottom surface, and the electrodes of the integrated circuit element 5 are formed on the stepped top surface of the metallized metal layer 3. electrically connected via wire 6;
Further, the bottom surface of the base 1 of the metallized metal layer 3 is brazed to the wiring conductor No. 8 of the external electrical wiring board 7 through a solder material 9 such as solder.
前記メタライズ金属層３はタングステン（イ）、モリブ
デン（ＭＯ）等の高融点金属粉末から成り、従来周知の
スクリーン印刷等の厚膜手法を採用することにより絶縁
基体１の外周部に形成される。The metallized metal layer 3 is made of high melting point metal powder such as tungsten (A) and molybdenum (MO), and is formed on the outer periphery of the insulating substrate 1 by employing a conventional thick film technique such as screen printing.
また、前記メタライズ金属層３の基体１側底面部）ζは
白金（ｐｔ） 、パラジウム（Ｐｄ）もしくはそれらの
合金を主成分とする金属ｗＩ４がめつき等により被着形
成されており、金属層４は化学的に安定であることから
メタライズ金属層３の側面で、絶。Further, the metallized metal layer 3 (bottom surface part on the base 1 side) ζ is formed by plating or the like with a metal wI4 whose main component is platinum (pt), palladium (Pd), or an alloy thereof. Since it is chemically stable, it cannot be used on the sides of the metallized metal layer 3.
緑基体１の表面近傍部分に間隙を形成し、該間隙内に大
気中に含まれる水分等が付着したとしてもすきま腐蝕作
用を受けることはなく導電性の錆を発生することは一切
ない。またこの金属層４は半田等のロウ材と極めて反応
性（濡れ性）が良く、メタライズ金属層３を外部電気配
線基板７の配線導体８に強めて強固にロウ付けすること
も可能となる。A gap is formed in the vicinity of the surface of the green substrate 1, and even if moisture contained in the atmosphere adheres to the gap, the green substrate 1 will not be subjected to crevice corrosion and will not generate any conductive rust. Further, this metal layer 4 has extremely good reactivity (wettability) with a brazing material such as solder, and it becomes possible to braze the metallized metal layer 3 to the wiring conductor 8 of the external electrical wiring board 7 in a strong manner.
尚、前記白金（ｐｔ）等から成る金属層４はその層厚を
０．３〜３．０μｍとすると安価番こして、かつチップ
キャリア底面のメタライズ金属層を外部電気配線基板の
配線導体に強固にロウ付けすることができることがら層
厚を０．３〜３．０μｍの範囲とすることが好ましい、
。Note that the metal layer 4 made of platinum (PT) or the like is made to have a thickness of 0.3 to 3.0 μm, which makes it inexpensive and allows the metallized metal layer on the bottom of the chip carrier to be firmly attached to the wiring conductor of the external electrical wiring board. It is preferable that the layer thickness is in the range of 0.3 to 3.0 μm since it can be brazed to
.
また金属層４はメタライズ金属層３の側底面部全面に設
ける必要はなく外部電気配線基板７の配線導体８と対向
する底面部のみに形成してもよい。Further, the metal layer 4 does not need to be provided on the entire side bottom surface of the metallized metal layer 3, and may be formed only on the bottom surface of the external electrical wiring board 7 facing the wiring conductor 8.
前記絶縁基体１の上面にはセラミック、ガラス等の電気
絶縁材料から成る蓋体２がガラス、樹脂等の封止部材を
介して取着されており、これによってチップキャリア内
部の空所は外気から完全に気密に封止され最終製品であ
る半導体装置となる。A lid 2 made of an electrically insulating material such as ceramic or glass is attached to the upper surface of the insulating base 1 via a sealing member such as glass or resin, thereby sealing the cavity inside the chip carrier from outside air. Completely hermetically sealed, the final product is a semiconductor device.
か（シテ、本発明のチップキャリア蚤ζよれば絶縁容器
の外周部に形成したメタライズ金属層表面にロウ材と濡
れ性が良く、かつ化学的に安定な白金（Ｐｔ） 、パラ
ジウム（Ｐｄ）もしくはそれらの合金を主成分とする金
属層゛を設けたことにより、すきま腐蝕作用による変色
や半導体装置としての機能に支障を来たすような導電性
の錆の発生は皆無であり、メタライズ金属層と外部電気
配線基板の配線導体とのロウ付は強度も極めて強固と為
すことが可能となる。According to the chip carrier flea of the present invention, platinum (Pt), palladium (Pd), or palladium (Pd), which has good wettability with the brazing material and is chemically stable, is added to the surface of the metallized metal layer formed on the outer periphery of the insulating container. By providing a metal layer mainly composed of these alloys, there is no discoloration due to crevice corrosion or conductive rust that would impede the function of a semiconductor device, and the metallized metal layer and external It is possible to braze the wiring conductor of the electric wiring board with extremely strong strength.
（実験例）
次１ζ本発明の作用効果を下記に示す実験例に基づいて
説明する。(Experimental Example) Next, the effects of the 1ζ present invention will be explained based on the experimental example shown below.
まず、１０１角のアルミナから成る生セラミツク体ある
いはセラミック焼結体５０個の一生面にタングステン、
モリブデン、マンガン等から成るメタライズ用ペースト
を使用して長さ３．Ｑ ｍ 、幅３，０ＪＯＩ。First, tungsten was applied to the whole surface of 50 raw ceramic bodies or ceramic sintered bodies made of 101 square alumina.
Using a metallizing paste made of molybdenum, manganese, etc., length 3. Q m, width 3,0 JOI.
厚み２０μｍのパターンを印刷するとともにこれを還元
雰囲気（憲素−水素雰囲気）中、約１４００〜１６００
℃の温度で焼成し、セラミック体表面にメタライズ金属
層を被着させる。次に前記メタライズ金属層表面に白金
（Ｐｔ） 、パラジウム（Ｐｄ）もしくはそれらの合金
をめっきにより被着させ、表面に銅箔を張ったエポキシ
樹脂板に半田を介しロウ付けするとともにセラミック体
にロウ付は面１こ対し垂直方向の外力を加えて引張りテ
ストを行ないセラミック体がロウ付は部より剥れた個数
を調べた。A pattern with a thickness of 20 μm is printed and the pattern is heated to approximately 1400 to 1600 μm in a reducing atmosphere (hydrogen atmosphere).
C. to deposit a metallized metal layer on the surface of the ceramic body. Next, platinum (Pt), palladium (Pd), or an alloy thereof is deposited on the surface of the metallized metal layer by plating, and is brazed to an epoxy resin plate covered with copper foil via solder, and then brazed to the ceramic body. A tensile test was performed by applying an external force perpendicular to the soldered surface, and the number of pieces of ceramic body peeled off from the brazed surface was determined.
また同時にＭ工Ｌ −ＳＴＤ −８８３−１００４に規
定の温湿度サイクル試験を２４０時間（１０サイクル）
行ない、その後メタライズ金属層及びその表面に施こし
ためつき居を顕微鏡により観察し、変色しているものの
数を調べた。At the same time, the temperature and humidity cycle test specified in M Engineering L-STD-883-1004 was conducted for 240 hours (10 cycles).
The metallized metal layer and the holes formed on its surface were then observed under a microscope to determine the number of discolored ones.
尚、試料番号１１及び１２は本発明品と比較するための
比較試料であり、試料番号１１はメタライズ金属層上に
めっき金属層を被着させず直接エポキシ樹脂板の銅箔に
ロウ付けしたもの、また試料番号１２はメタライズ金属
層上に従来使用されているニッケルをめっきしたもので
ある。In addition, sample numbers 11 and 12 are comparative samples for comparison with the products of the present invention, and sample number 11 is a sample in which a plating metal layer is not deposited on the metallized metal layer and is brazed directly to the copper foil of the epoxy resin plate. , Sample No. 12 is a metallized metal layer plated with conventionally used nickel.
上記の結果を下表に示す。The above results are shown in the table below.
（発明の効果）
上記実験結果からも判るようにメタライズ金属層を直接
エポキシ樹脂板にロウ付けしたもの（試料番号１１ ）
はその接合強度が３ｋｇの引張りテストで全数剥れてし
まい、またメタライズ金属層表面にニッケルの金属層を
形成したもの（試料番号１２）はその接合強度は大であ
るものの錆の発生による変色率が６０％もあるのに対し
、本発明の金属層を使用したものは７ ｋｇの引張りテ
ストでも剥れはほとんどなく変色率も４％以下である。(Effect of the invention) As can be seen from the above experimental results, the metallized metal layer was brazed directly to the epoxy resin plate (sample number 11)
The bonding strength of all of the samples peeled off in a 3 kg tensile test, and the sample with a nickel metal layer formed on the surface of the metallized metal layer (sample number 12) had a high bonding strength, but the rate of discoloration due to rust was high. In contrast, those using the metal layer of the present invention hardly peeled off even in a 7 kg tensile test, and the discoloration rate was less than 4%.
よって、本発明のチップキャリアは半導体集積回路素子
を収納するＩＣパッケージとして極めて有用である。Therefore, the chip carrier of the present invention is extremely useful as an IC package for housing semiconductor integrated circuit elements.
尚、本発明は上述の実施例、実験例に限定されるもので
はなく、メタライズ金ＢＥ上に形成する金属層として白
金（ｐｔ） 、パラジウム（Ｐｄ）もしくはそれらの合
金の他に第三成分を添加することも可能であり、この場
合、前述の実験例と同等の効果を奏することを実験によ
り確認している。Note that the present invention is not limited to the above-mentioned embodiments and experimental examples, and the metal layer formed on the metallized gold BE may include platinum (pt), palladium (Pd), or an alloy thereof, as well as a third component. It is also possible to add it, and in this case, it has been experimentally confirmed that the same effect as the above-mentioned experimental example can be obtained.
第１図は本発明のチップキャリアの一実施例を示す断面
図、！８２図は従来のチップキャリアの断面図である。
１．１１・・・絶 縁 基 体
２．１３・・・蓋体
３．１２・・・メタライズ金属層
４ ・・・・・・・・・金 属 層７．１５・・・
外部電気回路基板
８．１６・・・配線導体
９．１７・・・ロ ウ 材FIG. 1 is a sectional view showing an embodiment of the chip carrier of the present invention. FIG. 82 is a sectional view of a conventional chip carrier. 1.11... Insulating base body 2.13... Lid body 3.12... Metallized metal layer 4... Metal layer 7.15...
External electric circuit board 8.16...Wiring conductor 9.17...Raw material
Claims (1)
子と外部電気回路とを接続するためのメタライズ金属層
を形成したチップキャリアにおいて、前記メタライズ金
属層表面に白金、パラジウムもしくはそれらの合金を主
成分とする金属層を設けたことを特徴とするチップキャ
リア。In a chip carrier in which a metallized metal layer for connecting the semiconductor element and an external electric circuit is formed on the outer periphery of an insulating container that houses a semiconductor element, the surface of the metallized metal layer is mainly composed of platinum, palladium, or an alloy thereof. A chip carrier characterized by being provided with a metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17994684A JPS6158259A (en) | 1984-08-28 | 1984-08-28 | Chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17994684A JPS6158259A (en) | 1984-08-28 | 1984-08-28 | Chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6158259A true JPS6158259A (en) | 1986-03-25 |
Family
ID=16074707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17994684A Pending JPS6158259A (en) | 1984-08-28 | 1984-08-28 | Chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6158259A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000054561A1 (en) * | 1999-03-08 | 2000-09-14 | Robert Bosch Gmbh | Method for improving the manufacturing safety of weld joints |
| US7253029B2 (en) | 2004-03-10 | 2007-08-07 | M/A-Com, Inc. | Non-magnetic, hermetically-sealed micro device package |
| JPWO2015016173A1 (en) * | 2013-07-29 | 2017-03-02 | 京セラ株式会社 | Wiring board, wiring board with leads, and electronic device |
-
1984
- 1984-08-28 JP JP17994684A patent/JPS6158259A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000054561A1 (en) * | 1999-03-08 | 2000-09-14 | Robert Bosch Gmbh | Method for improving the manufacturing safety of weld joints |
| US6488199B1 (en) | 1999-03-08 | 2002-12-03 | Robert Bosch Gmbh | Method for improving the manufacturing safety of weld joints |
| US7253029B2 (en) | 2004-03-10 | 2007-08-07 | M/A-Com, Inc. | Non-magnetic, hermetically-sealed micro device package |
| JPWO2015016173A1 (en) * | 2013-07-29 | 2017-03-02 | 京セラ株式会社 | Wiring board, wiring board with leads, and electronic device |
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