JPS63137574A - Surface covering structure for metallized metal layer - Google Patents
Surface covering structure for metallized metal layerInfo
- Publication number
- JPS63137574A JPS63137574A JP61283391A JP28339186A JPS63137574A JP S63137574 A JPS63137574 A JP S63137574A JP 61283391 A JP61283391 A JP 61283391A JP 28339186 A JP28339186 A JP 28339186A JP S63137574 A JPS63137574 A JP S63137574A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- metallized metal
- metallized
- base body
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 90
- 239000002184 metal Substances 0.000 title claims abstract description 90
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 31
- 229910052697 platinum Inorganic materials 0.000 claims description 14
- 229910017052 cobalt Inorganic materials 0.000 claims description 11
- 239000010941 cobalt Substances 0.000 claims description 11
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 abstract description 23
- 238000007747 plating Methods 0.000 abstract description 13
- 238000005219 brazing Methods 0.000 abstract description 12
- 230000007797 corrosion Effects 0.000 abstract description 11
- 238000005260 corrosion Methods 0.000 abstract description 11
- 238000007789 sealing Methods 0.000 abstract description 9
- 229910045601 alloy Inorganic materials 0.000 abstract description 5
- 239000000956 alloy Substances 0.000 abstract description 5
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 5
- 229910052721 tungsten Inorganic materials 0.000 abstract description 5
- 239000000843 powder Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- 229910015363 Au—Sn Inorganic materials 0.000 abstract 1
- 239000004859 Copal Substances 0.000 abstract 1
- 241000782205 Guibourtia conjugata Species 0.000 abstract 1
- 239000000945 filler Substances 0.000 abstract 1
- 239000011810 insulating material Substances 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 22
- 238000012360 testing method Methods 0.000 description 17
- 229910052759 nickel Inorganic materials 0.000 description 10
- 238000011156 evaluation Methods 0.000 description 9
- 239000000047 product Substances 0.000 description 9
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 7
- 238000005476 soldering Methods 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 238000002845 discoloration Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 150000004679 hydroxides Chemical class 0.000 description 4
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012777 electrically insulating material Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910000833 kovar Inorganic materials 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009429 electrical wiring Methods 0.000 description 2
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- GUBSQCSIIDQXLB-UHFFFAOYSA-N cobalt platinum Chemical compound [Co].[Pt].[Pt].[Pt] GUBSQCSIIDQXLB-UHFFFAOYSA-N 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000009863 impact test Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はメタライズ金属層の表面被覆構造に関し、より
詳細には半導体集積回路素子を収納する半導体素子収納
用パッケージや多層配線基板等の電子部品におけるメタ
ライズ金属層の表面被覆構造に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a surface coating structure of a metallized metal layer, and more particularly to electronic components such as semiconductor element storage packages for housing semiconductor integrated circuit elements and multilayer wiring boards. The present invention relates to a surface coating structure of a metallized metal layer.
従来、電子部品、例えば半導体集積回路素子を収納する
ためのり一ドレスパッケージ（チップキャリア）は第２
図に示すようにセラミック、ガラス等の電気絶縁材料か
ら成り、その上面に蓋体をロウ付けするための、また外
周部、即ち側面及び底面に半導体集積回路素子を外部電
気回路に接続するためのタングステン（讐）、モリブデ
ン（Ｍｏ）等の高融点金属粉末から成るメタライズ金属
層１２ａ。Conventionally, adhesive dress packages (chip carriers) for housing electronic components, such as semiconductor integrated circuit elements, have been
As shown in the figure, it is made of an electrically insulating material such as ceramic or glass, and the top surface is used to braze the lid, and the outer periphery, that is, the side and bottom surfaces are used to connect the semiconductor integrated circuit element to an external electric circuit. The metallized metal layer 12a is made of high melting point metal powder such as tungsten and molybdenum (Mo).
１２ｂを形成した絶縁基体１１と蓋体１３とから構成さ
れており、絶縁基体１１と蓋体１３から成る絶縁容器内
部に半導体集積回路素子１４を収納するとともに蓋体１
３を絶縁基体１１にロウ付けし絶縁容器の内部を気密封
止することによって半導体装置となる。The semiconductor integrated circuit element 14 is housed inside the insulating container made up of the insulating base 11 and the lid 13, and the lid 1
3 to the insulating substrate 11 and hermetically sealing the inside of the insulating container, a semiconductor device is obtained.
この従来のチップキャリアは内部に収納した半導体集積
回路素子１４を外部電気回路に接続するために絶縁基体
１１底面部のメタライズ金属層１２ｂは外部電気配線基
板１５の配線導体１６にロウ材１７を介しロウ付は取着
され、絶縁基体１１底面部のメタライズ金属層１２ｂに
はその表面にロウ付は強度を強固とするためのニッケル
（Ｎｉ）及び金（Ａｕ）から成る金属層がめっきにより
被覆されている。In this conventional chip carrier, in order to connect the semiconductor integrated circuit element 14 housed inside to an external electrical circuit, the metallized metal layer 12b on the bottom surface of the insulating base 11 is connected to the wiring conductor 16 of the external electrical wiring board 15 via a brazing material 17. The solder is attached, and the surface of the metallized metal layer 12b on the bottom of the insulating substrate 11 is coated with a metal layer made of nickel (Ni) and gold (Au) to strengthen the solder by plating. ing.
また同時に絶縁基体１１上面のメタライズ金属層１２ａ
にも蓋体１３のロウ付けを強固とし、絶縁容器の気密封
止を完全とするためにロウ材の濡れ性が良いニッケル（
Ｎｉ）及び金（Ａｕ）がめっきにより被覆されている。At the same time, the metallized metal layer 12a on the upper surface of the insulating base 11
In order to strengthen the soldering of the lid 13 and to completely seal the insulating container, nickel (nickel), which has good wettability with the brazing material, is used.
Ni) and gold (Au) are coated by plating.
しかしながら、絶縁基体１１には直接めっきができない
こと及びめっき液の循環が悪いこと等からメタライズ金
属層１２ａ、１２ｂの側面で絶縁基体１１表面近傍部分
にはニッケルめっき層を被覆させることができず、ニッ
ケルめっき層と絶縁基体１１との間にわずかな隙間が形
成される。そのためこの隙間の一部に大気中に含まれる
水分等が付着するとニッケルめっき層に酸素濃度の相違
に起因する隙間腐蝕作用を生じ、ニッケルめっき層に酸
化物（錆）や水酸化物を生成し変色させることがある。However, because the insulating substrate 11 cannot be directly plated and the circulation of the plating solution is poor, it is not possible to coat the side surfaces of the metallized metal layers 12a and 12b near the surface of the insulating substrate 11 with a nickel plating layer. A slight gap is formed between the nickel plating layer and the insulating base 11. Therefore, if moisture contained in the atmosphere adheres to a part of this gap, crevice corrosion occurs on the nickel plating layer due to the difference in oxygen concentration, and oxides (rust) and hydroxides are generated on the nickel plating layer. May cause discoloration.
更にこの酸化物（錆）及び水酸化物は導電性で、かつ拡
散し易いという性質を有することから、例えば多数のメ
タライズ金属層１２ｂが近接して形成されているチップ
キャリアにおいては前記酸化物（錆）や水酸化物の拡散
により隣接するメタライズ金属層１２ｂ間が短絡し、電
子部品としての機能に支障を来すという重大な欠点を誘
発する。Furthermore, since these oxides (rust) and hydroxides are conductive and easily diffused, for example, in a chip carrier in which a large number of metallized metal layers 12b are formed in close proximity, the oxides (rust) and hydroxides are conductive and easily diffused. Due to the diffusion of hydroxides and metallized metal layers 12b, a short circuit occurs between adjacent metallized metal layers 12b, causing a serious drawback in that the function as an electronic component is impaired.
そこで、かかる欠点を解消するために、メタライズ金属
層の表面に被覆されるニッケルの金属層に代えて、化学
的に安定で導電性の錆を発生することがなく、ロウ材と
極めて反応性（濡れ性）の良い白金、パラジウム（Ｐｄ
）もしくはそれらの合金を主成分とする金属層をめっき
により被覆させることを本出願人は先に提案した。Therefore, in order to eliminate such drawbacks, we replaced the nickel metal layer coated on the surface of the metallized metal layer with a chemically stable, conductive metal layer that does not generate rust and is highly reactive with the brazing metal. Platinum, palladium (Pd) with good wettability
) or an alloy thereof, was previously proposed by the applicant to be coated by plating.
しかしながら、上記白金、パラジウムもしくはそれらの
合金を主成分とする金属層を直接タングステン、モリブ
デン等の高融点金属粉末から成るメタライズ金属層上に
めっきにより形成すると、該めっき金属層における隙間
腐蝕作用は有効に防止し得る゛ものの、白金、パラジウ
ムもしくはそれらの合金を主成分とする金属は均一電着
性に劣ることからメタライズ金属層上に均一厚みに被覆
させることができず、そのため、めっき金属層に外部よ
り機械的な応力が印加されると該めっき金属層の一部が
メタライズ金属層より剥離し、これが半導体集積回路素
子の特性をチェックするバーンインテスト（半導体集積
回路素子に高温の熱履歴を加えて特性変化を調べるテス
ト）等を行った場合に助長されて、めっき金属層のうち
蓋体がロウ付けされる部位や外部電気回路の配線導体に
ロウ付けされる部位のものがメタライズ金属層より完全
に剥離してしまい、その結果、半導体装置の外部電気回
路への取着接続が不完全となったり、絶縁容器の気密封
止が破れるという問題を有していた。However, when a metal layer mainly composed of platinum, palladium, or an alloy thereof is formed by plating directly on a metallized metal layer made of high-melting point metal powder such as tungsten or molybdenum, the crevice corrosion effect in the plated metal layer is effective. However, metals mainly composed of platinum, palladium, or their alloys have poor uniform electrodepositivity and cannot be coated to a uniform thickness on the metallized metal layer. When mechanical stress is applied from the outside, part of the plated metal layer peels off from the metallized metal layer, and this causes a burn-in test (which applies high-temperature thermal history to the semiconductor integrated circuit element) to check the characteristics of the semiconductor integrated circuit element. Tests to investigate changes in properties (tests to investigate changes in characteristics) have shown that the parts of the plated metal layer to which the lid is brazed or the parts to be brazed to the wiring conductors of external electrical circuits are less likely to be present than the metallized metal layer. This completely peels off, resulting in problems such as incomplete attachment and connection of the semiconductor device to an external electric circuit, and the hermetic sealing of the insulating container being broken.
本発明は前記欠点に鑑み案出されたもので、その目的は
半導体集積回路素子をチェックするバーンインテスト等
を行ったとしても絶縁容器の気密封止が破れることがな
く、また半導体装置等の電子部品を外部電気回路に確実
に接続することが可能なメタライズ金属層の表面被覆構
造を提供することにある。The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to prevent the hermetic seal of the insulating container from being broken even when performing a burn-in test to check semiconductor integrated circuit elements, and to prevent electronic devices such as semiconductor devices from being broken. An object of the present invention is to provide a surface coating structure of a metallized metal layer that can reliably connect a component to an external electric circuit.
本発明は絶縁基体上のメタライズ金属層表面に、コバル
ト （Ｃｏ）を主成分とする第１の金属層と白金（Ｐｔ
）を主成分とする第２の金属層との少なくとも二層から
成る金属層を層着被覆したことを特徴とするものである
。The present invention includes a first metal layer containing cobalt (Co) as a main component and platinum (Pt) on the surface of a metallized metal layer on an insulating substrate.
) is characterized in that it is coated with a metal layer consisting of at least two layers including a second metal layer containing as a main component.
本発明においてメタライズ金属層表面に、コバルトを主
成分とする第１の金属層を設け、その上に白金を主成分
とする第２の金属層を層着被覆した場合、該コバルトは
メタライズ金属層及び白金を主成分とする金属層のいず
れとも密着六人として層着被覆することができ、かつニ
ッケルと比較して前記隙間腐蝕作用を受は難いという特
性を有し、更に化学的に安定な金属層を得ることができ
る。In the present invention, when a first metal layer containing cobalt as a main component is provided on the surface of the metallized metal layer, and a second metal layer containing platinum as a main component is coated thereon, the cobalt is added to the metallized metal layer. It has the property of being able to be coated in close contact with both platinum and platinum-based metal layers, and is less susceptible to the crevice corrosion than nickel, and is chemically stable. A metal layer can be obtained.
次に本発明を第１図に示す実施例に基づき詳細に説明す
る。Next, the present invention will be explained in detail based on the embodiment shown in FIG.
第１図は本発明のメタライズ金属層の表面被覆構造を説
明するためにチップキャリア（半導体集積回路素子を収
納するためのリードレスパッケージ）を例にとって示し
た要部拡大断面図である。FIG. 1 is an enlarged sectional view of a main part of a chip carrier (a leadless package for accommodating a semiconductor integrated circuit element) as an example to explain the surface coating structure of a metallized metal layer of the present invention.
図において、ｌはセラミック、ガラス等の電気絶縁材料
から成る絶縁基体、５は蓋体である。この絶縁基体１と
蓋体５で半導体集積回路素子６を収納する絶縁容器を構
成する。前記絶縁基体１はその上面中央部に半導体集積
回路素子６を収納するための空所を形成する段状の凹部
を有しており、凹部底面に半導体集積回路素子６が接着
材を介し取着されている。In the figure, 1 is an insulating base made of an electrically insulating material such as ceramic or glass, and 5 is a lid. This insulating base 1 and lid 5 constitute an insulating container in which a semiconductor integrated circuit element 6 is housed. The insulating substrate 1 has a stepped recess in the center of its upper surface forming a space for accommodating a semiconductor integrated circuit element 6, and the semiconductor integrated circuit element 6 is attached to the bottom of the recess through an adhesive. has been done.
また、前記絶縁基体１には凹部底面及び凹部段状上面か
ら側面を介し底面にかけてメタライズ金属層２が形成さ
れており、メタライズ金属層２の凹部段状上面部には半
導体集積回路素子６の電極がワイヤ７を介し電気的に接
続される。Further, a metallized metal layer 2 is formed on the insulating substrate 1 from the bottom surface of the recess and the stepped upper surface of the recess through the side surfaces and the bottom surface, and the electrodes of the semiconductor integrated circuit element 6 are formed on the stepped upper surface of the metallized metal layer 2. are electrically connected via wire 7.
前記メタライズ金属層２はタングステン、モリブデン等
の高融点金属粉末から成り、従来周知のスクリーン印刷
等の４膜手法を採用することによって絶縁基体ｌの外周
部に形成される。The metallized metal layer 2 is made of high melting point metal powder such as tungsten or molybdenum, and is formed on the outer periphery of the insulating substrate 1 by employing a conventional four-layer technique such as screen printing.
また、前記メタライズ金属Ｎ２の絶縁基体１凹部底面部
、段状上面部及び側底面部にはコバルトを主成分とする
第１の金属層３と白金を主成分とする第２の金属層４が
それぞれめっき等により層着されており、メタライズ金
属層２はコバルトを主成分とする金属層と白金を主成分
とする金属層の二層により被覆されている。Furthermore, a first metal layer 3 containing cobalt as a main component and a second metal layer 4 containing platinum as a main component are formed on the bottom surface of the recess, the stepped top surface and the side bottom surface of the insulating base 1 of the metallized metal N2. They are each layered by plating or the like, and the metallized metal layer 2 is covered with two layers: a metal layer containing cobalt as a main component and a metal layer containing platinum as a main component.
また、前記絶縁基体１の上面にはセラミック、ガラス等
の電気絶縁材料から成るシールリング８が取着されてお
り、該シールリング８の上面にはメタライズ金属層２ａ
が前記手法と同様の手法により形成され、その上面部に
はコバルトを主成分とする第１の金属層３ａと白金を主
成分とする第、２の金属層４ａが層着被覆されている。Further, a seal ring 8 made of an electrically insulating material such as ceramic or glass is attached to the upper surface of the insulating base 1, and a metallized metal layer 2a is attached to the upper surface of the seal ring 8.
is formed by a method similar to that described above, and its upper surface is coated with a first metal layer 3a containing cobalt as a main component and a second metal layer 4a containing platinum as a main component.
前記第２の金属層４ａ上にはコバール（Ｆｅ−Ｎｉ−Ｇ
ｏ金合金に金（Ａｕ）めっきを施した蓋体５が金（Ａｕ
）−スズ（Ｓｎ）合金のロウ材を介して取着されており
、これによりチップキャリア内部の空所は外気から完全
に気密に封止され最終製品である半導体装置となる。Kovar (Fe-Ni-G) is formed on the second metal layer 4a.
o The lid body 5 is made of gold alloy plated with gold (Au).
)-tin (Sn) alloy brazing material, and as a result, the space inside the chip carrier is completely hermetically sealed from the outside air, resulting in a semiconductor device as a final product.
かくして、本発明によれば絶縁容器の外周部及びシール
リングの上面部に形成したメタライズ金属層表面に密着
力が大であるコバルトを主成分とする金属層と化学的に
安定な白金を主成分とする金属層を少なくとも二層設け
たことにより、隙間腐蝕作用を受けることは勿論、メタ
ライズ金属層とめっき金属層の密着強度を大としてめっ
き金属層がメタライズ金属層より剥離するのを皆無とな
し、同時に絶縁基体と蓋体のロウ付は及び半導体装置と
外部電気配線基板とのロウ付けを極めて強固となすこと
ができる。Thus, according to the present invention, on the surface of the metallized metal layer formed on the outer periphery of the insulating container and the upper surface of the seal ring, a metal layer mainly composed of cobalt, which has a high adhesive strength, and a metal layer mainly composed of chemically stable platinum are formed. By providing at least two metal layers, not only will the metal layer not be subject to crevice corrosion, but the adhesion strength between the metallized metal layer and the plated metal layer will be increased, and the peeling of the plated metal layer from the metallized metal layer will be completely eliminated. At the same time, the soldering between the insulating base and the lid and the soldering between the semiconductor device and the external electrical wiring board can be made extremely strong.
尚、本発明は上述の実施例に限定されるものではなく、
例えばリード付きの半導体素子収納用パッケージや多層
配線基板等のメタライズ金属層を有する電子部品にも適
用することができる。It should be noted that the present invention is not limited to the above-mentioned embodiments,
For example, it can be applied to electronic components having metallized metal layers, such as semiconductor element storage packages with leads and multilayer wiring boards.
次に本発明の作用効果を以下に示す実験例に基づき説明
する。Next, the effects of the present invention will be explained based on the experimental examples shown below.
（１）評価試料
アルミナから成る生セラミツク体を第１図に示すチップ
キャリアの形状に合わせて成型するとともにその底面に
長さ１．５ｎ＋ｍ、幅０．５ｍＩ＋＋、厚み２０μｍの
パターンを４０個、また上面に幅１．２ｍｍ、厚み２０
μｍの環状のパターン１個をタングステン、モリブデン
、マンガン等から成るメタライズ用ペーストを使用して
印刷形成するとともにこれを還元雰囲気（窒素−水素雰
囲気）中、約１４００〜１６００℃の温度で焼成し、セ
ラミック体表面にメタライズ金属層を形成する。次に前
記各メタライズ金属層表面に第１表に示す如く白金、コ
バルト、ニッケルー金をめっきにより被覆させたもの（
以上、比較例）及びコバルト−白金をめっきにより被覆
させたもの（本発明品）を製作し、これを各評価テスト
用の試料として夫々１００個準備した。(1) Evaluation sample A raw ceramic body made of alumina is molded to match the shape of the chip carrier shown in Fig. 1, and 40 patterns of length 1.5n+m, width 0.5mI++, and thickness 20μm are formed on the bottom surface. Width 1.2mm, thickness 20mm on the top surface
One μm annular pattern is printed using a metallizing paste made of tungsten, molybdenum, manganese, etc., and this is fired at a temperature of about 1400 to 1600°C in a reducing atmosphere (nitrogen-hydrogen atmosphere), A metallized metal layer is formed on the surface of the ceramic body. Next, the surface of each metallized metal layer was coated with platinum, cobalt, nickel-gold as shown in Table 1 (
As described above, a comparative example) and a product coated with cobalt-platinum (invention product) were manufactured, and 100 of these were prepared as samples for each evaluation test.
そして次に、上記評価試料を使用して以下の評価テスト
を行った。その結果を第１表に示す。Next, the following evaluation test was conducted using the above evaluation sample. The results are shown in Table 1.
（ｎ）隙間腐蝕テスト
上記評価試料２５個を、半導体集積回路素子を取着する
際に印加される温度及び絶縁容器を気密封止する際に印
加される温度を想定して順次、４５０℃の温度に２分間
、４３０℃の温度に１０分間保持し、その後、ＭＩＬ−
５ＴＤ−８８３−１００４に規定の温湿度サイクル試験
を２４０時間（１０サイクル）行うとともにメタライズ
金属層及びその表面に施しためっき層を顕微鏡により観
察し、変色しているものの数を調べて、変色の発生率を
算出した。(n) Crevice corrosion test The above 25 evaluation samples were sequentially heated at 450°C, assuming the temperature applied when attaching the semiconductor integrated circuit element and the temperature applied when hermetically sealing the insulating container. temperature for 2 minutes, held at a temperature of 430°C for 10 minutes, then MIL-
The temperature and humidity cycle test specified in 5TD-883-1004 was carried out for 240 hours (10 cycles), and the metallized metal layer and the plating layer applied to its surface were observed using a microscope, and the number of discolored particles was determined. The incidence rate was calculated.
（Ｉ［Ｉ）半田付は性テスト
上記評価試料２５個を前記（ｎ）隙間腐蝕テストと同様
順次、４５０℃の温度に２分間、４３０℃の温度に１０
分間保持し、その後ＭＩＬ−５ＴＤ−８８３Ｃ２００３
，２の半田付着度に規定された方法により、評価試料表
面を８時間水蒸気に曝し、２４５±５℃に制御された溶
融状態の共晶半田中に５秒間浸漬し、メタライズ金属層
に対する半田の濡れ面積が９５％以上のものを良品とし
、その百分率を求めた。(I [I) Soldering test The 25 evaluation samples above were sequentially heated to 450°C for 2 minutes and 430°C for 10 minutes in the same manner as (n) crevice corrosion test.
hold for a minute, then MIL-5TD-883C2003
, 2, the surface of the evaluation sample was exposed to water vapor for 8 hours and immersed in eutectic solder in a molten state controlled at 245 ± 5°C for 5 seconds to determine the degree of solder adhesion to the metallized metal layer. A product with a wetted area of 95% or more was considered to be a good product, and its percentage was determined.
（ｒＶ） ロウ付は強度テスト
上記評価試料２５個を前記（Ｉ［）隙間腐蝕テストと同
様順次、４５０℃の温度に２分間、４３０℃の温度に１
０分間保持し、その後、各試料底面のメタライズ金属層
に直径０．５＋＋＋ｎ＋φの銅線を半田により取着する
。次にこれを半導体集積回路の特性をチェックするバー
ンインテストを想定して１７５℃の温度に１６８時間保
持し、その後、銅線をメタライズ金属層に対し垂直方向
に引張ってロウ付は強度を調べ、その平均値を算出した
。(rV) Brazing is a strength test.The 25 evaluation samples mentioned above were sequentially heated to 450°C for 2 minutes and 430°C for 1 minute in the same manner as the (I[) crevice corrosion test.
After holding for 0 minutes, a copper wire with a diameter of 0.5+++n+φ is attached to the metallized metal layer on the bottom surface of each sample by soldering. Next, this was held at a temperature of 175°C for 168 hours assuming a burn-in test to check the characteristics of semiconductor integrated circuits, and then the brazing strength was examined by pulling the copper wire in a direction perpendicular to the metallized metal layer. The average value was calculated.
（Ｖ）気密封止テスト
上記評価試料２５個を前記（ｎ）隙間腐蝕テストと同様
、４５０℃の温度に２分間保持した後、試料上面の環状
メタライズ金属層に金−スズ合金のコラ材を用いて金め
っきされたコバールの板を接合し、絶縁基体の内部空所
を気密に封止する。そしてその後、−６５℃と＋１５０
℃の温度サイクルを３０サイクル、３０００Ｇの衝撃試
験を１０サイクル及びバーンインテストを想定して１７
５℃の温度に１６８時間保持し、しかる後、ヘリウム（
Ｈｅ）ガスを利用したリーク検査装置により絶縁基体の
内部空所の気密性を調べ良品率を算出した。(V) Air-tight sealing test As in the above (n) crevice corrosion test, the 25 evaluation samples were held at a temperature of 450°C for 2 minutes, and then a gold-tin alloy cola material was applied to the annular metallized metal layer on the top surface of the sample. The gold-plated Kovar plates are bonded together using a gold-plated Kovar plate, and the internal cavity of the insulating substrate is hermetically sealed. And after that, -65℃ and +150℃
℃ temperature cycle for 30 cycles, 3000G impact test for 10 cycles, and a burn-in test of 17
It was maintained at a temperature of 5°C for 168 hours, and then heated with helium (
He) The airtightness of the internal cavity of the insulating substrate was checked using a leak testing device using gas, and the non-defective product rate was calculated.
第１表から判るように、従来のメタライズ金属層表面に
ニッケルー金の金属層をめっきにより被覆させた試料番
号１５はニッケルの熱拡散及び隙間腐蝕作用により変色
の発生率が８４χと高く、半田付は良品率が２４χと極
めて低く、気密封止の良品率も９２χと低い。またコバ
ルトの金属層のみを形成した試料番号１４はコバルトの
金属層表面の著しい酸化のため、変色発生率は１００Ｘ
となり、ロウ付は強度も２．１Ｋｇ／ｍｍ”と低く、半
田付は性、気密封、止のいずれも極めて不良率が高い。As can be seen from Table 1, sample number 15, in which the surface of the conventional metallized metal layer was coated with a nickel-gold metal layer by plating, had a high discoloration rate of 84χ due to the thermal diffusion and crevice corrosion of nickel, and The non-defective product rate is extremely low at 24χ, and the non-defective product rate for hermetically sealed products is also low at 92χ. In addition, sample number 14, in which only a cobalt metal layer was formed, had a discoloration rate of 100X due to significant oxidation of the surface of the cobalt metal layer.
Therefore, the strength of brazing is as low as 2.1 kg/mm, and the defective rate of soldering is extremely high in terms of strength, airtight sealing, and sealing.
一方、メタライズ金属層表面に直接白金の金属層を設け
た試料番号１では白金の均一電着性に劣ることに起因し
て、ロウ付は強度が１．９Ｋｇ／ｍｍ”と極めて低く、
気密封止の良品率も７６χと低い。On the other hand, in sample number 1, in which a platinum metal layer was directly provided on the surface of the metallized metal layer, the brazing strength was extremely low at 1.9 Kg/mm due to poor uniform electrodeposition of platinum.
The quality of hermetically sealed products is also low at 76χ.
これらに対し、本発明によれば変色発生率は皆無であり
、またロウ付は強度は３．７Ｋｇ／ｍｍ２以上と高く、
半田付は良品率も９６％以上と優れ、気密封止の良品率
がいずれも１００％と極めて高く、良好な特性であるこ
とが判明した。In contrast, according to the present invention, there is no incidence of discoloration, and the strength of brazing is as high as 3.7 kg/mm2 or more.
The yield rate for soldering was excellent at over 96%, and the yield rate for hermetic sealing was extremely high at 100%, indicating good characteristics.
以上の如く、本発明のメタライズ金属層の表面被覆構造
では耐熱性及び耐湿性に優れ、電子部品としての機能に
支障を来す隙間腐蝕作用は勿論、変色の発生や気密封止
の劣化が皆無であり、かつロウ材との反応性に優れた高
信頼性の電子部品が得られる。As described above, the surface coating structure of the metallized metal layer of the present invention has excellent heat resistance and moisture resistance, and there is no occurrence of discoloration or deterioration of hermetic sealing, as well as crevice corrosion that interferes with the function of electronic components. A highly reliable electronic component with excellent reactivity with the brazing material can be obtained.
第１図は本発明に係るメタライズ金属層の表面被覆構造
を説明するためにチップキャリアを例に採って示した要
部拡大断面図、第２図は従来のチップキャリアの断面図
である。
１．１１ ・・・・・絶縁基体
２．２ａ、１２ ・・・・メタライズ金属層３．３ａ
・・・・・・第１の金属層
４．４ａ・・・・・・第２の金属層
５、工３・・・・・・蓋体FIG. 1 is an enlarged sectional view of a main part of a chip carrier taken as an example to explain the surface coating structure of a metallized metal layer according to the present invention, and FIG. 2 is a sectional view of a conventional chip carrier. 1.11... Insulating base 2.2a, 12... Metallized metal layer 3.3a
......First metal layer 4.4a...Second metal layer 5, work 3...Lid body
Claims (1)
）を主成分とする第１の金属層と白金（Ｐｔ）を主成分
とする第２の金属層との少なくとも二層から成る金属層
を層着被覆したことを特徴とするメタライズ金属層の表
面被覆構造。Cobalt (Co) is applied to the surface of the metallized metal layer on the insulating substrate.
) and a second metal layer containing platinum (Pt) as a main component. Covered structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61283391A JPH0736952B2 (en) | 1986-11-27 | 1986-11-27 | Surface coating structure of metallized metal layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61283391A JPH0736952B2 (en) | 1986-11-27 | 1986-11-27 | Surface coating structure of metallized metal layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63137574A true JPS63137574A (en) | 1988-06-09 |
| JPH0736952B2 JPH0736952B2 (en) | 1995-04-26 |
Family
ID=17664912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61283391A Expired - Lifetime JPH0736952B2 (en) | 1986-11-27 | 1986-11-27 | Surface coating structure of metallized metal layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0736952B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02139951A (en) * | 1988-11-21 | 1990-05-29 | Kyocera Corp | Package for housing semiconductor element |
| US20140084752A1 (en) * | 2012-09-26 | 2014-03-27 | Seiko Epson Corporation | Method of manufacturing electronic device, electronic apparatus, and mobile apparatus |
| CN105689833A (en) * | 2016-03-24 | 2016-06-22 | 株洲天微技术有限公司 | Brazing sealing covering method and structure for shell and cover plate of microcircuit module |
| CN108370244A (en) * | 2015-12-22 | 2018-08-03 | 京瓷株式会社 | Sealing ring, taking in electronic element packaging body, electronic equipment and their manufacturing method |
-
1986
- 1986-11-27 JP JP61283391A patent/JPH0736952B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02139951A (en) * | 1988-11-21 | 1990-05-29 | Kyocera Corp | Package for housing semiconductor element |
| US20140084752A1 (en) * | 2012-09-26 | 2014-03-27 | Seiko Epson Corporation | Method of manufacturing electronic device, electronic apparatus, and mobile apparatus |
| US9660176B2 (en) * | 2012-09-26 | 2017-05-23 | Seiko Epson Corporation | Method of manufacturing electronic device, electronic apparatus, and mobile apparatus |
| CN108370244A (en) * | 2015-12-22 | 2018-08-03 | 京瓷株式会社 | Sealing ring, taking in electronic element packaging body, electronic equipment and their manufacturing method |
| CN108370244B (en) * | 2015-12-22 | 2021-12-24 | 京瓷株式会社 | Seal ring, package for housing electronic component, electronic device, and methods for manufacturing seal ring and package for housing electronic component |
| CN105689833A (en) * | 2016-03-24 | 2016-06-22 | 株洲天微技术有限公司 | Brazing sealing covering method and structure for shell and cover plate of microcircuit module |
| CN105689833B (en) * | 2016-03-24 | 2018-02-23 | 株洲天微技术有限公司 | A kind of the sealed with brazing capping method and structure of microcircuit module housing and cover plate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0736952B2 (en) | 1995-04-26 |
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