JPH0736952B2 - Surface coating structure of metallized metal layer - Google Patents

Surface coating structure of metallized metal layer

Info

Publication number
JPH0736952B2
JPH0736952B2 JP61283391A JP28339186A JPH0736952B2 JP H0736952 B2 JPH0736952 B2 JP H0736952B2 JP 61283391 A JP61283391 A JP 61283391A JP 28339186 A JP28339186 A JP 28339186A JP H0736952 B2 JPH0736952 B2 JP H0736952B2
Authority
JP
Japan
Prior art keywords
metal layer
metallized metal
metallized
main component
coating structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61283391A
Other languages
Japanese (ja)
Other versions
JPS63137574A (en
Inventor
義博 細井
孝年 入江
隆晴 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP61283391A priority Critical patent/JPH0736952B2/en
Publication of JPS63137574A publication Critical patent/JPS63137574A/en
Publication of JPH0736952B2 publication Critical patent/JPH0736952B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はメタライズ金属層の表面被覆構造に関し、より
詳細には半導体集積回路素子を収納する半導体素子収納
用パッケージや多層配線基板等の電子部品におけるメタ
ライズ金属層の表面被覆構造に関するものである。
Description: TECHNICAL FIELD The present invention relates to a surface coating structure of a metallized metal layer, and more particularly to an electronic component such as a semiconductor element housing package for housing a semiconductor integrated circuit element or a multilayer wiring board. The present invention relates to the surface coating structure of the metallized metal layer in.

〔従来の技術〕[Conventional technology]

従来、電子部品、例えば半導体集積回路素子を収納する
ためのリードレスパッケージ(チップキャリア)は第2
図に示すようにセラミック、ガラス等の電気絶縁材料か
ら成り,その上面に蓋体をロウ付けするための、また外
周部、即ち側面及び底面に半導体集積回路素子を外部電
気回路に接続するためのタングステン(W)、モリブデ
ン(Mo)等の高融点金属粉末から成るメタライズ金属層
12a,12bを形成した絶縁基体11と蓋体13とから構成され
ており、絶縁基体11と蓋体13から成る絶縁容器内部に半
導体集積回路素子14を収納するとともに蓋体13を絶縁基
体11にロウ付けし絶縁容器の内部を気密封止することに
よって半導体装置となる。
Conventionally, a leadless package (chip carrier) for accommodating an electronic component, for example, a semiconductor integrated circuit device is a second type.
As shown in the figure, it is made of an electrically insulating material such as ceramic or glass, and is used for brazing the lid on its upper surface and for connecting the semiconductor integrated circuit element to the external electric circuit on the outer peripheral portion, that is, the side surface and the bottom surface. Metallized metal layer made of refractory metal powder such as tungsten (W) and molybdenum (Mo)
It is composed of an insulating base 11 on which 12a and 12b are formed and a lid 13, and a semiconductor integrated circuit element 14 is housed inside an insulating container made of the insulating base 11 and the lid 13 and the lid 13 is formed on the insulating base 11. A semiconductor device is obtained by brazing and hermetically sealing the inside of the insulating container.

この従来のチップキャリアは内部に収納した半導体集積
回路素子14を外部電気回路に接続するために絶縁基体11
底面部のメタライズ金属層12bは外部電気配線基板15の
配線導体16にロウ材17を介しロウ付け取着され、絶縁基
体11底面部のメタライズ金属層12bにはその表面にロウ
付け強度を強固とするためのニッケル(Ni)及び金(A
u)から成る金属層がめっきにより被覆されている。
This conventional chip carrier has an insulating substrate 11 for connecting a semiconductor integrated circuit element 14 housed inside to an external electric circuit.
The metallized metal layer 12b on the bottom surface is brazed and attached to the wiring conductor 16 of the external electric wiring substrate 15 via the brazing material 17, and the metallized metal layer 12b on the bottom surface of the insulating substrate 11 has a strong brazing strength on its surface. Nickel (Ni) and gold (A
The metal layer consisting of u) is coated by plating.

また同時に絶縁基体11上面のメタライズ金属層12aにも
蓋体13のロウ付けを強固とし、絶縁容器の気密封止を完
全とするためにロウ材の濡れ性が良いニッケル(Ni)及
び金(Au)がめっきにより被覆されている。
At the same time, the lid 13 is firmly brazed to the metallized metal layer 12a on the upper surface of the insulating substrate 11, and nickel (Ni) and gold (Au), which have good wettability of the brazing material in order to complete the hermetic sealing of the insulating container. ) Is coated by plating.

しかしながら、絶縁基体11には直接めっきができないこ
と及びめっき液の循環が悪いこと等からメタライズ金属
層12a,12bの側面で絶縁基体11表面近傍部分にはニッケ
ルめっき層を被覆させることができず、ニッケルめっき
層と絶縁基体11との間にわずかな隙間が形成される。そ
のためにこの隙間の一部に大気中に含まれる水分等が付
着するとニッケルめっき層に酸素濃度の相違に起因する
隙間腐蝕作用を生じ、ニッケルめっき層に酸化物(錆)
や水酸化物を生成し変色させることがある。
However, since the insulating base 11 cannot be directly plated and the circulation of the plating solution is poor, it is not possible to cover the surface of the insulating base 11 on the side surfaces of the metallized metal layers 12a and 12b with the nickel plating layer. A slight gap is formed between the nickel plating layer and the insulating substrate 11. Therefore, if moisture contained in the atmosphere adheres to a portion of this gap, the nickel plating layer will have a gap corrosion action due to the difference in oxygen concentration, and the nickel plating layer will have an oxide (rust).
May form hydroxide or hydroxide and cause discoloration.

更にこの酸化物(錆)及び水酸化物は導電性で、かつ拡
散し易いという性質を有することから、例えば多数のメ
タライズ金属層12bが近接して形成されているチップキ
ャリアにおいては前記酸化物(錆)や水酸化物の拡散に
より隣接するメタライズ金属層12b間が短絡し、電子部
品としての機能に支障を来すという重大な欠点を誘発す
る。
Furthermore, since the oxides (rust) and hydroxides have the property of being electrically conductive and easily diffused, for example, in a chip carrier in which many metallized metal layers 12b are formed in close proximity, the oxide ( Due to diffusion of rust) or hydroxide, a short circuit occurs between the adjacent metallized metal layers 12b, which causes a serious defect that the function as an electronic component is impaired.

そこで、かかる欠点を解消するために、メタライズ金属
層の表面に被覆されるニッケルの金属層に代えて、化学
的に安定で導電性の錆を発生することがなく、ロウ材と
極めて反応性(濡れ性)の良い白金、パラジウム(Pd)
もしくはそれらの合金を主成分とする金属層をめっきに
より被覆させることを本出願人は先に提案した。
Therefore, in order to eliminate such a drawback, in place of the nickel metal layer coated on the surface of the metallized metal layer, chemically stable and conductive rust is not generated, and it is extremely reactive with the brazing material ( Platinum (Pd) with good wettability
Alternatively, the present applicant has previously proposed coating a metal layer containing these alloys as a main component by plating.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかしながら、上記白金、パラジウムもしくはそれらの
合金を主成分とする金属層を直接タングステン,モリブ
デン等の高融点金属粉末から成るメタライズ金属層上に
めっきにより形成すると、該めっき金属層における隙間
腐蝕作用は有効に防止し得るものの、白金、パラジウム
もしくはそれらの合金を主成分とする金属は均一電着性
に劣ることからメタライズ金属層上に均一厚みに被覆さ
せることができず、そのため、めっき金属層に外部より
機械的な応力が印加されると該めっき金属層の一部がメ
タライズ金属層より剥離し、これが半導体集積回路素子
の特性をチェックするバーンインテスト(半導体集積回
路素子に高温の熱履歴を加えて特性変化を調べるテス
ト)等を行った場合に助長されて、めっき金属層のうち
蓋体がロウ付けされる部位や外部電気回路の配線導体に
ロウ付けされる部分のものがメタライズ金属層より完全
に剥離してしまい、その結果、半導体装置の外部電気回
路への取着接続が不完全となったり、絶縁容器の気密封
止が破れるという問題を有していた。
However, when the metal layer containing platinum, palladium, or an alloy thereof as a main component is directly formed on the metallized metal layer made of a refractory metal powder such as tungsten or molybdenum, the crevice corrosion effect in the plated metal layer is effective. However, the metal containing platinum, palladium, or an alloy thereof as a main component cannot be coated to a uniform thickness on the metallized metal layer because of its poor throwing power. When more mechanical stress is applied, a part of the plated metal layer peels off from the metallized metal layer, which causes the burn-in test to check the characteristics of the semiconductor integrated circuit element (when a high temperature heat history is applied to the semiconductor integrated circuit element, It is promoted when a test to check the change in characteristics is performed, and the lid of the plated metal layer is brazed. The part or the part brazed to the wiring conductor of the external electric circuit is completely peeled off from the metallized metal layer, and as a result, the attachment connection of the semiconductor device to the external electric circuit is incomplete, or the insulation is isolated. There was a problem that the hermetic seal of the container was broken.

〔発明の目的〕[Object of the Invention]

本発明は前記欠点に鑑み案出されたもので、その目的は
半導体集積回路素子をチェックするバーンインテスト等
を行ったとしても絶縁容器の気密封止が破れることがな
く、また半導体装置等の電子部品を外部電気回路に確実
に接続することが可能なメタライズ金属層の表面被覆構
造を提供することにある。
The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to prevent the airtight sealing of an insulating container from being broken even if a burn-in test or the like for checking a semiconductor integrated circuit element is performed, and an electronic device such as a semiconductor device. It is an object of the present invention to provide a surface coating structure of a metallized metal layer capable of reliably connecting a component to an external electric circuit.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は絶縁基体上のメタライズ金属層表面に、コバル
ト(Co)を主成分とする第1の金属層と白金(Pt)を主
成分とする第2の金属層との少なくとも二層から成る金
属層を層着被覆したことを特徴とするものである。
The present invention provides a metal having at least two layers, a first metal layer containing cobalt (Co) as a main component and a second metal layer containing platinum (Pt) as a main component, on the surface of a metallized metal layer on an insulating substrate. It is characterized in that the layers are layered and coated.

本発明においてメタライズ金属層表面に、コバルトを主
成分とする第1の金属層を設け、その上に白金を主成分
とする第2の金属層を層着被覆した場合、該コバルはメ
タライズ金属層及び白金を主成分とする金属層のいずれ
とも密着力大として層着被覆することができ、かつニッ
ケルと比較して前記隙間腐蝕作用を受け難いという特性
を有し、更に化学的に安定な金属層を得ることができ
る。
In the present invention, when the first metal layer containing cobalt as the main component is provided on the surface of the metallized metal layer and the second metal layer containing platinum as the main component is layer-coated on the first metal layer, the cobalt is the metallized metal layer. And a metal layer containing platinum as a main component, which can be layered and coated with high adhesion and is less susceptible to the above-mentioned crevice corrosion action than nickel, and is a chemically stable metal. Layers can be obtained.

〔実施例〕〔Example〕

次に本発明を第1図に示す実施例に基づき詳細に説明す
る。
Next, the present invention will be described in detail based on the embodiment shown in FIG.

第1図は本発明のメタライズ金属層の表面被覆構造を説
明するためにチップキャリア(半導体集積回路素子を収
納するためのリードレスパッケージ)を例にとって示し
た要部拡大断面図である。図において、1はセラミッ
ク,ガラス等の電気絶縁材料から成る絶縁基体、5は蓋
体である。この絶縁基体1と蓋体5で半導体集積回路素
子6を収納する絶縁容器を構成する。前記絶縁基体1は
その上面中央部に半導体集積回路素子6を収納するため
の空所を形成する段状の凹部を有しており、凹部底面に
半導体集積回路素子6が接着材を介し取着されている。
FIG. 1 is an enlarged cross-sectional view of an essential part showing a chip carrier (leadless package for housing a semiconductor integrated circuit device) as an example for explaining a surface coating structure of a metallized metal layer of the present invention. In the figure, 1 is an insulating base made of an electrically insulating material such as ceramic or glass, and 5 is a lid. The insulating base 1 and the lid 5 constitute an insulating container for housing the semiconductor integrated circuit element 6. The insulating base 1 has a stepped recess in the center of its upper surface that forms a space for accommodating the semiconductor integrated circuit device 6, and the semiconductor integrated circuit device 6 is attached to the bottom of the recess with an adhesive. Has been done.

また、前記絶縁基体1には凹部底面及び凹部段状上面か
ら側面を介し底面にかけてメタライズ金属層2が形成さ
れており、メタライズ金属層2の凹部段状上面部には半
導体集積回路素子6の電極がワイヤ7を介し電気的に接
続される。
A metallized metal layer 2 is formed on the insulating substrate 1 from the bottom surface of the recess and the upper surface of the recessed step to the bottom surface through the side surface. On the upper surface of the recessed step of the metallized metal layer 2, the electrode of the semiconductor integrated circuit element 6 is formed. Are electrically connected via the wire 7.

前記メタライズ金属層2はタングステン、モリブデン等
の高融点金属粉末から成り、従来周知のスクリーン印刷
等の厚膜手法を採用することによって絶縁基体1の外周
部に形成される。
The metallized metal layer 2 is made of a high melting point metal powder such as tungsten and molybdenum, and is formed on the outer peripheral portion of the insulating substrate 1 by using a conventionally known thick film method such as screen printing.

また、前記メタライズ金属層2の絶縁基体1凹部底面
部、段状上面部及び側底面部にはコバルトを主成分とす
る第1の金属層3と白金を主成分とする第2の金属層4
がそれぞれめっき等により層着されており、メタライズ
金属層2はコバルトを主成分とする金属層と白金を主成
分とする金属層の二層により被覆されている。
Further, the metallized metal layer 2 has a first metal layer 3 containing cobalt as a main component and a second metal layer 4 containing platinum as a main component on the bottom surface of the concave portion, the stepped top surface and the side bottom surface.
Are each layered by plating or the like, and the metallized metal layer 2 is covered with two layers of a metal layer containing cobalt as a main component and a metal layer containing platinum as a main component.

また、前記絶縁基体1の上面にはセラミック、ガラス等
の電気絶縁材料から成るシールリング8が取着されてお
り、該シールリング8の上面にはメタライズ金属層2aが
前記手法と同様の手法により形成され、その上面部には
コバルトを主成分とする第1の金属層3aと白金を主成分
とする第2の金属層4aが層着被覆されている。
A seal ring 8 made of an electrically insulating material such as ceramic or glass is attached to the upper surface of the insulating substrate 1, and a metallized metal layer 2a is formed on the upper surface of the seal ring 8 by the same method as described above. The first metal layer 3a containing cobalt as a main component and the second metal layer 4a containing platinum as a main component are layered and coated on the upper surface of the first metal layer 3a.

前記第2の金属層4a上にはコバール(Fe−Ni−Co合金)
に金(Au)めっきを施した蓋体5が金(Au)−スズ(S
n)合金のロウ材を介して取着されており、これにより
チップキャリア内部の空所は外気から完全に気密に封止
され最終製品である半導体装置となる。
Kovar (Fe-Ni-Co alloy) is formed on the second metal layer 4a.
The lid 5 that is plated with gold (Au) is gold (Au) -tin (S
n) It is attached via an alloy brazing material, whereby the void inside the chip carrier is completely airtightly sealed from the outside air, and the final product is a semiconductor device.

かくして、本発明によれば絶縁容器の外周部及びシール
リングの上面部に形成したメタライズ金属層表面に密着
力が大であるコバルトを主成分とする金属層と化学的に
安定な白金を主成分とする金属層を少なくとも二層設け
たことにより、隙間腐蝕作用を受けることは勿論、メタ
ライズ金属層とめっき金属層の密着強度を大としてめっ
き金属層がメタライズ金属層より剥離するのを皆無とな
し、同時に絶縁基体と蓋体のロウ付け及び半導体装置と
外部電気配線基板とのロウ付けを極めて強固となすこと
ができる。
Thus, according to the present invention, a metal layer containing cobalt as a main component, which has a large adhesion to the surface of the metallized metal layer formed on the outer peripheral part of the insulating container and the upper surface of the seal ring, and a chemically stable platinum main component. As a result of providing at least two metal layers, the metal corrosion metal layer and the plated metal layer have a high adhesion strength, and the plated metal layer does not separate from the metallized metal layer. At the same time, the brazing of the insulating base and the lid and the brazing of the semiconductor device and the external electric wiring board can be made extremely strong.

尚、本発明は上述の実施例に限定されるものではなく、
例えばリード付きの半導体素子収納用パッケージや多層
配線基板等のメタライズ金属層を有する電子部品にも適
用することができる。
The present invention is not limited to the above-mentioned embodiment,
For example, the present invention can be applied to electronic components having a metallized metal layer such as a leaded semiconductor element housing package and a multilayer wiring board.

次に本発明の作用効果を以下に示す実験例に基づき説明
する。
Next, the operation and effect of the present invention will be described based on the following experimental examples.

〔実験例〕[Experimental example]

(I)評価試料 アルミナから成る生セラミック体を第1図に示すチップ
キャリアの形状に合わせて成型するとともにその底面に
長さ1.5mm,幅0.5mm,厚み20μmのパターンを40個、また
上面に幅1.2mm,厚み20μmの環状のパターン1個をタン
グステン、モリブデン,マンガン等から成るメタライズ
用ペーストを使用して印刷形成するとともにこれを還元
雰囲気(窒素−水素雰囲気)中、約1400〜1600℃の温度
で焼成し、セラミック体表面にメタライズ金属層を形成
する。次に前記各メタライズ金属層表面に第1表に示す
如く白金,コバルト,ニッケル−金をめっきにより被覆
させたもの(以上,比較例)及びコバルト−白金めっき
により被覆させたもの(本発明品)を製作し、これを各
評価テスト用の試料として夫々100個準備した。
(I) Evaluation sample A green ceramic body made of alumina was molded according to the shape of the chip carrier shown in FIG. 1, and 40 patterns with a length of 1.5 mm, a width of 0.5 mm and a thickness of 20 μm were formed on the bottom surface, and on the top surface. A ring-shaped pattern with a width of 1.2 mm and a thickness of 20 μm is printed and formed using a metallizing paste made of tungsten, molybdenum, manganese, etc., and this is heated in a reducing atmosphere (nitrogen-hydrogen atmosphere) at about 1400-1600 ° C. It is fired at a temperature to form a metallized metal layer on the surface of the ceramic body. Next, as shown in Table 1, each metallized metal layer surface is coated with platinum, cobalt, nickel-gold by plating (above, comparative example) and cobalt-platinum plating (product of the present invention). Was manufactured, and 100 of each were prepared as samples for each evaluation test.

そして次に、上記評価試料を使用して以下の評価テスト
を行った。その結果を第1表に示す。
Then, next, the following evaluation tests were performed using the above evaluation samples. The results are shown in Table 1.

(II)隙間腐蝕テスト 上記評価試料25個を、半導体集積回路素子を取着する際
に印加される温度及び絶縁容器を気密封止する際に印加
される温度を想定して順次、450℃の温度に2分間、430
℃の温度に10分間保持し、その後、MIL−STD−883−100
4に規定の温湿度サイクル試験を240時間(10サイクル)
行うとともにメタライズ金属層及びその表面に施しため
っき層を顕微鏡により観察し、変色しているものの数を
調べて、変色の発生率を算出した。
(II) Gap corrosion test Twenty-five of the above evaluation samples were sequentially subjected to 450 ° C. assuming the temperature applied when attaching the semiconductor integrated circuit element and the temperature applied when hermetically sealing the insulating container. 2 minutes at temperature, 430
Hold at a temperature of ℃ for 10 minutes, then MIL-STD-883-100
240 hours (10 cycles) of temperature and humidity cycle test specified in 4
In addition, the metallized metal layer and the plating layer applied to the surface of the metallized metal layer were observed with a microscope, and the number of discolored ones was examined to calculate the discoloration occurrence rate.

(III)半田付け性テスト 上記評価試料25個を前記(II)隙間腐蝕テストと同様順
次、450℃の温度に2分間,430℃の温度に10分間保持
し、その後MIL−STD−883C 2003.2の半田付着度に規定
された方法により、評価試料表面を8時間水蒸気に曝
し、245±5℃に制御された溶融状態の共晶半田中に5
秒間浸漬し、メタライズ金属層に対する半田の濡れ面積
が95%以上のものを良品とし、その百分率を求めた。
(III) Solderability test Twenty-five evaluation samples described above were sequentially held at 450 ° C for 2 minutes and 430 ° C for 10 minutes in the same manner as in the (II) crevice corrosion test, and then the MIL-STD-883C 2003.2 The surface of the sample to be evaluated was exposed to water vapor for 8 hours according to the method specified in the solder adhesion, and the eutectic solder in the molten state controlled at 245 ± 5 ° C
It was soaked for a second, and a solder having a wetted area of 95% or more with respect to the metallized metal layer was regarded as a good product, and the percentage thereof was calculated.

(IV)ロウ付け強度テスト 上記評価試料25個を前記(II)隙間腐蝕テストと同様順
次、450℃の温度に2分間,430℃の温度に10分間保持
し、その後、各試料底面のメタライズ金属層に直径0.5m
mφの銅線を半田により取着する。次にこれを半導体集
積回路の特性をチェックするバーンインテストを想定し
て175℃の温度に168時間保持し、その後、銅線をメタラ
イズ金属層に対し垂直方向に引張ってロウ付け強度を調
べ、その平値を算出した。
(IV) Brazing Strength Test The 25 evaluation samples above were sequentially held at 450 ° C. for 2 minutes and 430 ° C. for 10 minutes in the same manner as in the above (II) crevice corrosion test, and then the metallized metal on the bottom surface of each sample. 0.5m diameter in layers
Attach the mφ copper wire with solder. Next, assuming this for a burn-in test to check the characteristics of the semiconductor integrated circuit, hold it at a temperature of 175 ° C for 168 hours, then pull the copper wire in the direction perpendicular to the metallized metal layer and examine the brazing strength. The average price was calculated.

(V)気密封止テスト 上記評価試料25個を前記(II)隙間腐蝕テストと同様、
450℃の温度に2分間保持した後、試料上面の環状メタ
ライズ金属層に金−スズ合金のロウ材を用いて金めっき
されたコバールの板を接合し、絶縁基体の内部空所を気
密に封止する。そしてその後、−65℃と+150℃の温度
サイクルを30サイクル、3000Gの衝撃試験を10サイクル
及びバーンインテストを想定して175℃の温度に168時間
保持し、しかる後、ヘリウム(He)ガスを利用したリー
ク検査装置により絶縁基体の内部空所の気密性を調べ良
品率を算出した。
(V) Airtight sealing test The 25 evaluation samples above were subjected to the same test as the (II) crevice corrosion test.
After holding at a temperature of 450 ° C for 2 minutes, a Kovar plate plated with gold-tin alloy brazing material was joined to the annular metallized metal layer on the upper surface of the sample to hermetically seal the inner cavity of the insulating substrate. Stop. After that, 30 cycles of -65 ℃ and + 150 ℃ temperature cycles, 10 cycles of 3000G impact test and 165 hours of temperature at 175 ℃ assuming burn-in test are performed, and then helium (He) gas is used. The leak inspecting device was used to check the airtightness of the inner space of the insulating substrate and calculate the non-defective rate.

第1表から判るように、従来のメタライズ金属層表面に
ニッケル−金の金属層をめっきにより被覆させた試料番
号15はニッケルの熱拡散及び隙間腐蝕作用により変色の
発生率が84%と高く、半田付け良品率が24%と極めて低
く、気密封止の良品率も92%と低い。またコバルトの金
属層のみを形成した試料番号14はコバルトの金属層表面
の著しい酸化のため、変色発生率は100%となり、ロウ
付け強度も2.1Kg/mm2と低く、半田付け性、気密封止の
いずれも極めて不良率が高い。
As can be seen from Table 1, Sample No. 15 in which the surface of the conventional metallized metal layer is coated with a nickel-gold metal layer by plating has a high discoloration occurrence rate of 84% due to the thermal diffusion and crevice corrosion of nickel, The rate of non-defective products for soldering is extremely low at 24%, and the rate of non-defective products for hermetic sealing is also low at 92%. In addition, Sample No. 14 with only the cobalt metal layer formed has a 100% discoloration rate due to the significant oxidation of the cobalt metal layer surface, and the brazing strength is as low as 2.1 kg / mm 2 , solderability, and airtightness. The failure rate is extremely high in both cases.

一方、メタライズ金属層表面に直接白金の金属層を設け
た試料番号1では白金の均一電着性に劣ることに起因し
て、ロウ付け強度が1.9Kg/mm2と極めて低く、気密封止
の良品率も76%と低い。
On the other hand, in sample No. 1 in which the platinum metal layer was directly provided on the metallized metal layer surface, the brazing strength was extremely low at 1.9 Kg / mm 2 due to the inferior platinum uniform electrodeposition and The non-defective rate is as low as 76%.

これらに対し、本発明によれば変色発生率は皆無であ
り、またロウ付け強度は3.7Kg/mm2以上と高く、半田付
け良品率も96%以上と優れ、気密封止の良品率がいずれ
も100%と極めて高く、良好な特性であることが判明し
た。
On the other hand, according to the present invention, there is no occurrence of discoloration, the brazing strength is as high as 3.7 kg / mm 2 or more, the good soldering rate is 96% or more, and the good rate of hermetic sealing is Was also extremely high at 100% and was found to have good characteristics.

〔発明の効果〕〔The invention's effect〕

以上の如く、本発明のメタライズ金属層の表面被覆構造
では耐熱性及び耐湿性に優れ、電子部品としての機能に
支障を来す隙間腐蝕作用は勿論、変色の発生や気密封止
の劣化が皆無であり、かつロウ材との反応性に優れた高
信頼性の電子部品が得られる。
As described above, the surface coating structure of the metallized metal layer of the present invention is excellent in heat resistance and moisture resistance, and has no crevice corrosion action which impairs the function as an electronic component, and does not cause discoloration or deterioration of hermetic sealing. It is also possible to obtain a highly reliable electronic component having excellent reactivity with the brazing material.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明に係るメタライズ金属層の表面被覆構造
を説明するためにチップキャリアを例に採って示した要
部拡大断面図、第2図は従来のチップキャリアの断面図
である。 1,11……絶縁基体 2,2a,12……メタライズ金属層 3,3a……第1の金属層 4,4a……第2の金属層 5,13……蓋体
FIG. 1 is an enlarged cross-sectional view of an essential part showing a chip carrier as an example for explaining a surface coating structure of a metallized metal layer according to the present invention, and FIG. 2 is a cross-sectional view of a conventional chip carrier. 1,11 …… Insulating substrate 2,2a, 12 …… Metalized metal layer 3,3a …… First metal layer 4,4a… Second metal layer 5,13 …… Lid

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁基体上のメタライズ金属層表面に、コ
バルト(Co)を主成分とする第1の金属層と白金(Pt)
を主成分とする第2の金属層との少なくとも二層から成
る金属層を層着被覆したことを特徴とするメタライズ金
属層の表面被覆構造。
1. A first metal layer containing cobalt (Co) as a main component and platinum (Pt) on the surface of a metallized metal layer on an insulating substrate.
A surface coating structure for a metallized metal layer, characterized in that a metal layer comprising at least two layers including a second metal layer containing as a main component is layered and coated.
JP61283391A 1986-11-27 1986-11-27 Surface coating structure of metallized metal layer Expired - Lifetime JPH0736952B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61283391A JPH0736952B2 (en) 1986-11-27 1986-11-27 Surface coating structure of metallized metal layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61283391A JPH0736952B2 (en) 1986-11-27 1986-11-27 Surface coating structure of metallized metal layer

Publications (2)

Publication Number Publication Date
JPS63137574A JPS63137574A (en) 1988-06-09
JPH0736952B2 true JPH0736952B2 (en) 1995-04-26

Family

ID=17664912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61283391A Expired - Lifetime JPH0736952B2 (en) 1986-11-27 1986-11-27 Surface coating structure of metallized metal layer

Country Status (1)

Country Link
JP (1) JPH0736952B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2866962B2 (en) * 1988-11-21 1999-03-08 京セラ株式会社 Manufacturing method of semiconductor device storage package
JP6167494B2 (en) * 2012-09-26 2017-07-26 セイコーエプソン株式会社 Electronic device container manufacturing method, electronic device manufacturing method, electronic device, electronic apparatus, and mobile device
JP6787662B2 (en) * 2015-12-22 2020-11-18 京セラ株式会社 Seal ring, electronic component storage package, electronic device and manufacturing method of these
CN105689833B (en) * 2016-03-24 2018-02-23 株洲天微技术有限公司 A kind of the sealed with brazing capping method and structure of microcircuit module housing and cover plate

Also Published As

Publication number Publication date
JPS63137574A (en) 1988-06-09

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