JPH02139951A - Package for housing semiconductor element - Google Patents
Package for housing semiconductor elementInfo
- Publication number
- JPH02139951A JPH02139951A JP29415988A JP29415988A JPH02139951A JP H02139951 A JPH02139951 A JP H02139951A JP 29415988 A JP29415988 A JP 29415988A JP 29415988 A JP29415988 A JP 29415988A JP H02139951 A JPH02139951 A JP H02139951A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- metallized
- insulating substrate
- metal layer
- insulating base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 45
- 239000000758 substrate Substances 0.000 abstract description 24
- 239000000919 ceramic Substances 0.000 abstract description 20
- 238000005219 brazing Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 6
- 239000011733 molybdenum Substances 0.000 abstract description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052721 tungsten Inorganic materials 0.000 abstract description 6
- 239000010937 tungsten Substances 0.000 abstract description 6
- 238000007639 printing Methods 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 239000010931 gold Substances 0.000 description 6
- 239000000843 powder Substances 0.000 description 6
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012777 electrically insulating material Substances 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 239000011572 manganese Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000000276 sedentary effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（座業上の利用分野）
本発明は半導体素子、特に半導体集積回路素子を収容す
るための半導体素子収納用パッケージの改良に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION (Field of Sedentary Use) The present invention relates to an improvement in a package for accommodating a semiconductor element, particularly for accommodating a semiconductor integrated circuit element.
（従来の技術）
従来、半導体素子を収容するための半導体素子収納用パ
ッケージ、例えばリードレスのパッケージ（チップキャ
リア）は、アルミナ（Ａｌｔｏｓ）セラミックス等の電
気絶縁材料から成り、その上面中央部に、底面にメタラ
イズ金属層が被着形成された半導体素子を収容するため
の凹部を有し、かつ外周部、即ち側面及び底面に半導体
素子を外部電気回路に接続するためのタングステン（Ｗ
） 、モリブデン（Ｍｏ）等の金属粉末から成るメタラ
イズリードを被着形成した絶縁基体と蓋体とから構成さ
れており、絶縁基体の凹部底面に設けたメタライズ金属
層上に半導体素子を取着固定するとともに該半導体素子
の各電極をボンディングワイヤを介しメタライズリード
に電気的に接続し、しかる後、絶縁基体の上面に蓋体を
接着材を介し接合させ、内部に半導体素子を気密に封止
することによって最終製品としての半導体装置が完成す
る。(Prior Art) Conventionally, a semiconductor element storage package for accommodating a semiconductor element, such as a leadless package (chip carrier), is made of an electrically insulating material such as alumina (Altos) ceramics, and has a central part on its upper surface. It has a recessed portion on the bottom surface for accommodating the semiconductor element on which a metallized metal layer is deposited, and a tungsten (W
), consists of an insulating base on which a metallized lead made of metal powder such as molybdenum (Mo) is adhered, and a lid, and a semiconductor element is attached and fixed on the metallized metal layer provided on the bottom of the recess of the insulating base. At the same time, each electrode of the semiconductor element is electrically connected to the metallized lead via a bonding wire, and then a lid body is bonded to the upper surface of the insulating base via an adhesive, and the semiconductor element is hermetically sealed inside. As a result, a semiconductor device as a final product is completed.
尚、この従来の半導体素子収納用パッケージは絶縁基体
の凹部底面に設けたメタライズ金属層に半導体素子を強
固に取着固定するために、またメタライズリードと外部
電気回路との電気的接続を良好とし、かつメタライズリ
ードが酸化腐蝕するのを有効に防止するために通常、メ
タライズ金属層及びメタライズリードの外表面にはニッ
ケル（Ｎｉ）及び金（Ａｕ）等がメツキにより層着され
ている。This conventional package for storing semiconductor elements is designed to firmly attach and fix the semiconductor element to the metallized metal layer provided on the bottom of the recess of the insulating base, and to ensure good electrical connection between the metallized leads and the external electric circuit. In order to effectively prevent oxidative corrosion of the metallized lead, nickel (Ni), gold (Au), etc. are usually deposited on the outer surface of the metallized metal layer and the metallized lead by plating.
（発明が解決しようとする課題）
しかし乍ら、この従来の半導体素子収納用バフケージは
、近時の電子機器の小型化に伴い絶縁基体の形状が小さ
く、特に厚みが薄くなってきていること、絶縁基体の凹
部底面に被着形成されるメタライズ金属層はその厚みが
他のメタライズリードと同じく約２０μ請以上あること
等から以下に述べるような欠点を有する。(Problem to be Solved by the Invention) However, in this conventional buff cage for storing semiconductor elements, the shape of the insulating base has become smaller and the thickness has become thinner as electronic devices have become smaller in recent years. The metallized metal layer deposited on the bottom surface of the recess of the insulating substrate has the following disadvantages because its thickness is about 20 micrometers or more like other metallized leads.
即ち、未焼成のセラミック体にタングステン（−）、モ
リブデン（Ｎｏ）等の金属粉末から成る金属ペーストを
２０μ−以上の厚みに印刷塗布し、しかる後、これを還
元性雰囲気中、約１５００℃の温度で焼成してメタライ
ズ金属層及びメタライズリードを有するセラミワク体（
絶縁基体）を得る際、セラミックはタングステン（す、
モリブデン（Ｍｏ）等のメタライズ金属層と熱膨張係数
が異なることから両者間に熱膨張係数の相違に起因する
応力が発生し、これが絶縁基体内に内在したものとなっ
ている。そのためこの絶縁基体のメタライズ金属層上に
半導体素子を金−シリコン（Ａｕ−５ｉ）等のロウ材を
介し取着固定する場合、絶縁基体に半導体素子の熱膨張
係数とメタライズ金属層又はセラミックとの熱膨張係数
の相違により発生する応力が印加されると該応力が前記
絶縁基体に内在する応力と相位って大となり、絶縁基体
にクラックや割れを発生してしまい、その結果、パフケ
ージ内部に収容する半導体素子の気密が容易に破れ、半
導体素子を長期間にわたり、正常、且つ安定に作動させ
ることができないという欠点を有していた。That is, a metal paste consisting of metal powders such as tungsten (-) and molybdenum (No) is printed and coated on an unfired ceramic body to a thickness of 20 μ- or more, and then this is heated at about 1500°C in a reducing atmosphere. Ceramic work body with metallized metal layer and metalized lead by firing at high temperature (
When obtaining an insulating substrate), the ceramic is
Since the thermal expansion coefficient is different from that of the metallized metal layer such as molybdenum (Mo), stress is generated between the two due to the difference in thermal expansion coefficient, and this stress is inherent in the insulating base. Therefore, when a semiconductor element is attached and fixed on the metallized metal layer of this insulating base through a brazing material such as gold-silicon (Au-5i), the coefficient of thermal expansion of the semiconductor element and that of the metallized metal layer or ceramic on the insulating base are different. When stress generated due to the difference in thermal expansion coefficients is applied, this stress increases in phase with the stress inherent in the insulating base, causing cracks and fractures in the insulating base, and as a result, the insulating base is accommodated inside the puff cage. This has the drawback that the airtightness of the semiconductor device is easily broken, making it impossible to operate the semiconductor device normally and stably for a long period of time.
（発明の目的）
本発明は上記欠点に鑑み案出されたものでその目的は、
絶縁基体内に内在する応力を小とし、絶縁基体に半導体
素子を取着固定する際の応力が印加されたとしても絶縁
基体にクランクや割れが発生するのを皆無となし、内部
に収容する半導体素子を長期間にわたり正常、かつ安定
に作動させることができる半導体素子収納用パッケージ
を提供することにある。(Object of the invention) The present invention was devised in view of the above-mentioned drawbacks, and its object is to:
The stress inherent in the insulating base is minimized, and even if the stress is applied when attaching and fixing the semiconductor element to the insulating base, there will be no cracking or cracking in the insulating base, and the semiconductor housed inside the insulating base will be completely free of cracks or cracks. It is an object of the present invention to provide a package for housing a semiconductor element that allows the element to operate normally and stably for a long period of time.
（課題を解決するための手段）
本発明は半導体素子を収容するための凹部及び該凹部底
面に半導体素子を取着するためのメタライズ金属層をを
する絶縁基体と蓋体とから成る半導体素子収納用パッケ
ージにおいて、前記絶縁基体の凹部底面に設けたメタラ
イズ金属層の厚みを１５μ−以下としたことを特徴とす
るものである。(Means for Solving the Problems) The present invention provides a semiconductor device housing comprising a recess for accommodating a semiconductor element, an insulating base and a lid having a metallized metal layer for attaching the semiconductor element to the bottom of the recess. The package is characterized in that the metallized metal layer provided on the bottom surface of the recess of the insulating substrate has a thickness of 15 μm or less.
（実施例）
次に本発明にかかる半導体素子収納用パッケージをリー
ドレスのパッケージ（チップキャリア）を例に採って詳
細に説明する。(Example) Next, a semiconductor element storage package according to the present invention will be described in detail by taking a leadless package (chip carrier) as an example.
第１図は本発明の半導体素子収納用パッケージの一実施
例を示し、１はアルミナセラミック等の電気絶縁材料か
ら成る絶縁基体、２は蓋体である。FIG. 1 shows an embodiment of the semiconductor element storage package of the present invention, in which 1 is an insulating base made of an electrically insulating material such as alumina ceramic, and 2 is a lid.
この絶縁基体１と蓋体２とで半導体素子を収容するため
の容器を構成する。This insulating base 1 and lid 2 constitute a container for accommodating a semiconductor element.
前記絶縁基体１はその上面中央部に半導体素子を収容す
るための空所を形成する段状の凹部を有しており、該凹
部底面にはメタライズ金属層３が被着形成されている。The insulating substrate 1 has a stepped recess in the center of its upper surface forming a cavity for accommodating a semiconductor element, and a metallized metal layer 3 is deposited on the bottom surface of the recess.
前記絶縁基体１の凹部底面に設けたメタライズ金属層３
上には半導体素子４がロウ材を介し取着され、固定され
る。a metallized metal layer 3 provided on the bottom surface of the recess of the insulating substrate 1;
A semiconductor element 4 is attached and fixed thereon via a brazing material.
また前記絶縁基体ｌには凹部段状上面から側面を介し底
面にかけて導出しているメタライズリード５が形成され
ており、メタライズリード５の凹部段状上面部には半導
体素子４の電極がボンディングワイヤ６を介し電気的に
接続され、またメタライズリード５の基体１底面部は外
部電気回路の配線導体に半田等のロウ材を介しロウ付け
される。Further, a metallized lead 5 is formed on the insulating base l, extending from the stepped upper surface of the recess through the side surface to the bottom surface, and the electrode of the semiconductor element 4 is connected to the bonding wire 6 on the stepped upper surface of the recessed portion of the metallized lead 5. The bottom surface of the base 1 of the metallized lead 5 is brazed to a wiring conductor of an external electric circuit using a brazing material such as solder.
前記絶縁基体１、メタライズ金属Ｎ３及びメタライズリ
ート５は表面に金属ペーストを印刷塗布した未焼成セラ
ミツクシート（グリーンシート）を複数枚積層するとと
もに還元性雰囲気中（Ｈ！−Ｎ！ガス中）、約１４００
〜１６００℃の高温で焼成することによって形成される
。The insulating substrate 1, the metallized metal N3, and the metallized REET 5 are made by laminating a plurality of unfired ceramic sheets (green sheets) whose surfaces are coated with a printed metal paste, and are heated in a reducing atmosphere (H!-N! gas) to approx. 1400
It is formed by firing at a high temperature of ~1600°C.
尚、前記未焼成セラミツクシートはアルミナ（八１１０
３） 、シリカ（５ｉｆｔ）等のセラミック原料粉末に
適当な溶削、溶媒を添加混合して泥漿物を作り、これを
従来周知のドクターブレード法によりシート状となすこ
とによって形成され、また金属ペーストはタングステン
（−）、モリブデン（Ｍｏ） 、マンガン（Ｍｎ）等の
高融点金属粉末に適当な溶剤、溶媒を添加混合すること
によって作成され、未焼成セラミツクシートの表面には
従来周知のスクリーン印刷等の厚膜手法を採用すること
によって印刷塗布される。The unfired ceramic sheet is made of alumina (8110
3) It is formed by appropriately melting and mixing a ceramic raw material powder such as silica (5ift), adding a solvent, and forming a slurry into a sheet using the conventionally well-known doctor blade method. is created by adding and mixing a suitable solvent to high melting point metal powder such as tungsten (-), molybdenum (Mo), manganese (Mn), etc., and the surface of the unfired ceramic sheet is coated with conventionally well-known screen printing etc. Printing is applied by adopting a thick film technique.
前記絶縁基体１の凹部底面に被着形成されるメタライズ
金属層３はその厚みが１５μ−以下であり、厚みが薄い
ことから未焼成セラミツクシートに金属ペーストを印刷
塗布し、しかる後、焼成してメタライズ金属Ｎ３を有す
る絶縁基体１を得る場合、セラミックとモリブデン、タ
ングステン等との熱膨張係数の相違により発生する応力
は極めて小さいものであり、絶縁基体１内に大きな応力
が内在することはない。従って、絶縁基体ｌのメタライ
ズ金属層３上に半導体素子４をロウ材を介し取着固定す
る際、絶縁基体に半導体素子とメタライズ金属層３又は
セラミック体との熱膨張係数の相違により発生する応力
が印加されたとしても該応力が前記絶縁基体に内在する
応力と相位って大となることはなく、絶縁基体１にクラ
７クや割れ等が発生することもない。The metallized metal layer 3 formed on the bottom surface of the recess of the insulating substrate 1 has a thickness of 15 μm or less, and since it is thin, a metal paste is printed and coated on an unfired ceramic sheet, and then fired. When obtaining the insulating substrate 1 having the metallized metal N3, the stress generated due to the difference in thermal expansion coefficient between ceramic and molybdenum, tungsten, etc. is extremely small, and no large stress is inherent in the insulating substrate 1. Therefore, when attaching and fixing the semiconductor element 4 to the metallized metal layer 3 of the insulating base l via a brazing material, stress is generated on the insulating base due to the difference in coefficient of thermal expansion between the semiconductor element and the metallized metal layer 3 or the ceramic body. Even if the stress is applied, the stress will not be as large as the stress inherent in the insulating base 1, and cracks, cracks, etc. will not occur in the insulating base 1.
尚、前記絶縁基体１の凹部底面に被着形成するメタライ
ズ金属層３の厚みを１５μＩ以下とするには未焼成セラ
ミツクシートに金属ペーストをスクリーン印刷法により
印刷塗布する際、スクリーンのレジスト厚みを薄くした
り、金属ペーストの粘度を小さ（することによって調節
される。Incidentally, in order to make the thickness of the metallized metal layer 3 formed on the bottom surface of the recess of the insulating substrate 1 to be 15 μI or less, when applying the metal paste to the unfired ceramic sheet by screen printing method, the resist thickness of the screen is thinned. It can be adjusted by reducing the viscosity of the metal paste.
また前記絶縁基体１に設けたメタライズ金属層３及びメ
タライズリード５は、メタライズ金属層３上に半導体素
子４を強固に取着固定するために、またメタライズリー
ド５と外部電気回路との電気的接続を良好とし、かつメ
タライズリード５が酸化腐蝕するのを防止するために、
その外表面にニッケル（Ｎｉ）及び金（Ａｕ）がメツキ
により層着されている。Further, the metallized metal layer 3 and the metallized leads 5 provided on the insulating substrate 1 are used for firmly attaching and fixing the semiconductor element 4 on the metallized metal layer 3, and for electrical connection between the metallized lead 5 and an external electric circuit. In order to improve the quality and prevent the metallized lead 5 from being oxidized and corroded,
Nickel (Ni) and gold (Au) are layered on its outer surface by plating.
かくして前記絶縁基体１の凹部底面に設けたメタライズ
金属層３に半導体素子４を金−シリコン（Ａｕ−Ｓｔ）
等のロウ材を介し取着固定するとともに半導体素子の各
電極をメタライズリード５にボンディングワイヤ６を介
して電気的に接続し、しかる後、絶縁基体ｌの上面に蓋
体２を接着材により取着し、容器の内部を気密に封止す
ることによって最終製品である半導体装置となる。Thus, the semiconductor element 4 is formed of gold-silicon (Au-St) on the metallized metal layer 3 provided on the bottom surface of the recess of the insulating substrate 1.
At the same time, each electrode of the semiconductor element is electrically connected to the metallized lead 5 via a bonding wire 6, and then the lid body 2 is attached to the upper surface of the insulating base l using an adhesive. The final product, the semiconductor device, is obtained by attaching the container and hermetically sealing the inside of the container.
尚、前記蓋体２は金属板、あるいは絶縁基体１と同様の
セラミックス板から成り、セラミック板から成る場合に
は、例えばセラミックスの粉末を従来周知のプレス成形
法を採用することによって絶縁基体１の凹部を塞ぐ大き
さの板状に成形するとともにこれを高温で焼成すること
によって形成される。Note that the lid 2 is made of a metal plate or a ceramic plate similar to the insulating base 1, and when it is made of a ceramic plate, the insulating base 1 is formed by, for example, using a known press molding method with ceramic powder. It is formed by molding it into a plate shape large enough to close the recess and firing it at a high temperature.
（実験例）
次ぎに本発明の作用効果を下記に示す実験例に基づいて
説明する。(Experimental Example) Next, the effects of the present invention will be explained based on the experimental example shown below.
まずアルミナ（ＡｈＯｓ）セラミックスから成る未焼成
セラミツクシートにタングステン（−）の粉末を用いた
金属ペーストを所定パターンに印刷塗布し、これを複数
枚積層するとともに約１５００℃の温度で焼成して第１
図に示す様な凹部底面にメタライズ金属層を被着形成し
た構造の半導体素子収納用バフケージの絶縁基体を作成
する。First, a metal paste using tungsten (-) powder is printed and coated in a predetermined pattern on an unfired ceramic sheet made of alumina (AhOs) ceramics.
An insulating base of a buff cage for housing a semiconductor element having a structure in which a metallized metal layer is deposited on the bottom surface of a recess as shown in the figure is prepared.
尚、この際、半導体素子が取着固定されるメタライズ金
属層の厚みは第１表に示す夫々の厚みとし、これらを１
００個づつ作って実験試料とした。At this time, the thickness of the metallized metal layer to which the semiconductor element is attached and fixed shall be as shown in Table 1, and these shall be 1
00 pieces were made and used as experimental samples.
次に前記絶縁基体のメタライズ金属層上に金−シリコン
（Ａｕ−Ｓｔ）から成るロウ材及びシリコン半導体素子
を載置するとともにこれを４５０℃に設定されたヒータ
ーブロック上に置き、ロウ材を加熱溶融させて半導体素
子をメタライズ金属層上にロウ付けする。Next, a brazing material made of gold-silicon (Au-St) and a silicon semiconductor element are placed on the metallized metal layer of the insulating base, and this is placed on a heater block set at 450°C to heat the brazing material. The semiconductor element is melted and brazed onto the metallized metal layer.
尚、前記絶縁基体に設けたメタライズ金属層の外表面に
は該メタライズ金属層と半導体素子との接合を良好とす
るためにニッケル（Ｎｉ）及び金（Ａｕ）をメツキによ
り層着した。Incidentally, nickel (Ni) and gold (Au) were layered on the outer surface of the metallized metal layer provided on the insulating substrate by plating in order to improve the bonding between the metallized metal layer and the semiconductor element.
そして次ぎに前記絶縁基体の上面にコバール（Ｆｅ−Ｎ
ｉ−Ｃｏ合金）から成る金属製の蓋体を接着材を介し接
着し、パッケージの内部を気密に封止するとともにヘリ
ウムリークディテクターでパフケージ内部の気密性を検
査し、気密が破れているものの数を数え、これを不良率
として算出した。Then, Kovar (Fe-N
A metal lid made of i-Co alloy is bonded with an adhesive to airtightly seal the inside of the package, and a helium leak detector is used to test the airtightness of the inside of the puff cage, and the number of cases where the airtightness is broken is determined. This was calculated as the defective rate.
その結果を第１表に示す。The results are shown in Table 1.
第
表
＊印を付した試料番号のものは本発明の範囲外のもので
ある。Sample numbers marked with * in the table are outside the scope of the present invention.
（発明の効果）
上記実験結果からも判るように、絶縁基体の凹部底面に
設けたメタライズ金属層の厚みが１８μ−を越えるもの
（試料番号５及び６）は絶縁基体内に内在している応力
が大きいためメタライズ金属層上に半導体素子をロウ付
けするとその際の応力が前記ｍ、ｉ基体内に内在する応
力と相位って大となり、絶縁基体にクランクや割れを発
生させて３３％以上のパッケージに気密不良を招来させ
てしまうのに対し、本発明のもの、即ち、メタライズ金
属層の厚みが１５μ麟以下であるものは絶縁基体内に内
在する応力が小さく、半導体素子をロウ付けする際に応
力が印加されても絶縁基体にクラックや割れ等を発生す
ることはな（パッケージ内部に半導体素子を気密に封止
するのを可能として半導体素子を長期間にわたり正常、
且つ安定に作動させることができる。(Effects of the Invention) As can be seen from the above experimental results, the thickness of the metallized metal layer provided on the bottom surface of the recess of the insulating substrate exceeds 18 μ- (sample numbers 5 and 6) due to the stress inherent in the insulating substrate. is large, so when a semiconductor element is brazed onto a metallized metal layer, the stress at that time becomes as large as the stress inherent in the substrate m and i, causing cranks and cracks in the insulating substrate, resulting in a loss of 33% or more. In contrast, the present invention, in which the metallized metal layer has a thickness of 15 μm or less, has less stress within the insulating substrate, making it easier to solder semiconductor elements when soldering. Even if stress is applied to the insulating substrate, no cracks or cracks will occur in the insulating substrate.
Moreover, it can be operated stably.
第１図は本発明にかかる半導体素子収納用パッケージの
一実施例を示す断面図である。
１：絶縁基体 ２：蓋体
３：メタライズ金属層
５：メタライズリード
ょＡか人
（ｔｌ＞）餉り卓す≧FIG. 1 is a sectional view showing an embodiment of a semiconductor element storage package according to the present invention. 1: Insulating base 2: Lid 3: Metallized metal layer 5: Metallized lead
Claims (1)
体素子を取着するためのメタライズ金属層を有する絶縁
基体と蓋体とから成る半導体素子収納用パッケージにお
いて、前記絶縁基体の凹部底面に設けたメタライズ金属
層の厚みを１５μｍ以下としたことを特徴とする半導体
素子収納用パッケージ。In a package for storing a semiconductor element, which comprises an insulating base and a lid body, each having a recess for accommodating a semiconductor element and a metallized metal layer for attaching the semiconductor element to the bottom surface of the recess, the package is provided on the bottom surface of the recess of the insulating base. A package for storing semiconductor elements, characterized in that the thickness of the metallized metal layer is 15 μm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63294159A JP2866962B2 (en) | 1988-11-21 | 1988-11-21 | Manufacturing method of semiconductor device storage package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63294159A JP2866962B2 (en) | 1988-11-21 | 1988-11-21 | Manufacturing method of semiconductor device storage package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02139951A true JPH02139951A (en) | 1990-05-29 |
| JP2866962B2 JP2866962B2 (en) | 1999-03-08 |
Family
ID=17804078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63294159A Expired - Lifetime JP2866962B2 (en) | 1988-11-21 | 1988-11-21 | Manufacturing method of semiconductor device storage package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2866962B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6342148A (en) * | 1986-08-07 | 1988-02-23 | Showa Denko Kk | Conductive sheet and metallizing method using said sheet |
| JPS63137574A (en) * | 1986-11-27 | 1988-06-09 | Kyocera Corp | Surface covering structure for metallized metal layer |
-
1988
- 1988-11-21 JP JP63294159A patent/JP2866962B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6342148A (en) * | 1986-08-07 | 1988-02-23 | Showa Denko Kk | Conductive sheet and metallizing method using said sheet |
| JPS63137574A (en) * | 1986-11-27 | 1988-06-09 | Kyocera Corp | Surface covering structure for metallized metal layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2866962B2 (en) | 1999-03-08 |
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