JP2604621B2 - Manufacturing method of semiconductor device storage package - Google Patents

Manufacturing method of semiconductor device storage package

Info

Publication number
JP2604621B2
JP2604621B2 JP63068885A JP6888588A JP2604621B2 JP 2604621 B2 JP2604621 B2 JP 2604621B2 JP 63068885 A JP63068885 A JP 63068885A JP 6888588 A JP6888588 A JP 6888588A JP 2604621 B2 JP2604621 B2 JP 2604621B2
Authority
JP
Japan
Prior art keywords
convex portion
metal
semiconductor element
metal base
insulating frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63068885A
Other languages
Japanese (ja)
Other versions
JPH01239959A (en
Inventor
正則 白鳥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP63068885A priority Critical patent/JP2604621B2/en
Publication of JPH01239959A publication Critical patent/JPH01239959A/en
Application granted granted Critical
Publication of JP2604621B2 publication Critical patent/JP2604621B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子、特に半導体集積回路素子を収容
する半導体素子収納用パッケージの製造方法に関するも
のである。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, particularly a package for housing a semiconductor device for housing a semiconductor integrated circuit device.

〔従来の技術〕[Conventional technology]

近時、情報処理装置の高性能化、高速度化に伴い、そ
れを構成する半導体素子も高密度、高集積化が急激に進
んでいる。そのため半導体素子の単位面積、単位体積あ
たりの発熱量が増大し、半導体素子を正常に、かつ安定
に作動させるためにはその熱をいかに効率的に除去する
かが課題となっている。
2. Description of the Related Art In recent years, as information processing apparatuses have become higher in performance and higher in speed, semiconductor elements constituting the information processing apparatuses have been rapidly increasing in density and integration. Therefore, the amount of heat generated per unit area and unit volume of the semiconductor element increases, and how to efficiently remove the heat has been a problem in order to operate the semiconductor element normally and stably.

従来、半導体素子の発生する除去方法としては第3図
に示すように中央部に凸部12を有する金属基体11上に、
前記凸部12を囲繞するようにして絶縁枠体13をロウ付け
取着した構造の半導体素子収納用パッケージを準備し、
金属基体11の凸部12上面に半導体素子14を載置して半導
体素子14から発生される熱を金属基体11に吸収させると
ともに該吸収した熱を大気中に放出することによって行
われている。
Conventionally, as a method of removing a semiconductor element, as shown in FIG.
Prepare a semiconductor element storage package having a structure in which the insulating frame 13 is brazed and attached so as to surround the convex portion 12,
This is performed by placing the semiconductor element 14 on the upper surface of the convex portion 12 of the metal base 11, absorbing the heat generated from the semiconductor element 14 to the metal base 11, and releasing the absorbed heat to the atmosphere.

尚、前記半導体素子収納用パッケージにおいて、金属
基体11は、上面に取着される絶縁枠体13との間に熱応力
が発生しないように熱膨張係数が絶縁枠体13と近似する
銅−タングステン合金より形成され、その外表面には絶
縁枠体13をロウ付け取着する際のロウ材が強固に接合す
るようにロウ材と濡れ性が良い、例えばニッケル(Ni)
等かな成る金属層15がめっきにより層着されている。
In the semiconductor element housing package, the metal base 11 is made of copper-tungsten whose thermal expansion coefficient is close to that of the insulating frame 13 so that thermal stress does not occur between the metal base 11 and the insulating frame 13 attached to the upper surface. It is made of an alloy, and has good wettability with the brazing material so that the brazing material when the insulating frame 13 is brazed and attached to the outer surface is firmly joined to the outer surface, for example, nickel (Ni)
An even metal layer 15 is deposited by plating.

また前記絶縁枠体13はその下面にモリブデン(Mo)、
マンガン(Mn)、タングステン(W)等の高融点金属か
ら成るメタライズ金属層16が被着形成されており、該メ
タライズ金属層16を金属基体11に銀ロウ(銀−銅合金)
等のロウ材17を介しロウ付けすることによって絶縁枠体
13は金属基体11上に取着される。
The insulating frame 13 has molybdenum (Mo) on its lower surface,
A metallized metal layer 16 made of a refractory metal such as manganese (Mn), tungsten (W) or the like is formed on the metal substrate 11, and the metallized metal layer 16 is formed on a metal substrate 11 by silver brazing (silver-copper alloy).
Insulation frame by brazing through brazing material 17 such as
13 is attached on the metal base 11.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかし乍ら、この従来の半導体素子収納用パッケージ
は、金属基体11の外表面全面、即ち、半導体素子14が載
置される凸部上面を含むすべての外表面にロウ材と濡れ
性(接合性)の良い金属層15が層着されていること及び
金属基体11の凸部側面と絶縁枠体13の内周面との間に両
者の熱膨張係数の若干の相違に起因して発生する応力を
有効に吸収するために通常、0.5mm程度の間隙が形成さ
れていること等から金属基体11上に絶縁枠体13をロウ材
17を介しロウ付けする際、熔融したロウ材17の一部が前
記間隙内を毛管現象により這い上がり、金属基体11の凸
部上面に流出付着して表面を粗面となし、その結果、金
属基体の凸部上面に半導体素子を強固に取着することが
できなかったり、半導体素子が金属基体の凸部上面に傾
斜をもって取着され、半導体素子の各電極を外部リード
ピンに接続するワイヤボンディングの作業ができなくな
ったりするという欠点を有していた。
However, in this conventional package for housing a semiconductor element, the entire surface of the outer surface of the metal base 11, that is, the entire outer surface including the upper surface of the convex portion on which the semiconductor element 14 is mounted, has wettability (bonding property). A) a metal layer 15 having good adhesion, and a stress generated due to a slight difference in the thermal expansion coefficient between the convex side surface of the metal base 11 and the inner peripheral surface of the insulating frame 13. Usually, a gap of about 0.5 mm is formed in order to effectively absorb
At the time of brazing through 17, a part of the molten brazing material 17 creeps up in the gap by capillary action, flows out and adheres to the upper surface of the convex portion of the metal base 11, and the surface becomes rough, and as a result, the metal The semiconductor element cannot be firmly attached to the upper surface of the convex portion of the base, or the semiconductor device is attached with an inclination to the upper surface of the convex portion of the metal substrate, and wire bonding for connecting each electrode of the semiconductor element to an external lead pin is used. There was a disadvantage that work could not be performed.

〔発明の目的〕[Object of the invention]

本発明は上記欠点に鑑み案出されたもので、その目的
は金属基体の上面に絶縁枠体を強固にロウ付けするのを
可能とし、かつ金属基体の凸部上面に絶縁枠体をロウ付
けするためのロウ材が流出付着するのを皆無となし、金
属基体の凸部上面に半導体素子を強固に取着させること
ができるとともに半導体素子の各電極を外部リードピン
の各々に確実に接続させることができる半導体素子収納
用パッケージの製造方法を提供することにある。
The present invention has been devised in view of the above drawbacks, and has as its object to enable an insulating frame to be firmly brazed to the upper surface of a metal substrate, and to braze the insulating frame to the upper surface of the convex portion of the metal substrate. The semiconductor device can be firmly attached to the upper surface of the convex portion of the metal base, and each electrode of the semiconductor device can be securely connected to each of the external lead pins. It is an object of the present invention to provide a method for manufacturing a semiconductor device storage package that can be manufactured.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の半導体素子収納用パッケージの製造方法は、
中央部に半導体素子が載置される凸部を有し、かつ外表
面にロウ材と接合性が良い金属層を層着させた金属基体
と電気絶縁材料から成る枠体とを準備し、 前記金属基体の凸部側面もしくは上側面に耐熱性、非
ロウ材接合性に優れた被覆層を披着させ、 次いで前記金属基体上に、該基体に設けた凸部を囲繞
するようにして絶縁枠体をロウ付けし、 しかる後、前記被覆層を金属基体の凸部より剥離させ
除去することを特徴とするものである。
The method for manufacturing a semiconductor element storage package according to the present invention includes:
A metal substrate having a convex portion on which the semiconductor element is mounted at the center, and a metal layer having good bonding properties with the brazing material on the outer surface, and a frame made of an electrically insulating material, A covering layer having excellent heat resistance and non-brazing material bonding properties is deposited on the side or upper side of the convex portion of the metal substrate, and then the insulating frame is formed on the metal substrate so as to surround the convex portion provided on the substrate. The method is characterized in that the body is brazed, and thereafter, the coating layer is peeled off from the projections of the metal base and removed.

〔実施例〕〔Example〕

次に本発明を第1図に示す実施例に基づき詳細に説明
する。
Next, the present invention will be described in detail based on the embodiment shown in FIG.

第1図は本発明の製造方法によって製作された半導体
素子収納用パッケージの一実施例を示し、1は金属基
体、2は絶縁枠体である。
FIG. 1 shows an embodiment of a semiconductor device housing package manufactured by the manufacturing method of the present invention, wherein 1 is a metal base, and 2 is an insulating frame.

前記金属基体1はその上面中央部に凸部1aが設けてあ
り、該凸部1aの上には半導体素子が接着材を介し取着さ
れる。
The metal base 1 is provided with a convex portion 1a at the center of the upper surface, and a semiconductor element is mounted on the convex portion 1a via an adhesive.

前記金属基体1は半導体素子が発する熱を直接伝導吸
収するとともに該吸収した熱を大気中に放出する作用を
為し、後述する絶縁枠体2との間に大きな熱応力が発生
しないよう熱膨張係数が絶縁枠体2と近似し、かつ良熱
伝導性である材料、即ち銅−タングステン合金(Cu−W
合金)より形成されている。
The metal base 1 functions to directly conduct and absorb the heat generated by the semiconductor element and to release the absorbed heat to the atmosphere, so that thermal expansion does not occur between the metal base 1 and the insulating frame 2 described later. A material having a coefficient close to that of the insulating frame 2 and having good thermal conductivity, that is, a copper-tungsten alloy (Cu-W
Alloy).

尚、前記金属基体1は、例えばタングステンの粉末
(約10μm)を1000Kg/cm2の圧力で加圧成形するととも
にこれを還元雰囲気中、約2300℃の温度で焼成して多孔
質のタングステン焼結体を得、次に1100℃の温度で加熱
熔融させた銅を前記タングステン焼結体の多孔部に毛管
現象を利用して含浸させることによって形成される。
The metal substrate 1 is formed, for example, by pressing tungsten powder (about 10 μm) at a pressure of 1000 kg / cm 2 and firing it at a temperature of about 2300 ° C. in a reducing atmosphere to form a porous tungsten sintered body. A body is obtained, and then formed by impregnating the porous portion of the tungsten sintered body with copper heated and melted at a temperature of 1100 ° C. using a capillary phenomenon.

また前記金属基体1はその外表面全面にロウ材と濡れ
性(接合性)が良く、耐蝕性に優れたニッケル(Ni)等
から成る金属層1bが従来周知の無電解めっき法や電解め
っき法により層着されている。この金属層1bは後述する
絶縁枠体2を金属基体1にロウ付けする際のロウ材と金
属基体1との接合強度を大となすとともに金属基体1が
酸化を受けて腐蝕するのを防止する作用を為す。
The metal substrate 1 has a metal layer 1b made of nickel (Ni) or the like having excellent wettability (bonding property) and excellent corrosion resistance on the entire outer surface of the metal substrate 1 by a conventionally known electroless plating method or electrolytic plating method. Is layered. The metal layer 1b increases the bonding strength between the brazing material and the metal base 1 when brazing an insulating frame 2 to be described later to the metal base 1, and prevents the metal base 1 from being oxidized and corroded. Works.

前記金属層1bは、例えば無電解めっき法により層着さ
せる場合、まず金属基体1を塩化アンミンパラジウム2g
/、エチレンジアミンテトラアセティックアシッド(E
DTA)10g/、水酸化ナトリウム100g/から成る液温70
℃の活性液中に5〜10分間浸漬させて活性化処理をする
とともに硫酸ニッケル30g/、クエン酸ナトリウム10g/
、コハク酸ナトリウム20g/、酢酸ナトリウム20g/
、ジメチルアミンボラン3g/から成る液温65℃のニ
ッケルめっき液中に約10分間浸漬させてニッケルを析出
被着させることによって金属基体1の外表面全面に層着
される。
When the metal layer 1b is deposited by, for example, an electroless plating method, first, the metal substrate 1 is coated with 2 g of ammine palladium chloride.
/, Ethylenediaminetetraacetic acid (E
DTA) 10 g /, sodium hydroxide 100 g / liquid temperature 70
Activated by immersing in an active solution at 5 ° C. for 5 to 10 minutes and nickel sulfate 30 g / sodium citrate 10 g /
, Sodium succinate 20g /, sodium acetate 20g /
Then, the substrate is immersed in a nickel plating solution of 3 g / dimethylamine borane at a temperature of 65 ° C. for about 10 minutes to deposit and deposit nickel, thereby forming a layer on the entire outer surface of the metal substrate 1.

前記金属基体1の上面外周端には金属基体1の上面に
設けた凸部1aを囲繞するようにして絶縁枠体2が取着さ
れており、金属基体1と絶縁枠体2とで半導体素子3を
収容するための空所が内部に形成される。
An insulating frame 2 is attached to the outer peripheral edge of the upper surface of the metal substrate 1 so as to surround the convex portion 1a provided on the upper surface of the metal substrate 1. The metal substrate 1 and the insulating frame 2 A space for accommodating 3 is formed therein.

前記絶縁枠体2は例えばアルミナセラミックスから成
り、アルミナセラミックスの粉末に適当な有機溶剤、溶
媒を添加して泥漿状となすとともにこれをドクターブレ
ード法を採用することによってグリーンシート(生シー
ト)を形成し、しかる後、前記グリーンシートに適当な
打抜き加工を施すとともに複数枚積層し、高温で焼成す
ることによって製作される。
The insulating frame 2 is made of, for example, alumina ceramics. A green sheet (raw sheet) is formed by adding a suitable organic solvent and a solvent to alumina ceramic powder to form a slurry and employing a doctor blade method. Thereafter, the green sheet is manufactured by subjecting the green sheet to an appropriate punching process, laminating a plurality of sheets, and firing at a high temperature.

また、前記絶縁枠体2はその下面にタングステン、モ
リブデン等の金属から成るメタライズ金属層8が被着さ
れており、該メタライズ金属層8と金属基体1とを銀ロ
ウ(銀−銅合金)等のロウ材9を介しロウ付けすること
によって金属基体1上に取着される。
A metallized metal layer 8 made of a metal such as tungsten or molybdenum is adhered on the lower surface of the insulating frame 2, and the metallized metal layer 8 and the metal substrate 1 are formed by silver brazing (silver-copper alloy) or the like. Is attached onto the metal substrate 1 by brazing through the brazing material 9.

尚、この場合、金属基体1の外表面にはロウ材と濡れ
性(接合性)が良い金属層1bが層着されていることから
ロウ材9と金属層1b及びメタライズ金属層8との接合強
度を大となすことができ、これによって金属基体1上に
絶縁枠体2を強固に取着することが可能となる。
In this case, since the metal layer 1b having good wettability (bonding property) with the brazing material is layered on the outer surface of the metal base 1, the joining of the brazing material 9 with the metal layer 1b and the metallized metal layer 8 is performed. The strength can be increased, so that the insulating frame 2 can be firmly attached on the metal base 1.

前記絶縁枠体2はまたその内部にモリブデン(Mo)、
タングステン(W)等の金属から成る導電層4が設けて
あり、該導電層4は半導体素子3の電極をリードピン5
に接続する作用を為し、その一端に外部リードピン5
が、また他端に半導体素子3の電極に接続されたワイヤ
6が取着される。
The insulating frame 2 also has molybdenum (Mo) therein.
A conductive layer 4 made of a metal such as tungsten (W) is provided. The conductive layer 4 connects an electrode of the semiconductor element 3 to a lead pin 5.
To the external lead pin 5 at one end.
However, a wire 6 connected to the electrode of the semiconductor element 3 is attached to the other end.

前記絶縁枠体2に設けた導電層4に取着される外部リ
ードピン5は内部に収容する半導体素子3の各電極を外
部回路に接続する作用を為し、コバール(Fe−Ni−Co合
金)や42Alloy等の金属をピン状に成したものが使用さ
れる。
The external lead pins 5 attached to the conductive layer 4 provided on the insulating frame 2 serve to connect each electrode of the semiconductor element 3 housed therein to an external circuit, and are made of Kovar (Fe-Ni-Co alloy). A pin made of a metal such as or 42Alloy is used.

尚、前記外部リードピン5の外表面には該外部リード
ピン5と外部回路との電気的接続を良好とするために、
また外部リードピン5が酸化腐蝕するのを防止するため
にニッケル(Ni)、金(Au)等から成る良導電性で、か
つ耐蝕性に優れた金属を従来周知のめっき法により披着
させておくことが望ましい。
In order to improve the electrical connection between the external lead pins 5 and an external circuit,
In order to prevent the external lead pins 5 from being oxidized and corroded, a metal having good conductivity and excellent corrosion resistance made of nickel (Ni), gold (Au) or the like is deposited by a conventionally known plating method. It is desirable.

また前記絶縁枠体2の上面には蓋体7がガラス、樹脂
等の接着剤を介して取着され、これによって半導体素子
収納用パッケージの内部が完全に気密に封止される。
Further, a lid 7 is attached to the upper surface of the insulating frame 2 via an adhesive such as glass or resin, whereby the inside of the semiconductor element housing package is completely hermetically sealed.

かくして絶縁枠体2が取着された金属基体1の凸部1a
上に半導体素子3を取着し、半導体素子3の各電極をワ
イヤ6を介して導電層4に接続するとともに蓋体7を絶
縁枠体2の上面に取着することによって最終製品である
半導体装置となる。
Thus, the protrusion 1a of the metal base 1 to which the insulating frame 2 is attached.
The semiconductor element 3 is mounted thereon, and the electrodes of the semiconductor element 3 are connected to the conductive layer 4 via wires 6 and the lid 7 is attached to the upper surface of the insulating frame 2 to thereby obtain a semiconductor as a final product. Device.

次に本発明の半導体素子収納用パッケージの製造方法
について説明する。
Next, a method for manufacturing the semiconductor device housing package of the present invention will be described.

まず、第2図(a)に示すように中央部に半導体素子
が載置される凸部1aを有し、外表面にロウ材との濡れ性
(接合性)が良い金属層1bが層着されて成る金属基体1
を準備する。
First, as shown in FIG. 2 (a), a metal layer 1b having a good wettability (bonding property) with a brazing material is deposited on the outer surface of the semiconductor device having a convex portion 1a on which a semiconductor element is mounted at the center. Metal substrate 1 formed
Prepare

次に第2図(b)に示す如く、金属基体1の凸部1a側
面に耐熱性に優れ、かつ非ロウ材接合性(ロウ材との濡
れ性が悪い)である被覆層10を被着させる。この被覆層
10は後述する絶縁枠体2を金属基体1上にロウ付けする
際、ロウ材が金属基体1の凸部1aの側面を這い上がり、
凸部上面に流出付着するのを防止する作用を為す。
Next, as shown in FIG. 2 (b), a coating layer 10 having excellent heat resistance and non-brazing material bonding property (poor wettability with brazing material) is applied to the side surface of the convex portion 1a of the metal substrate 1. Let it. This coating layer
When brazing an insulating frame 2 to be described later on the metal base 1, the brazing material creeps up the side surface of the convex portion 1 a of the metal base 1,
It functions to prevent the outflow and adhesion to the upper surface of the convex portion.

前記被覆層10はアルミナセラミックス等の無機物が好
適に使用され、例えばアルミナセラミックスの粉末に適
当な有機溶剤、溶媒を添加混合してペースト状と成し、
該ペーストを金属基体1の凸部1a側面に印刷塗布すると
ともに約100℃の温度で乾燥焼成することによって金属
基体1の凸部1a側面に披着される。
The coating layer 10 is preferably made of an inorganic material such as alumina ceramics.For example, an organic solvent suitable for alumina ceramic powder, a solvent is added and mixed to form a paste,
The paste is printed on the side surface of the convex portion 1a of the metal substrate 1 and dried and fired at a temperature of about 100 ° C. to be deposited on the side surface of the convex portion 1a of the metal substrate 1.

尚、前記アルミナセラミックスから成る被覆層10はそ
の金属基体1の凸部1a側面との接合強度が弱く、外力印
加によって凸部1a側面より容易に剥離させることができ
る。
The coating layer 10 made of alumina ceramics has a low bonding strength with the side surface of the convex portion 1a of the metal base 1, and can be easily separated from the side surface of the convex portion 1a by applying an external force.

また前記被覆層10は金属基体の凸部1a側面に限らず上
面及び側面の両方に被着させておいてもよい。
Further, the coating layer 10 may be applied not only to the side surface of the convex portion 1a of the metal base but also to both the upper surface and the side surface.

そして次に第2図(C)に示す如く、金属基体1上
に、該基体1に設けた凸部1aを囲繞するようにして絶縁
枠体2を載置し、両者をロウ材9を介しロウ付けする。
Then, as shown in FIG. 2 (C), the insulating frame 2 is placed on the metal base 1 so as to surround the protruding portion 1a provided on the base 1, and the insulating frame 2 is connected to the metal base 1 via the brazing material 9. Braze.

尚、このロウ付けの時、熔融したロウ材9が金属基体
1の凸部1a側面を這い上がろうとするが該凸部1a側面に
は耐熱性に優れ、かつ非ロウ材接合性(ロウ材との濡れ
性が悪い)である被覆層10が披着されていることからそ
の這い上がりが有効に阻止され、その結果、熔融したロ
ウ材が凸部1aの上面に流出付着し、凸部1aの上面を粗面
となして半導体素子の取着強度を低下させたり、傾斜を
もって取着されるようになすことは皆無となる。
At the time of this brazing, the molten brazing material 9 tends to crawl on the side surface of the convex portion 1a of the metal base 1, but the side surface of the convex portion 1a has excellent heat resistance and non-brazing material bonding property (brazing material). Is clogged up because the coating layer 10 having poor wettability is effectively prevented, and as a result, the molten brazing material flows out and adheres to the upper surface of the convex portion 1a, and the convex portion 1a There is no need to make the upper surface of the semiconductor device rough, thereby lowering the attachment strength of the semiconductor element, or to attach the semiconductor device with an inclination.

尚、前記絶縁枠体2を金属基体1上にロウ付けするロ
ウ材9としては、例えば銀ロウ(銀−銅合金)が好適に
使用され、ロウ材9の枠状体を金属基体1と絶縁枠体2
の間に挟み込むとともにこれを約900℃の温度で加熱熔
融させることによって金属基体1と絶縁枠体2とをロウ
付けする。
As the brazing material 9 for brazing the insulating frame 2 onto the metal base 1, for example, silver brazing (silver-copper alloy) is preferably used, and the frame of the brazing material 9 is insulated from the metal base 1. Frame 2
The metal base 1 and the insulating frame 2 are brazed by being sandwiched between them and heated and melted at a temperature of about 900 ° C.

そして最後に第2図(d)に示す如く、金属基体1の
凸部1a側面に披着させた被覆層10を剥離除去させ、これ
によって製品としての半導体素子収納用パッケージが完
成する。
Finally, as shown in FIG. 2 (d), the coating layer 10 deposited on the side surface of the convex portion 1a of the metal base 1 is peeled off, thereby completing a semiconductor element housing package as a product.

前記被覆層10の剥離除去としては水の入った水槽中
に、上面に絶縁枠体2がロウ付けされている金属基体1
を投入するとともに水槽の水に26〜28KHzの超音波振動
を与え、被覆層10に外部応力を印加させることによって
行われる。
The coating layer 10 is peeled and removed by placing a metal base 1 having an insulating frame 2 brazed on the upper surface thereof in a water tank filled with water.
And ultrasonic waves of 26 to 28 KHz are applied to the water in the water tank to apply an external stress to the coating layer 10.

〔発明の効果〕〔The invention's effect〕

以上の通り、本発明の製造方法によれば金属基体の半
導体素子が載置される凸部側面に耐熱性に優れ、かつ非
ロウ材接合性(ロウ材との濡れ性が悪い)である被覆層
を被着させたことから金属基体上に絶縁枠体をロウ付け
する際、熔融したロウ材が凸部側面を這い上がるのが有
効に阻止され、凸部上面にロウ材が流出付着して表面を
粗面となすことは一切ない。
As described above, according to the manufacturing method of the present invention, the coating having excellent heat resistance and non-brazing material bonding property (poor wettability with brazing material) is provided on the side surface of the convex portion of the metal substrate on which the semiconductor element is mounted. When the insulating frame is brazed on the metal base because the layer is applied, the molten brazing material is effectively prevented from creeping up the side surface of the convex portion, and the brazing material flows out and adheres to the upper surface of the convex portion. The surface is never rough.

従って、金属基体1はその凸部上面が常に平坦であ
り、半導体素子を水平、且つ強固に取着させることが可
能となる。
Therefore, the upper surface of the convex portion of the metal substrate 1 is always flat, and the semiconductor element can be horizontally and firmly attached.

また半導体素子の取着を水平となすことができること
から半導体素子の各電極と外部リードピンとの接続を自
動ワイヤーボンダーを使用して行うことができ、両者の
接続を正確、かつ確実となすことも可能となる。
In addition, since the mounting of the semiconductor element can be made horizontal, each electrode of the semiconductor element can be connected to the external lead pin using an automatic wire bonder, and the connection between them can be made accurately and securely. It becomes possible.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の製造方法によって製作された半導体素
子収納用パッケージの一実施例を示す断面図、第2図は
本発明の製造方法を説明するための各工程を示す断面
図、第3図は従来の半導体素子収納用パッケージの断面
図である。 1:金属基体、1a:凸部 1b:金属層、2:絶縁枠体 9:ろう材、10:被覆層
FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor device housing package manufactured by the manufacturing method of the present invention. FIG. 2 is a cross-sectional view showing each step for explaining the manufacturing method of the present invention. FIG. 1 is a sectional view of a conventional package for housing a semiconductor element. 1: Metal substrate, 1a: Convex part 1b: Metal layer, 2: Insulating frame 9: Brazing material, 10: Coating layer

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】中央部に半導体素子が載置される凸部を有
し、かつ外表面にロウ材と接合性が良い金属層を層着さ
せた金属基体と電気絶縁材料から成る枠体とを準備し、 前記金属基体の凸部側面もしくは上側面に耐熱性、非ロ
ウ材接合性に優れた被覆層を被着させ、 次いで前記金属基体上に、該基体に設けた凸部を囲繞す
るようにして絶縁枠体をロウ付けし、 しかる後、前記被覆層を金属基体の凸部より剥離させ除
去することを特徴とする半導体素子収納用パッケージの
製造方法。
1. A frame comprising an electrically insulating material and a metal base having a convex portion on which a semiconductor element is mounted at a center portion, and a metal layer having good bonding properties with a brazing material layered on an outer surface. Is prepared, and a coating layer having excellent heat resistance and non-brazing material bonding property is applied to the side surface or the upper side surface of the convex portion of the metal substrate. Then, the convex portion provided on the metal substrate is surrounded on the metal substrate. A method for manufacturing a package for housing a semiconductor element, comprising: brazing an insulating frame body in the above manner; and thereafter, peeling and removing the coating layer from a convex portion of the metal base.
【請求項2】前記金属基体の凸部に被着させる被覆層が
無機材より成っていることを特徴とする特許請求の範囲
第1項記載の半導体素子収納用パッケージの製造方法。
2. The method according to claim 1, wherein the coating layer applied to the projections of the metal base is made of an inorganic material.
JP63068885A 1988-03-22 1988-03-22 Manufacturing method of semiconductor device storage package Expired - Fee Related JP2604621B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63068885A JP2604621B2 (en) 1988-03-22 1988-03-22 Manufacturing method of semiconductor device storage package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63068885A JP2604621B2 (en) 1988-03-22 1988-03-22 Manufacturing method of semiconductor device storage package

Publications (2)

Publication Number Publication Date
JPH01239959A JPH01239959A (en) 1989-09-25
JP2604621B2 true JP2604621B2 (en) 1997-04-30

Family

ID=13386554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63068885A Expired - Fee Related JP2604621B2 (en) 1988-03-22 1988-03-22 Manufacturing method of semiconductor device storage package

Country Status (1)

Country Link
JP (1) JP2604621B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2904141B2 (en) * 1996-08-20 1999-06-14 日本電気株式会社 Semiconductor device

Also Published As

Publication number Publication date
JPH01239959A (en) 1989-09-25

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