JP2570765Y2 - Package for storing semiconductor elements - Google Patents

Package for storing semiconductor elements

Info

Publication number
JP2570765Y2
JP2570765Y2 JP1991066661U JP6666191U JP2570765Y2 JP 2570765 Y2 JP2570765 Y2 JP 2570765Y2 JP 1991066661 U JP1991066661 U JP 1991066661U JP 6666191 U JP6666191 U JP 6666191U JP 2570765 Y2 JP2570765 Y2 JP 2570765Y2
Authority
JP
Japan
Prior art keywords
semiconductor element
metal plate
metal
metal base
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1991066661U
Other languages
Japanese (ja)
Other versions
JPH0520336U (en
Inventor
右文 出田
博司 土岐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP1991066661U priority Critical patent/JP2570765Y2/en
Publication of JPH0520336U publication Critical patent/JPH0520336U/en
Application granted granted Critical
Publication of JP2570765Y2 publication Critical patent/JP2570765Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Description

【考案の詳細な説明】[Detailed description of the invention]

【0001】[0001]

【産業上の利用分野】本考案は半導体素子、特に半導体
素子集積回路素子を収容するための半導体素子収納用パ
ッケージの改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a package for accommodating a semiconductor device, in particular, a semiconductor device for accommodating a semiconductor device integrated circuit device.

【0002】[0002]

【従来の技術】近年、情報処理装置の高性能化に伴いそ
れを構成する半導体素子も高密度化、高集積化が急激に
進んでいる。そのため半導体素子は作動時に発生する単
位面積、単位体積あたりの発熱量が増大し、半導体素子
を正常、且つ安定に作動させるためにはその熱をいかに
効率的に除去するかが課題となっている。
2. Description of the Related Art In recent years, as the performance of an information processing apparatus has become higher, the density and the degree of integration of semiconductor elements constituting the information processing apparatus have been rapidly increasing. Therefore, the amount of heat generated per unit area and unit volume generated during operation of the semiconductor element increases, and how to efficiently remove the heat has been an issue in order to operate the semiconductor element normally and stably. .

【0003】従来、半導体素子の発生する熱の除去方法
としては一般に上面中央部に半導体素子が載置固定され
る載置部を有する銅−タングステン合金から成る金属基
体上に、前記載置部を囲繞するようにしてアルミナセラ
ミックスから成る絶縁枠体を銀ロウ等のロウ材を介し取
着された構造の半導体素子収納用パッケージを準備し、
金属基体の半導体素子載置部に半導体素子を金属板を介
して載置固定し半導体素子から発生される熱を金属基体
に吸収させるととも該吸収した熱を大気中に放出するこ
とによって行われている。
Conventionally, as a method of removing heat generated by a semiconductor element, the above-described mounting part is generally formed on a metal base made of a copper-tungsten alloy having a mounting part on which the semiconductor element is mounted and fixed at the center of the upper surface. Prepare a semiconductor element storage package having a structure in which an insulating frame made of alumina ceramics is attached via a brazing material such as silver brazing so as to surround it.
The method is performed by mounting and fixing a semiconductor element on a semiconductor element mounting portion of a metal base via a metal plate, absorbing heat generated from the semiconductor element to the metal base, and releasing the absorbed heat to the atmosphere. ing.

【0004】尚、前記絶縁枠体には金属配線層が埋設さ
れており、該金属配線層を介して内部に収容する半導体
素子の各電極を外部の電気回路に電気的に接続し得るよ
うになっている。
A metal wiring layer is embedded in the insulating frame so that each electrode of a semiconductor element housed therein can be electrically connected to an external electric circuit via the metal wiring layer. Has become.

【0005】また金属基体の半導体素子載置部と半導体
素子との間に介在される金属板は金属基体と半導体素子
の熱膨張係数の差によって生じる熱応力を緩和する作用
を為し、該金属板は打ち抜き加工により形成されるとと
もに打ち抜き加工の際に形成されるバリ面が半導体素子
側となるように配置されている。
The metal plate interposed between the semiconductor element mounting portion of the metal base and the semiconductor element acts to relieve thermal stress caused by the difference in thermal expansion coefficient between the metal base and the semiconductor element. The plate is formed by punching and is arranged such that a burr surface formed at the time of punching is on the semiconductor element side.

【0006】更に前記金属板はその外表面にニッケルメ
ッキ、金メッキが施してあり、ニッケルメッキ膜、金メ
ッキ膜を被着させることよって金属板と半導体素子とが
容易、且つ強固に接合し得るようになっている。
[0006] Further, the metal plate is plated with nickel or gold on its outer surface so that the metal plate and the semiconductor element can be easily and firmly joined to each other by applying a nickel plating film or a gold plating film. Has become.

【0007】[0007]

【考案が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージにおいては、金属板を
打ち抜き加工により形成する際、外周部に屈曲したバリ
が形成され、これが金属板の外表面にニッケルメッキ、
金メッキを施す際、メッキ液の残留を許容してしまう。
そのためこの屈曲したバリを有する面側に半導体素子を
接合すると、半導体素子を接合する際の熱が金属板に印
加された際、屈曲したバリに残留するメッキ液が気化膨
張し、ニッケルメッキ膜、金メッキ膜を金属板より剥離
させて半導体素子と金属板との接合強度を大幅に低下さ
せてしまうという欠点を有していた。
However, in the conventional package for accommodating a semiconductor element, when a metal plate is formed by punching, a bent burr is formed on an outer peripheral portion, and this burr is formed on the outer surface of the metal plate by nickel. plating,
When gold plating is performed, a residual plating solution is allowed.
Therefore, when the semiconductor element is bonded to the surface having the bent burrs, when heat at the time of bonding the semiconductor elements is applied to the metal plate, a plating solution remaining on the bent burrs vaporizes and expands, and a nickel plating film, There is a drawback that the gold plating film is peeled off from the metal plate and the bonding strength between the semiconductor element and the metal plate is greatly reduced.

【0008】[0008]

【課題を解決するための手段】本考案は半導体素子が金
属板を介して載置固定される載置部を有する金属基体
に、前記載置部を囲繞するようにして絶縁枠体を取着し
て成る半導体素子収納用パッケージにおいて、前記金属
基体に半導体素子を載置固定する金属板は、打ち抜き加
工により形成されるバリ面が前記金属基体側となるよう
に配置されていることを特徴とするものである。
According to the present invention, an insulating frame is attached to a metal base having a mounting portion on which a semiconductor element is mounted and fixed via a metal plate so as to surround the mounting portion. In the semiconductor device housing package, the metal plate for mounting and fixing the semiconductor element on the metal base is arranged so that a burr surface formed by punching is on the metal base side. Is what you do.

【0009】[0009]

【実施例】次に本考案を添付図面に基づき詳細に説明す
る。図1 は本考案にかかる半導体素子収納用パッケージ
の一実施例を示す断面図であり、1 は金属基体、2 は金
属板、3 は絶縁枠体である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing one embodiment of a package for housing a semiconductor device according to the present invention, wherein 1 is a metal base, 2 is a metal plate, and 3 is an insulating frame.

【0010】前記金属基体1 はその上面中央部に半導体
素子が載置される凸状の載置部1aが設けてあり、該凸状
載置部1a上には半導体素子4 が金属板2 を間に挟んで載
置固定される。
The metal substrate 1 is provided with a convex mounting portion 1a on which a semiconductor element is mounted at the center of the upper surface thereof. On the convex mounting portion 1a, a semiconductor element 4 is provided with a metal plate 2 on which a semiconductor plate is mounted. It is placed and fixed with sandwiched between.

【0011】前記金属基体1 は半導体素子4 が発する熱
を吸収するとともに該吸収した熱を大気中に放出する作
用を為し、後述する絶縁枠体3 との間に大きな熱応力が
発生しないよう熱膨張係数が絶縁枠体3 と近似し、且つ
良熱伝導性である材料、例えば銅−タングステン合金
(Cu-W合金) により形成されている。
The metal base 1 functions to absorb the heat generated by the semiconductor element 4 and release the absorbed heat to the atmosphere, so that a large thermal stress is not generated between the metal base 1 and the insulating frame 3 described later. It is formed of a material having a thermal expansion coefficient close to that of the insulating frame 3 and having good thermal conductivity, for example, a copper-tungsten alloy (Cu-W alloy).

【0012】尚、前記銅−タングステン合金より成る金
属基体1 は、例えばタングステンの粉末( 約10μm)を10
00Kg/cm 2 の圧力で加圧成形するとともにこれを還元雰
囲気中、約2300℃の温度で焼成して多孔質のタングステ
ン焼結体を得、次に1100℃の温度で加熱溶融させた銅を
前記タングステン焼結体の多孔部分に毛管現象を利用し
含浸させることによって形成される。
The metal substrate 1 made of the copper-tungsten alloy is made of, for example, tungsten powder (about 10 μm).
This is pressed at a pressure of 00 kg / cm 2 and fired at a temperature of about 2300 ° C. in a reducing atmosphere to obtain a porous tungsten sintered body. It is formed by impregnating the porous portion of the tungsten sintered body using a capillary phenomenon.

【0013】また前記金属基体1 はその上面外周端に金
属基体1 の上面に設けた凸状の載置部1aを囲繞するよう
にして絶縁枠体3 が取着されており、金属基体1 と絶縁
枠体3 とで半導体素子4 を収容するための空所が形成さ
れる。
An insulating frame 3 is attached to the metal base 1 so as to surround a convex mounting portion 1a provided on the upper surface of the metal base 1 at the outer peripheral end of the upper surface. A space for accommodating the semiconductor element 4 is formed with the insulating frame 3.

【0014】前記絶縁枠体3 はアルミナセラミックス等
の電気絶縁材料から成り、例えばアルミナセラミックス
の粉末に適当な有機溶剤、溶媒を添加混合して泥漿状と
なすとともにこれをドクターブレード法を採用すること
によってグリーンシート( セラミック生シート) を形成
し、しかる後、前記グリーンシートに適当な打ち抜き加
工を施すとともに複数枚積層し、高温で焼成することに
よって製作される。
The insulating frame 3 is made of an electrical insulating material such as alumina ceramics. For example, a suitable organic solvent and a solvent are added to and mixed with alumina ceramic powder to form a slurry, and this is formed by a doctor blade method. To form a green sheet (ceramic green sheet). Thereafter, the green sheet is subjected to an appropriate punching process, and a plurality of the green sheets are laminated and fired at a high temperature.

【0015】前記絶縁枠体3 はその下面にタングステ
ン、モリブデン等の高融点金属粉末から成るメタライズ
金属層5 が被着されており、該メタライズ金属層5 と金
属基体1 とを銀ロウ等のロウ材6 を介しロウ付けするこ
とによって金属基体1 上に取着される。
The insulating frame 3 has a metallized metal layer 5 made of a refractory metal powder such as tungsten or molybdenum adhered on the lower surface thereof. It is mounted on the metal substrate 1 by brazing through the material 6.

【0016】また前記絶縁枠体3 の内部にはモリブデ
ン、タングステン等の高融点金属粉末から成る導電層7
が設けてあり、該導電層7 は半導体素子4 の電極を外部
リードピン8 に接続する作用を為し、その一端に外部リ
ードピン8 が、また他端に半導体素子4 の電極に接続さ
れたボンディングワイヤ9 が取着される。
A conductive layer 7 made of a high melting point metal powder such as molybdenum or tungsten is provided inside the insulating frame 3.
The conductive layer 7 serves to connect the electrode of the semiconductor element 4 to the external lead pin 8, and the external lead pin 8 is connected to one end of the conductive layer 7, and the bonding wire is connected to the electrode of the semiconductor element 4 at the other end. 9 is attached.

【0017】前記絶縁枠体3 に設けた導電層7 に取着さ
れる外部リードピン8 は内部に収容する半導体素子4 の
各電極を外部電気回路に接続する作用を為し、コバール
金属Fe-Ni-Co合金) や42アロイ(Fe-Ni合金) 等の金属を
棒状に加工したものが使用される。
The external lead pins 8 attached to the conductive layer 7 provided on the insulating frame 3 serve to connect each electrode of the semiconductor element 4 housed therein to an external electric circuit, so that the Kovar metal Fe-Ni A rod-shaped metal such as -Co alloy) or 42 alloy (Fe-Ni alloy) is used.

【0018】尚、前記外部リードピン8 の外表面にニッ
ケル(Ni)、金(Au)から成る良導電性で、且つ耐蝕性に優
れた金属をメッキ法により2 乃至20μm の厚みに層着さ
せておくと外部リードピン8 と外部電気回路との電気的
接続が良好となり、また外部リードピン8 の酸化腐食が
有効に防止される。従って、外部リードピン8 の酸化腐
食を防止し、且つ外部電気回路との電気的接続を良好と
するには外部リードピン8 の外表面にニッケル(Ni)、金
(Au)から成る良導電性で、且つ耐蝕性に優れた金属を2
乃至20μm の厚みに層着しておくことが好ましい。
A good conductive and corrosion-resistant metal made of nickel (Ni) or gold (Au) is applied on the outer surface of the external lead pin 8 by plating to a thickness of 2 to 20 μm. By doing so, the electrical connection between the external lead pins 8 and the external electric circuit is improved, and oxidation corrosion of the external lead pins 8 is effectively prevented. Therefore, in order to prevent the external lead pins 8 from being oxidized and corroded and to improve the electrical connection with an external electric circuit, nickel (Ni) or gold
(Au) made of highly conductive and corrosion resistant metal
It is preferable to coat the layer to a thickness of from 20 to 20 μm.

【0019】また前記上面に絶縁枠体3 が取着された金
属基体1 は図2 に示すように、その半導体素子載置部1a
に金属板2 を間に挟んで半導体素子4 が載置固定され
る。
Further, as shown in FIG. 2, the metal substrate 1 having the insulating frame 3 attached to the upper surface thereof has a semiconductor element mounting portion 1a.
The semiconductor element 4 is mounted and fixed with the metal plate 2 interposed therebetween.

【0020】前記金属基体1 の半導体素子載置部1aと半
導体素子4 との間に挟まれる金属板2 は金属基体1 と半
導体素子4 との熱膨張係数の差によって生じる熱応力を
緩和する作用を為し、金属基体1 と半導体素子4 との間
の熱膨張係数を有する金属材料、具体的にはモリブデン
が好適に使用される。
A metal plate 2 sandwiched between the semiconductor element mounting portion 1a of the metal base 1 and the semiconductor element 4 acts to relieve thermal stress caused by a difference in thermal expansion coefficient between the metal base 1 and the semiconductor element 4. Therefore, a metal material having a coefficient of thermal expansion between the metal substrate 1 and the semiconductor element 4, specifically, molybdenum is preferably used.

【0021】前記金属板2 はモリブデンの薄板を打ち抜
き加工法により所定形状に打ち抜くことによって形成さ
れ、該金属板2 は打ち抜き時に形成されるバリ2aが金属
基体1 の半導体素子載置部1a側となるようにして銀ロウ
等のロウ材10を介し金属基体1 の半導体素子載置部1a上
面に取着される。この場合、屈曲したバリ2a内にはロウ
材10が入り込むため金属板2 と金属基体1 とのロウ付け
強度が大幅に向上するとともに金属板2 の外表面に後述
するニッケルメッキ膜、金メッキ膜を層着させる際、メ
ッキ液が屈曲したバリ2a内に入り込んで残留するのが有
効に防止され、金属板2 と半導体素子4 との接合強度を
極めて高いものとなすこともできる。
The metal plate 2 is formed by punching a thin plate of molybdenum into a predetermined shape by a punching method. The metal plate 2 has a burr 2a formed at the time of punching and a metal substrate 1 on the semiconductor element mounting portion 1a side of the metal base 1. In this way, it is attached to the upper surface of the semiconductor element mounting portion 1a of the metal base 1 via a brazing material 10 such as silver brazing. In this case, since the brazing material 10 enters the bent burr 2a, the brazing strength between the metal plate 2 and the metal base 1 is greatly improved, and a nickel plating film or a gold plating film described later is formed on the outer surface of the metal plate 2. At the time of layering, the plating solution is effectively prevented from entering and remaining in the bent burr 2a, and the bonding strength between the metal plate 2 and the semiconductor element 4 can be made extremely high.

【0022】また前記金属板2 はその外表面にニッケル
膜と金膜とから成る2 層構造のメッキ膜10が層着されて
おり、該メッキ膜10のニッケル膜は金属板2 表面に金膜
を強固に被着させる作用を為し、また金膜は半導体素子
4 を構成するシリコンと共晶合金を作り、半導体素子4
を金属板2 上に強固に接合させる作用を為す。
On the outer surface of the metal plate 2, a plating film 10 having a two-layer structure composed of a nickel film and a gold film is layered, and the nickel film of the plating film 10 is a gold film on the surface of the metal plate 2. Acts firmly, and the gold film is
4 Make a eutectic alloy with silicon that constitutes
Is firmly bonded on the metal plate 2.

【0023】尚、前記ニッケル膜と金膜とから成る2 層
構造のメッキ膜10は従来周知の電解メッキ法、或いは無
電解メッキ法を採用することによって金属板2 の外表面
に層着される。この場合、金属板2 の屈曲したバリ2a内
にはロウ材10が充填されているためメッキ液がバリ2a内
に入り込んで残留することはほとんどなく、その結果、
半導体素子4 を金属板2 上に接合する際、金属板2 に熱
が印加されたとしてもメッキ膜10はバリ2a内に残留する
メッキ液の気化膨張によって剥離することは皆無であ
り、半導体素子4 を金属板2 に強固に接合させることが
可能となる。
The plating film 10 having a two-layer structure composed of the nickel film and the gold film is formed on the outer surface of the metal plate 2 by employing a conventionally known electrolytic plating method or electroless plating method. . In this case, since the brazing material 10 is filled in the bent burr 2a of the metal plate 2, the plating solution hardly enters the burr 2a and remains, and as a result,
When the semiconductor element 4 is bonded onto the metal plate 2, even if heat is applied to the metal plate 2, the plating film 10 does not peel off due to the vaporization and expansion of the plating solution remaining in the burr 2 a. 4 can be firmly joined to the metal plate 2.

【0024】かくして本考案の半導体素子収納用パッケ
ージによれば、金属基体1 の半導体素子載置部1a上に取
着された金属板2 に半導体素子4 を接合固定し、半導体
素子4 の各電極をボンディングワイヤ9 を介して導電層
7 に接続するとともに蓋体11を絶縁枠体3 の上面に
封止材を介し取着することによって最終製品としての半
導体装置となる。
Thus, according to the package for housing a semiconductor element of the present invention, the semiconductor element 4 is bonded and fixed to the metal plate 2 attached on the semiconductor element mounting portion 1a of the metal base 1, and each electrode of the semiconductor element 4 is fixed. The bonding layer 9 through the conductive layer
7 and the lid 11 is attached to the upper surface of the insulating frame 3 via a sealing material, whereby a semiconductor device as a final product is obtained.

【0025】尚、本考案は上述した実施例に限定される
ものではなく、本考案の要旨を逸脱しない範囲であれば
種々の変更は可能である。
The present invention is not limited to the embodiment described above, and various modifications can be made without departing from the scope of the present invention.

【0026】[0026]

【考案の効果】本考案の半導体素子収納用パッケージに
よれば半導体素子が直接接合される金属板を、該金属板
に形成されたバリが金属基体側となるようにして金属基
体の半導体素子載置部に配したことから金属板を金属基
体の半導体素子載置部にロウ付けする際、ロウ材の一部
が金属板のバリ内に入り込んで金属板と金属基体の半導
体素子載置部とのロウ付け強度を大幅に向上させること
ができる。
According to the package for housing a semiconductor element of the present invention, a metal plate to which a semiconductor element is directly joined is mounted such that burrs formed on the metal plate face the metal substrate. When the metal plate is brazed to the semiconductor element mounting portion of the metal base because it is arranged in the mounting portion, a part of the brazing material enters into the burr of the metal plate and the metal plate and the semiconductor element mounting portion of the metal base are Can greatly improve the brazing strength.

【0027】また金属基体の半導体素子載置部に金属板
をロウ付けする際、ロウ材が金属板のバリ内に入り込む
ことから金属板の外表面ニッケルメッキ膜、金メッキ膜
を層着させる際、メッキ液がバリ内に入り込んで残留す
ることは殆どなく、その結果、半導体素子を金属板上に
接合させる際、金属板に熱が印加されたとしてもメッキ
膜はバリ内に残留するメッキ液の気化膨張によって剥離
することは皆無となり、半導体素子を金属板に強固に接
合させることも可能となる。
Further, when brazing a metal plate to a semiconductor element mounting portion of a metal substrate, since a brazing material enters into burrs of the metal plate, when a nickel plating film and a gold plating film are deposited on the outer surface of the metal plate, The plating solution hardly enters the burrs and remains. As a result, when the semiconductor element is bonded to the metal plate, even if heat is applied to the metal plate, the plating film is formed of the plating solution remaining in the burrs. There is no peeling due to vaporization and expansion, and the semiconductor element can be firmly joined to the metal plate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本考案の半導体素子収納用パッケージの一実施
例を示す断面図。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device storage package according to the present invention.

【図2】図1に示す半導体素子収納用パッケージの要部
拡大断面図である。
2 is an enlarged cross-sectional view of a main part of the package for housing a semiconductor element shown in FIG. 1;

【符号の説明】[Explanation of symbols]

1・・・金属基体 1a・・半導体素子載置部 2・・・金属板 2a・・バリ 3・・・絶縁枠体 DESCRIPTION OF SYMBOLS 1 ... Metal base 1a ... Semiconductor element mounting part 2 ... Metal plate 2a ... Burr 3 ... Insulating frame

Claims (1)

(57)【実用新案登録請求の範囲】(57) [Scope of request for utility model registration] 【請求項1】半導体素子が金属板を介して載置固定され
る載置部を有する金属基体に、前記載置部を囲繞するよ
うにして絶縁枠体を取着して成る半導体素子収納用パッ
ケージにおいて、前記金属基体に半導体素子を載置固定
する金属板は、打ち抜き加工により形成されるバリ面が
前記金属基体側となるように配置されていることを特徴
とする半導体素子収納用パッケージ。
1. A semiconductor element storage device comprising: a metal base having a mounting portion on which a semiconductor element is mounted and fixed via a metal plate; and an insulating frame body attached to the metal base so as to surround the mounting portion. In the package, the metal plate for mounting and fixing the semiconductor element on the metal base is arranged such that a burr surface formed by punching is on the metal base side.
JP1991066661U 1991-08-22 1991-08-22 Package for storing semiconductor elements Expired - Lifetime JP2570765Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1991066661U JP2570765Y2 (en) 1991-08-22 1991-08-22 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1991066661U JP2570765Y2 (en) 1991-08-22 1991-08-22 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH0520336U JPH0520336U (en) 1993-03-12
JP2570765Y2 true JP2570765Y2 (en) 1998-05-13

Family

ID=13322311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1991066661U Expired - Lifetime JP2570765Y2 (en) 1991-08-22 1991-08-22 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP2570765Y2 (en)

Also Published As

Publication number Publication date
JPH0520336U (en) 1993-03-12

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