JP2510585Y2 - Package for storing semiconductor devices - Google Patents

Package for storing semiconductor devices

Info

Publication number
JP2510585Y2
JP2510585Y2 JP5423090U JP5423090U JP2510585Y2 JP 2510585 Y2 JP2510585 Y2 JP 2510585Y2 JP 5423090 U JP5423090 U JP 5423090U JP 5423090 U JP5423090 U JP 5423090U JP 2510585 Y2 JP2510585 Y2 JP 2510585Y2
Authority
JP
Japan
Prior art keywords
semiconductor element
coating layer
metal base
insulating coating
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5423090U
Other languages
Japanese (ja)
Other versions
JPH0412637U (en
Inventor
博司 土岐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP5423090U priority Critical patent/JP2510585Y2/en
Publication of JPH0412637U publication Critical patent/JPH0412637U/ja
Application granted granted Critical
Publication of JP2510585Y2 publication Critical patent/JP2510585Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Description

【考案の詳細な説明】 (産業上の利用分野) 本考案は半導体素子、特に半導体集積回路素子を収容
するための半導体素子収納用パッケージの改良に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an improvement in a semiconductor device housing package for housing a semiconductor device, particularly a semiconductor integrated circuit device.

(従来技術及びその課題) 近時、情報処理装置の高性能化、高速度化に伴い、そ
れを構成する半導体素子も高密度、高集積化が急激に進
んでいる。そのため半導体素子の単位面積、単位体積あ
たりの発熱量が増大し、半導体素子を正常、且つ安定に
作動させるためにはその熱をいかに効率的に除去するか
が課題となっている。
(Prior Art and Problems Thereof) In recent years, as the performance and speed of information processing apparatuses have increased, the density and integration of semiconductor elements constituting the information processing apparatuses have rapidly increased. Therefore, the amount of heat generated per unit area and unit volume of the semiconductor element increases, and a problem is how to efficiently remove the heat in order to operate the semiconductor element normally and stably.

従来、半導体素子の発生する熱の除去方法としては第
2図に示すように上面中央部に半導体素子13が載置され
る載置部11aを有した金属基体11上に、前記載置部11aを
囲繞するようにして絶縁枠体12をロウ付け取着した構造
の半導体素子収納用パッケージを準備し、金属基体11の
半導体素子載置部11aに半導体素子13を載置して半導体
素子13が発生する熱を金属基体11に吸収させるとともに
該吸収した熱を大気中に放出することによって行われて
いる。
Conventionally, as a method for removing heat generated by a semiconductor element, as shown in FIG. 2, a mounting portion 11a is placed on a metal base 11 having a mounting portion 11a on which a semiconductor element 13 is mounted in a central portion of an upper surface. A semiconductor element housing package having a structure in which the insulating frame 12 is brazed and attached so as to surround the semiconductor element 13 is mounted on the semiconductor element mounting portion 11a of the metal base 11 and the semiconductor element 13 is The heat generated is absorbed by the metal substrate 11 and the absorbed heat is released to the atmosphere.

尚、前記半導体素子収納用パッケージにおいて、金属
基体11は上面にロウ付け取着される絶縁枠体12との間に
大きな熱応力が発生しないよう熱膨張係数が絶縁枠体12
と近似する金属、例えば銅−タングステン合金(Cu-W合
金)により形成されており、また前記絶縁枠体12はその
下面にモリブデン(Mo)、タングステン(W)、マンガ
ン(Mn)等の高融点金属から成るメタライズ金属層14が
被着形成されており、該メタライズ金属層14を金属基体
11に銀ロウ(Ag-Cu合金)等のロウ材15を介しロウ付け
することによって金属基体11上に絶縁枠体12をロウ付け
取着させている。
In the package for housing the semiconductor element, the metal base body 11 has a thermal expansion coefficient of the insulating frame body 12 so that a large thermal stress is not generated between the metal base body 11 and the insulating frame body 12 which is brazed and attached to the upper surface.
Is formed of a metal similar to that of, for example, a copper-tungsten alloy (Cu-W alloy), and the insulating frame 12 has a high melting point of molybdenum (Mo), tungsten (W), manganese (Mn), etc. on its lower surface. A metallized metal layer 14 made of a metal is deposited and formed, and the metallized metal layer 14 is formed on a metal substrate.
The insulating frame body 12 is brazed and attached to the metal base 11 by brazing to the metal base 11 via a brazing material 15 such as silver braze (Ag—Cu alloy).

しかし乍ら、この従来の半導体素子収納用パッケージ
は半導体素子13が金属基体11に直接取着されていること
及び金属基体11の下面が大きく露出していること等から
該半導体素子収納用パッケージを外部の回路基板上に実
装させた場合、金属基体11に回路基板上の他の電子部品
や配線導体が接触すると金属基体11を介して内部に収容
する半導体素子13に不要な電気が流れてしまい、その結
果、半導体素子13に誤動作を起こさせたり、特性に劣化
を生じさせたりするという欠点を有していた。
However, in this conventional semiconductor element storage package, since the semiconductor element 13 is directly attached to the metal base 11 and the lower surface of the metal base 11 is largely exposed, the semiconductor element storage package is When mounted on an external circuit board, if other electronic components or wiring conductors on the circuit board come into contact with the metal base 11, unnecessary electricity will flow to the semiconductor element 13 housed inside via the metal base 11. As a result, there is a defect that the semiconductor element 13 may malfunction or its characteristics may deteriorate.

そこで上記欠点を解消するために本出願人は先に金属
基体の外表面に酸化アルミニウム(アルミナ:Al2O3
から成る絶縁被覆層をスパッタリング等で被着させた半
導体素子収納用パッケージを提案した(実開昭64-50438
号公報参照)。
Therefore, in order to solve the above-mentioned drawbacks, the present applicant first applied aluminum oxide (alumina: Al 2 O 3 ) to the outer surface of the metal substrate.
We proposed a package for accommodating semiconductor devices in which an insulating coating layer consisting of is deposited by sputtering etc.
(See the official gazette).

しかし乍ら、この半導体素子収納用パッケージは絶縁
被覆層を構成する酸化アルミニウムの熱膨張係数が約7.
0×10-6/℃であり、金属基体を構成する銅−タングス
テンの熱膨張係数(6.0×10-6/℃)と差異を有してい
ること及び従来の半導体素子が発する熱は3W程度であっ
たものが近時は10W程度となり、発熱量が3倍以上の大
きなものとなってきていること等から以下に述べるよう
な欠点を誘発する。
However, in this semiconductor device housing package, the thermal expansion coefficient of aluminum oxide that constitutes the insulating coating layer is about 7.
0 × 10 -6 / ° C, which is different from the thermal expansion coefficient (6.0 × 10 -6 / ° C) of copper-tungsten that composes the metal substrate, and the heat generated by conventional semiconductor devices is about 3 W However, the current value is about 10 W, and the calorific value is more than three times as large, which causes the following defects.

即ち、 絶縁被覆層と金属基体との間に熱膨張係数の相違があ
ることから両者に半導体素子の発する熱が印加されると
両者間に熱応力が発生するとともに該熱応力によって絶
縁被覆層が金属基体より剥がれてしまい、その結果、金
属基体が露出し、金属基体に回路基板上の他の電子部品
や配線導体が接触すると該金属基体を介して内部に収容
する半導体素子に不要な電気が流れ、これによって半導
体素子に誤動作を起こさせたり、特性に劣化を生じさせ
たりしてしまう また絶縁被覆層が金属基体より剥がれると該絶縁被覆
層上に取着されている半導体素子も同時に金属基体より
剥がれてしまい、その結果、半導体素子の発する熱を金
属基体に良好に伝導吸収させることができなくなり、ま
た半導体素子の各電極を外部の回路基板に良好に電気的
接続することができなくなって半導体装置としての機能
を喪失してしまう 等の欠点を有していた。
That is, since there is a difference in thermal expansion coefficient between the insulating coating layer and the metal substrate, when heat generated by the semiconductor element is applied to both, a thermal stress is generated between the two and the insulating coating layer is formed by the thermal stress. When peeled off from the metal base, as a result of which the metal base is exposed and other electronic components or wiring conductors on the circuit board come into contact with the metal base, unnecessary electricity is generated in the semiconductor element housed inside through the metal base. Flow, which may cause the semiconductor element to malfunction or cause deterioration in characteristics. Further, when the insulating coating layer is peeled off from the metal substrate, the semiconductor element attached on the insulating coating layer is also simultaneously welded to the metal substrate. As a result, the heat generated by the semiconductor element cannot be satisfactorily conducted and absorbed by the metal substrate, and the electrodes of the semiconductor element can be satisfactorily electrically connected to the external circuit board. Had drawbacks such as resulting in loss of function as a semiconductor device can no longer be connected.

(考案の目的) 本考案は上記諸欠点に鑑み案出されたもので、その目
的は金属基体に絶縁被覆層を強固に被着させ、内部に収
容する半導体素子に不要な電気が流れるのを皆無として
半導体素子を長期間にわたり正常、且つ安定に作動させ
ることができる半導体素子収納用パッケージを提供する
ことにある。
(Object of the Invention) The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to firmly adhere an insulating coating layer to a metal substrate to prevent unnecessary electricity from flowing to a semiconductor element housed inside. It is an object of the present invention to provide a package for accommodating a semiconductor element, which can operate the semiconductor element normally and stably over a long period of time without any element.

(課題を解決するための手段) 本考案は銅−タングステン合金から成り、上面中央部
に半導体素子が載置される載置部を有する金属基体上
に、該載置部を囲繞するようにして絶縁枠体を取着して
成る半導体素子収納用パッケージにおいて、前記金属基
体の少なくとも半導体素子載置部表面に30.0乃至70.0重
量%の非晶質ガラスに30.0乃至70.0重量%の酸化アルミ
ニウム粉末、ステアタイト粉末、スピネル粉末の少なく
とも1種を含有させて成る絶縁被覆層を被着させたこと
を特徴とするものである。
(Means for Solving the Problems) The present invention is made of a copper-tungsten alloy, and surrounds the mounting portion on a metal substrate having a mounting portion on which a semiconductor element is mounted in the center of the upper surface. In a package for accommodating a semiconductor element formed by attaching an insulating frame, at least the surface of the semiconductor element mounting portion of the metal substrate is provided with 30.0 to 70.0% by weight of amorphous glass and 30.0 to 70.0% by weight of aluminum oxide powder, and It is characterized in that an insulating coating layer containing at least one of tight powder and spinel powder is applied.

(実施例) 次に本考案を添付図面に基づき詳細に説明する。(Example) Next, this invention is demonstrated in detail based on an accompanying drawing.

第1図は本考案の半導体素子収納用パッケージの一実
施例を示し、1は金属基体、2は絶縁枠体である。
FIG. 1 shows an embodiment of a package for housing a semiconductor device of the present invention, in which 1 is a metal base and 2 is an insulating frame.

前記金属基体1はその上面中央部に半導体素子3を載
置させための凸状の載置部1aが設けてあり、該載置部1a
上には半導体素子3が接着材を介し取着される。
The metal base 1 is provided with a convex mounting portion 1a for mounting the semiconductor element 3 on the center of the upper surface thereof.
The semiconductor element 3 is attached to the upper side with an adhesive.

前記金属基体1は半導体素子3が発する熱を直接伝導
吸収するとともに該吸収した熱を大気中に放出する作用
を為し、後述する絶縁枠体2との間に大きな熱応力が発
生しないよう熱膨張係数が絶縁枠体2と近似し、且つ良
熱伝導性である材料、具体的には銅−タングステン合金
(Cu-W合金)により形成されている。
The metal base 1 directly conducts and absorbs the heat generated by the semiconductor element 3 and releases the absorbed heat into the atmosphere, so that a large thermal stress is not generated between the metal base 1 and the insulating frame 2 described later. It is made of a material having a coefficient of expansion similar to that of the insulating frame 2 and good thermal conductivity, specifically, a copper-tungsten alloy (Cu-W alloy).

尚、前記銅−タングステン合金より成る金属基体1
は、例えばタングステンの粉末(約10μm)を1000Kg/c
m2の圧力で加圧成形するとともにこれを還元雰囲気中、
約2300℃の温度で焼成して多孔質のタングステン焼結体
を得、次に1100℃の温度で加熱溶融させた銅を前記タン
グステン焼結体の多孔部分に毛管現象を利用して含浸さ
せることによって形成される。
The metal base 1 made of the copper-tungsten alloy
Is, for example, tungsten powder (about 10 μm) 1000 Kg / c
Pressure molding with a pressure of m 2 and this in a reducing atmosphere,
To obtain a porous tungsten sintered body by firing at a temperature of about 2300 ° C., and then to impregnate the porous portion of the tungsten sintered body with a capillary phenomenon by using copper heated and melted at a temperature of 1100 ° C. Formed by.

また前記金属基体1は半導体素子載置部1a表面に絶縁
被覆層4が被着されている。
The metal base 1 has an insulating coating layer 4 deposited on the surface of the semiconductor element mounting portion 1a.

前記絶縁被覆層4は金属基体1と該金属基体1の半導
体素子載置部1aに載置される半導体素子3とを電気的に
絶縁分離する作用を為し、金属基体1に回路基板上の他
の電子部品や配線導体が接触し金属基体1を介して半導
体素子3に不要な電気が流れようとしてもその電気の流
れは前記絶縁被覆層4により完全に阻止され、半導体素
子3に不要な電気が流れることは一切ない。
The insulating coating layer 4 serves to electrically insulate and separate the metal base 1 from the semiconductor element 3 mounted on the semiconductor element mounting portion 1a of the metal base 1, and the metal base 1 is provided on the circuit board. Even if other electronic components or wiring conductors come into contact with each other and unnecessary electric power flows to the semiconductor element 3 through the metal substrate 1, the electric current flow is completely blocked by the insulating coating layer 4 and is unnecessary for the semiconductor element 3. No electricity flows.

また前記絶縁被覆層4は30.0乃至70.0重量%の非晶質
ガラスに30.0乃至70.0重量%の酸化アルミニウム粉末、
ステアタイト粉末、スピネル粉末の少なくとも1種を含
有させて成り、その熱膨張係数は5.7乃至6.5×10-6/℃
で、金属基体1を構成する銅−タングステンの熱膨張係
数と近似する。そのため絶縁被覆層4と金属基体1の両
者に半導体素子3の発する熱が印加されたとしても両者
は熱膨張係数が近似することから両者間に大きな熱応力
が発生することはなく、該熱応力によって絶縁被覆層4
が金属基体1より剥離することもない。
The insulating coating layer 4 comprises 30.0 to 70.0% by weight of amorphous glass and 30.0 to 70.0% by weight of aluminum oxide powder,
It is made by containing at least one of steatite powder and spinel powder, and its thermal expansion coefficient is 5.7 to 6.5 × 10 -6 / ° C.
Then, it is approximated to the thermal expansion coefficient of copper-tungsten forming the metal substrate 1. Therefore, even if the heat generated by the semiconductor element 3 is applied to both the insulating coating layer 4 and the metal substrate 1, the thermal expansion coefficients of the two are similar to each other, so that a large thermal stress does not occur between the two and the thermal stress is not generated. Insulation coating layer 4
Does not separate from the metal substrate 1.

前記絶縁被覆層4は非晶質ガラスとして酸化シリコン
(SiO2)64.0重量%、酸化ホウ素(B2O3)19.0重量%、
酸化アルミニウム(Al2O3)8.0重量%、酸化ナトリウ
ム、酸化カリウム(K2O)3.0重量%、(Na2O)2.0重量
%等から成るガラスが好適に使用され、該非晶質ガラス
粉末に酸化アルミニウム粉末、ステアタイト粉末、スピ
ネル粉末の少なくとも1種と適当な有機溶剤、溶媒を添
加混合して泥漿状となし、これを金属基体1の半導体素
子載置部1a上に印刷塗布するとともに約1000℃の温度で
焼き付けることによって金属基体1の半導体素子載置部
1a表面に被着される。
The insulating coating layer 4 is composed of amorphous glass as silicon oxide (SiO 2 ) 64.0% by weight, boron oxide (B 2 O 3 ) 19.0% by weight,
A glass comprising 8.0% by weight of aluminum oxide (Al 2 O 3 ), 3.0% by weight of sodium oxide, 3.0% by weight of potassium oxide (K 2 O), 2.0% by weight of (Na 2 O), etc. is preferably used, and the amorphous glass powder is At least one of aluminum oxide powder, steatite powder, and spinel powder, and an appropriate organic solvent and solvent are added and mixed to form a slurry, which is printed and applied on the semiconductor element mounting portion 1a of the metal substrate 1 and at the same time. The semiconductor element mounting portion of the metal substrate 1 is baked by baking at a temperature of 1000 ° C.
1a is applied to the surface.

尚、前記絶縁被覆層4は非晶質ガラスに含有させる酸
化アルミニウム粉末、ステアタイト粉末、スピネル粉末
の量が30.0重量%未満、或いは70.0重量%を越えると絶
縁被覆層4の熱膨張係数が絶縁被覆層4の熱膨張係数に
合わなくなって絶縁被覆層4を金属基体1に強固に被着
させることができなくなる。従って、非晶質ガラスに含
有される酸化アルミニウム粉末、ステアタイト粉末、ス
ピネル粉末の量は30.0乃至70.0重量%の範囲に限定され
る。
When the amount of aluminum oxide powder, steatite powder, and spinel powder contained in the amorphous glass is less than 30.0% by weight, or exceeds 70.0% by weight, the thermal expansion coefficient of the insulating coating layer 4 becomes insulating. Since the thermal expansion coefficient of the coating layer 4 is not satisfied, the insulating coating layer 4 cannot be firmly adhered to the metal substrate 1. Therefore, the amounts of aluminum oxide powder, steatite powder, and spinel powder contained in the amorphous glass are limited to the range of 30.0 to 70.0% by weight.

また前記絶縁被覆層4はその内部に酸化ニオブ、酸化
タンタルの少なくとも1種を1.0乃至10.0重量部添加し
ておくと絶縁被覆層4の金属基体1に対する濡れ性を大
きく改善し、絶縁被覆層4を金属基体1により強固に被
着させることができる。従って、絶縁被覆層4には酸化
ニオブ、酸化タンタルの少なくとも1種を1.0乃至10.0
重量部添加しておくことが望ましい。
If 1.0 to 10.0 parts by weight of at least one of niobium oxide and tantalum oxide is added to the inside of the insulating coating layer 4, the wettability of the insulating coating layer 4 with respect to the metal substrate 1 is greatly improved, and the insulating coating layer 4 Can be firmly adhered to the metal substrate 1. Therefore, the insulating coating layer 4 contains at least one of niobium oxide and tantalum oxide in the range of 1.0 to 10.0.
It is desirable to add parts by weight.

更に前記絶縁被覆層4はその厚みが5.0μm未満であ
ると金属基体1と半導体素子3との電気的な絶縁分離が
不十分となって半導体素子3に不要な電気が流れやすく
なり、また厚さが250.0μmを超えると半導体素子3の
発する熱が金属基体1に良好に伝導吸収されなくなる傾
向にあることから絶縁被覆層4の厚みは5.0乃至250.0μ
mの範囲としておくことが好ましい。
Further, if the thickness of the insulating coating layer 4 is less than 5.0 μm, the electrical insulation between the metal substrate 1 and the semiconductor element 3 is insufficient, and unnecessary electricity easily flows to the semiconductor element 3. When the thickness exceeds 250.0 μm, the heat generated by the semiconductor element 3 tends not to be well conducted and absorbed by the metal substrate 1, so that the thickness of the insulating coating layer 4 is 5.0 to 250.0 μm.
It is preferable to set it in the range of m.

前記金属基体1はまたその上面外周端に金属基体1の
上面に設けた凸状の載置部1aを囲繞するようにして絶縁
枠体2が取着されており、金属基体1と絶縁枠体2とで
半導体素子3を収容するための空所が形成される。
The metal base 1 has an insulating frame body 2 attached to the outer peripheral edge of the upper surface of the metal base body 1 so as to surround the convex mounting portion 1a provided on the upper surface of the metal base body 1. A space for accommodating the semiconductor element 3 is formed with 2.

前記絶縁枠体2はアルミナセラミックス等の電気絶縁
材料から成り、例えばアルミナセラミックスの粉末に適
当な有機溶剤、溶媒を添加混合して泥漿状となすととも
にこれをドクターブレード法を採用することによってグ
リーンシート(セラミック生シート)を形成し、しかる
後、グリーンシートに適当な打抜き加工を施すとともに
複数枚積層し、高温で焼成することによって製作され
る。
The insulating frame 2 is made of an electrically insulating material such as alumina ceramics. For example, a powder of alumina ceramics is mixed with an appropriate organic solvent or solvent to form a slurry, and the slurry is formed by a doctor blade method. (Ceramic green sheet) is formed, and thereafter, the green sheet is appropriately punched, and a plurality of sheets are laminated and fired at a high temperature.

前記絶縁枠体2はその下面にタングステン、モリブデ
ン等の高融点金属粉末から成るメタライズ金属層5が被
着されており、該メタライズ金属層5と金属基体1とを
銀ロウ等のロウ材6を介しロウ付けすることによって金
属基体1上に取着される。
On the lower surface of the insulating frame 2, a metallized metal layer 5 made of a high melting point metal powder such as tungsten or molybdenum is deposited. The metallized metal layer 5 and the metal base 1 are coated with a brazing material 6 such as silver solder. It is attached to the metal substrate 1 by brazing via.

また前記絶縁枠体2の内部にはモリブデン、タングス
テン等の高融点金属粉末から成る導電層7が設けてあ
り、該導電層7は半導体素子3の電極を外部リードピン
8に接続する作用を為し、その一端に外部リードピン8
が、また他端に半導体素子3の電極に接続されたボンデ
ィングワイヤ9が取着される。
A conductive layer 7 made of a high melting point metal powder such as molybdenum or tungsten is provided inside the insulating frame 2. The conductive layer 7 functions to connect the electrode of the semiconductor element 3 to the external lead pin 8. , An external lead pin 8 at one end
However, the bonding wire 9 connected to the electrode of the semiconductor element 3 is attached to the other end.

前記絶縁枠体2に設けた導電層7に取着される外部リ
ードピン8は内部に収容する半導体素子3の各電極を外
部回路に接続する作用を為し、コバール(Fe-Ni-Co合
金)や42Alloy(Fe-Ni合金)等の金属を棒状に加工した
ものが使用される。
The external lead pins 8 attached to the conductive layer 7 provided on the insulating frame 2 serve to connect the electrodes of the semiconductor element 3 housed inside to an external circuit, and are made of Kovar (Fe-Ni-Co alloy). A metal such as 42Alloy (Fe-Ni alloy) processed into a rod shape is used.

尚、前記外部リードピン8の外表面にニッケル(N
i)、金(Au)から成る良導電性で、且つ耐蝕性に優れ
た金属をメッキ法により層着させておくと外部リードピ
ン8と外部回路との電気的接続が良好となり、また外部
リードピン8の酸化腐食が有効に防止される。従って、
外部リードピン8の外表面にはニッケル(Ni)、金(A
u)から成る良導電性で、且つ耐蝕性に優れた金属を2
乃至10μmの厚みに層着しておくことが好ましい。
It should be noted that nickel (N
i), if a metal having good conductivity and excellent corrosion resistance made of gold (Au) is layered by a plating method, the electrical connection between the external lead pin 8 and the external circuit becomes good, and the external lead pin 8 The oxidative corrosion of is effectively prevented. Therefore,
On the outer surface of the external lead pin 8, nickel (Ni), gold (A
u), which is a metal with good conductivity and excellent corrosion resistance
It is preferable to layer them to a thickness of 10 to 10 μm.

また前記絶縁枠体2の上面には蓋体10がガラス、樹脂
等の封止材を介して取着され、これによって半導体素子
収納用パッケージの内部が完全に気密に封止される。
A lid 10 is attached to the upper surface of the insulating frame 2 via a sealing material such as glass or resin, whereby the inside of the semiconductor element housing package is completely hermetically sealed.

かくして絶縁枠体2が取着された金属基体1の凸状載
置部1a上に半導体素子3を取着し、半導体素子3の各電
極をボンディングワイヤ9を介して導電層7に接続する
とともに蓋体10を絶縁枠体2の上面に封止材を介し取着
することによって最終製品としての半導体装置となる。
Thus, the semiconductor element 3 is mounted on the convex mounting portion 1a of the metal substrate 1 to which the insulating frame 2 is mounted, and each electrode of the semiconductor element 3 is connected to the conductive layer 7 through the bonding wire 9. By attaching the lid body 10 to the upper surface of the insulating frame body 2 with a sealing material interposed therebetween, a semiconductor device as a final product is obtained.

尚、本考案は上述の実施例に限定されるものではなく
本考案の要旨を逸脱しない範囲であれば種々の変更は可
能であり、例えば絶縁被覆層4を金属基体1の半導体素
子載置部1a表面に限ることなく、金属基体1の外表面全
面に被着させておいてもよい。この場合、絶縁被覆層4
は半導体素子3への不要な電気の流れを阻止するととも
に金属基体1の酸化腐食をも有効に防止するため絶縁被
覆層4は金属基体1の外表面全面に被着させておくこと
が好ましい。
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, the insulating coating layer 4 may be used as the semiconductor element mounting portion of the metal substrate 1. Not limited to the surface 1a, it may be adhered to the entire outer surface of the metal substrate 1. In this case, the insulating coating layer 4
In order to prevent unnecessary flow of electricity to the semiconductor element 3 and effectively prevent oxidative corrosion of the metal substrate 1, it is preferable that the insulating coating layer 4 be deposited on the entire outer surface of the metal substrate 1.

(考案の効果) 本考案の半導体素子収納用パッケージによれば、前記
金属基体の少なくとも半導体素子載置部表面に30.0乃至
70.0重量%の非晶質ガラスに30.0乃至70.0重量%の酸化
アルミニウム粉末、ステアタイト粉末、スピネル粉末の
少なくとも1種を含有させて成る絶縁被覆層を被着させ
たことから半導体素子収納用パッケージを回路基板上に
実装させた際、回路基板上の他の電子部品や配線導体が
金属基体に接触したとしても金属基体と該金属基体上面
に載置される半導体素子とは前記絶縁被覆層によって電
気的に絶縁分離していることから半導体素子に不要な電
気が流れることは一切なく、内部に収容する半導体素子
を長期間にわたり正常、且つ安定に作動させることが可
能となる。
(Effect of the Invention) According to the package for accommodating a semiconductor element of the present invention, at least the surface of the semiconductor element mounting portion of the metal base having a thickness of 30.0 to 30.0.
Since a 70.0 wt% amorphous glass is coated with an insulating coating layer containing 30.0 to 70.0 wt% of at least one of aluminum oxide powder, steatite powder, and spinel powder, a package for housing a semiconductor device is obtained. When mounted on a circuit board, even if other electronic components or wiring conductors on the circuit board contact the metal base, the metal base and the semiconductor element mounted on the upper surface of the metal base are electrically connected by the insulating coating layer. Since they are electrically isolated from each other, no unnecessary electricity flows through the semiconductor element, and the semiconductor element accommodated inside can be normally and stably operated for a long period of time.

また本考案の絶縁被覆層はその熱膨張係数が金属基体
を構成する銅−タングステンと近似することから絶縁被
覆層と金属基体の両者に半導体素子が発する熱が印加さ
れたとしても両者間には熱応力が発生することは一切な
く、絶縁被覆層が金属基体より剥離することもない。従
って、これによっても内部に収容する半導体素子を長期
間にわたり正常、且つ安定に作動させることが可能とな
る。
Further, since the insulating coating layer of the present invention has a coefficient of thermal expansion similar to that of copper-tungsten which constitutes the metal substrate, even if heat generated by the semiconductor element is applied to both the insulating coating layer and the metal substrate, the heat is generated between the two layers. No thermal stress is generated, and the insulating coating layer does not peel off from the metal substrate. Therefore, also by this, the semiconductor element housed inside can be normally and stably operated for a long period of time.

【図面の簡単な説明】[Brief description of drawings]

第1図は本考案にかかる半導体素子収納用パッケージの
一実施例を示す断面図、第2図は従来の半導体素子収納
用パッケージの断面図である。 1……金属基体、1a……半導体素子載置部 2……絶縁枠体、4……絶縁被覆層
FIG. 1 is a sectional view showing an embodiment of a semiconductor device housing package according to the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device housing package. 1 ... Metal substrate, 1a ... Semiconductor element mounting portion 2 ... Insulating frame, 4 ... Insulating coating layer

Claims (1)

(57)【実用新案登録請求の範囲】(57) [Scope of utility model registration request] 【請求項1】銅−タングステン合金から成り、上面中央
部に半導体素子が載置される載置部を有する金属基体上
に、該載置部を囲繞するようにして絶縁枠体を取着して
成る半導体素子収納用パッケージにおいて、前記金属基
体の少なくとも半導体素子載置部表面に30.0乃至70.0重
量%の非晶質ガラスに30.0乃至70.0重量%の酸化アルミ
ニウム粉末、ステアタイト粉末、スピネル粉末の少なく
とも1種を含有させて成る絶縁被覆層を被着させたこと
を特徴とする半導体素子収納用パッケージ。
1. An insulating frame body is mounted on a metal base made of a copper-tungsten alloy and having a mounting portion on which a semiconductor element is mounted in the center of the upper surface so as to surround the mounting portion. In a package for storing a semiconductor element, which is composed of at least 30.0 to 70.0% by weight of amorphous glass on the surface of at least the semiconductor element mounting portion of the metal base, 30.0 to 70.0% by weight of aluminum oxide powder, steatite powder, and spinel powder. A package for accommodating a semiconductor element, characterized in that an insulating coating layer containing one kind is deposited.
JP5423090U 1990-05-24 1990-05-24 Package for storing semiconductor devices Expired - Lifetime JP2510585Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5423090U JP2510585Y2 (en) 1990-05-24 1990-05-24 Package for storing semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5423090U JP2510585Y2 (en) 1990-05-24 1990-05-24 Package for storing semiconductor devices

Publications (2)

Publication Number Publication Date
JPH0412637U JPH0412637U (en) 1992-01-31
JP2510585Y2 true JP2510585Y2 (en) 1996-09-11

Family

ID=31576111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5423090U Expired - Lifetime JP2510585Y2 (en) 1990-05-24 1990-05-24 Package for storing semiconductor devices

Country Status (1)

Country Link
JP (1) JP2510585Y2 (en)

Also Published As

Publication number Publication date
JPH0412637U (en) 1992-01-31

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