JPH07169916A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to select arbitrarily any bit from a plurality of bits owned by a data signal lines in a connection point between an input/ output port specified with one address and a data signal line connected to the input/output port. CONSTITUTION:There is installed an input/output means 2 which inputs and outputs outside data and provides an input/output port having a plurality of bits selected with one of address signal combinations. The combinations of data signal lines 4a and 4b are connected to each bit of the input/output port 2 on a one-to-one basis. The combination of the bits can be changed over with a change-over switch 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having an input / output circuit for inputting, outputting or inputting / outputting signals in a single chip microcomputer.

[0002]

2. Description of the Related Art For example, for a semiconductor integrated circuit product having a specification with an 80-pin input / output terminal in order to be housed in an 80-pin package, some functions and terminals of the specification are omitted. There are times when you want to develop a product that achieves a low price by using a pin package.

In such a case, if a new dedicated chip for a 64-pin package is developed, the development cost and the burden on the period increase, so that most of the chips are used for 80-pin products. Use the same chip as the one, 8
By selecting only the required 64 chips from the 0-pin chip, the product with 64-pin specifications has been realized.

Therefore, in a product with a package of 64 pins, it is necessary to reduce 16 pins with respect to a product with a package of 80 pins.

The chip developed for 80 pins is
Generally, all 80 pins are used to input / output power, input / output ports, control signals, etc., so the input / output pins such as timer and serial input / output part which are the peripheral functions built into the chip can be used. The products commonly used as general-purpose input / output pins have been realized as 64-pin package products by selecting only the input / output pins that are particularly required.

FIG. 7 is a block diagram showing a conventional semiconductor integrated circuit. In FIG. 7, 2 is a latch / direction register as a port output latch / input / output direction register, 3 is a pad, 4a is a data output line, and 6a is a line. A decode signal line for outputting a signal (hereinafter referred to as a decode signal) as an address signal input to the latch / direction register 2 for selecting an input / output port.

Next, the operation will be described. Input / output of data is performed between the data output line 4a and the pad 3 via the latch / direction register 2. At this time, the input / output is controlled by the decode signal obtained from the address signal.

FIG. 8 is a block diagram showing an input / output circuit of a semiconductor integrated circuit having a plurality of the above latch / direction registers. Reference numerals 2a to 2h are latch / direction registers and 3a to.
3h is a pad, 4 is a data signal line, 6 is a signal line for outputting a decode signal for selecting one of a plurality of input / output ports, 15 is a dedicated input / output signal line for peripheral functions, and 26 is an address for the decode signal. Address decode circuits created from signals, 27 are address signal lines, and 28a to 28c are peripheral function circuits such as timers and serial input / output units.

As shown in FIG. 8, the latch / direction register 2a
.About.2h, pads 3a to 3h, and data signal line 4 are fixed by hardware and cannot be changed after being commercialized. In addition, the peripheral function circuits 28a to 28
The same applies to each dedicated input / output signal line 15 from c.

[0010]

Since the conventional semiconductor integrated circuit is constructed as described above, it is necessary to select the required 64 pins from the 80 pin terminals, for example. In order to prioritize the peripheral functions to be selected and to select the pins, as shown in FIG. 9, 8 bits can be continuously used from port P70 to port P77 in the 80-pin package, but from port P70 to port P72 in the 64-pin package. And the port P77, the bit of the usable input / output port jumps.

Therefore, when it is used as an input / output port, it is impossible to successively handle a plurality of bits of the input / output port, and there is a problem that a program becomes complicated in data processing. It was

Further, since the unnecessary terminal is not connected to the outside as shown in FIG. 10, it is necessary to process the bit of the input / output port which is not connected to the outside. This is because if the input / output port is left in the input mode in a floating state, a through current will flow through the P-channel transistor and the N-channel transistor of the input / output buffer configured by the C-MOS circuit.

To prevent this, the output mode is set, and the state of the input / output pad is set to the power supply voltage (Vcc) level (hereinafter referred to as "H '") or the ground (GND) level (hereinafter referred to as "L'"). Therefore, there is a problem in that the program processing in software becomes complicated and the processing speed is reduced.

Further, as shown in FIG. 10, when connecting terminals (hereinafter, referred to as pads) 20 for connecting to the outside of the chip 19 and the frame 22 with a bonding wire 21,
The distance between the pads 20 that connect the bonding wires 21 is such that the pads 20 that connect with the bonding wires 21
The presence of the unconnected pad 20 between the two makes the pad 2 irregular and connects the bonding wire 21.
It becomes easy for 0 to concentrate in one place.

Then, the bonding wire 21 inevitably becomes long, and the bonding wire 21 becomes the chip 19.
There is a problem in that it is difficult to manufacture due to the fact that the frame 22 is electrically short-circuited due to the contact with the frame 22 and the shape of the frame 22 is complicated, resulting in a decrease in product yield and reliability.

According to the invention of claim 1, at a connection point between an input / output port designated by one address and a data signal line connected to the input / output port, an arbitrary bit is selected from a plurality of bits of the data signal line. It is an object of the present invention to obtain a semiconductor integrated circuit capable of selecting.

An object of the present invention is to provide a semiconductor integrated circuit capable of preparing a plurality of decode signals connected to a plurality of input / output ports and switching the combination of the input / output ports and the decode signals.

According to a third aspect of the present invention, a semiconductor integrated circuit capable of selecting an arbitrary signal from a plurality of dedicated input / output signals at a connection point of dedicated input / output signals of peripheral functions connected to each bit of the input / output port. Aim to get.

[0019]

According to another aspect of the present invention, there is provided a semiconductor integrated circuit for inputting, outputting or inputting / outputting data to / from an external device, and selecting a plurality of bits selected by one of a combination of address signals. An input / output port unit having an input / output port is provided, and a combination of bits of a data signal line connected in a one-to-one correspondence with each bit of each input / output port can be arbitrarily switched by a switch. It was done.

A semiconductor integrated circuit according to the invention of claim 2 is
Input / output of data to / from the outside and input / output, and input / output port means having an input / output port having a plurality of bits selected by one of a combination of address signals are provided, and each of the input / output ports is configured. Addresses assigned to a plurality of bit groups are changed by each bit by a switch for address selection.

A semiconductor integrated circuit according to the invention of claim 3 is
Input / output or input / output of data with the outside is provided, and input / output port means having an input / output port having a plurality of bits selected by one of combinations of address signals is provided for controlling timers, interrupts, etc. The connection between a dedicated input / output signal line for signals or the like and any one of the above input / output port means is switched by a switch.

[0022]

In the semiconductor integrated circuit according to the invention of claim 1, the switching signal inputted to the switching device is controlled to "H '" or "L', and the data signal line connected to the latch / direction register of the input / output port is controlled. Switch the bit and change the bit of the data that the I / O port has.

According to another aspect of the semiconductor integrated circuit of the present invention, by controlling the switching signal, the decode signal connected to a plurality of bits of the input / output port is switched by the switching unit. Change the address of.

According to another aspect of the semiconductor integrated circuit of the present invention, by controlling the switching signal, the bit of the input / output port to which the dedicated input / output signal is connected is switched and the terminal to which the dedicated input / output signal is input / output is changed. To do.

[0025]

EXAMPLES Example 1. An embodiment of the invention of claim 1 will be described below with reference to the drawings. In FIG. 1, 1 is a switching device, 2
Is a latch / direction register as input / output port means, 3
Is a pad, 4a to 4b are data signal lines connected to the switch 1, 5 is a data signal line connected from the switch 1 to the latch / direction register 2, 6a is a decode signal line of the latch / direction register 2, and 7a Is a switching signal line of the switching device.

Next, the operation will be described. First, the switching device 5 receives a switching signal input through the switching signal line 7,
The data signal on the data signal line 5 connected between the switch 1 and the latch / direction register 2 is switched to either the data signal line 4a or the data signal line 4b. By doing so, the data bus signal line input to the latch / direction register 2 can be switched from DB0 to DB1.

FIG. 2 is a circuit diagram showing the details of the switching device 1. In FIG. 2, 8a and 8b are N-channel transistors, 9a and 9b are P-channel transistors, 10 is an inverter circuit, and 11a and 11b are switching devices. 1 input signal line.

Further, 12 is a switching signal line of the switching device 1, and 13
Is an output signal line of the switching unit, and an input signal line 11 of the switching unit 1
a and 11b are the data signal lines 4a and 4b of FIG. 1, respectively.
In addition, the switching signal line 12 of the switching device 1 is the switching signal line 7 of FIG.
In addition, the output signal line 13 of the switch 1 is the data signal line 5 of FIG.
Respectively connected to.

In the circuit shown in FIG. 2, when the voltage level of the switching signal line 12 of the switch 1 is "L '", the output of the inverter circuit 10 becomes "H" and the N-channel transistor 8a and the P-channel The transistor 9a is turned on, and the N-channel transistor 8b and the P-channel transistor 9b are turned off. As a result, the input signal of the input signal line 11a is output to the output signal line 13, and the data signal of the data signal line 4a in FIG. 1 is input to the latch / direction register 2 through the data signal line 5.

Further, when the voltage level of the switching signal line 12 of the switch 1 is "H ', the output of the inverter circuit 10 is" H ".
L ', the N-channel transistor 8a and the P-channel transistor 9a are turned off, and the N-channel transistor 8b and the P-channel transistor 9b are further turned on.
Turns on. As a result, the signal input to the input signal line 11b is output to the output signal line 13 of the switch.

Further, in this circuit, the input signal lines 11a,
The input signal line 11b and the output signal line 13 may have the opposite input / output relationship. In that case, the switching signal line 12 of the switching device
, The input signal of the output signal line 13 is output to the input signal line 11a, and when the voltage level of the switching signal line 12 of the switch is "L ', the input signal of the output signal line 13 Will be output to the input signal line 11b.

Considering this embodiment for a semiconductor integrated circuit as shown in FIG. 10, for example, in the case of an 80-pin package, the ports P71 to P77 are connected to consecutive bits from the data signal DB1 to the data signal DB7, respectively. However, in the case of the 64-pin package, since only the data signal DB1, the data signal DB2, and the data signal DB7 are connected, the data signal DB1 to the data signal DB3 can be connected to the data bus of continuous bits.

As a result, for example, when outputting 3-bit data to the port P71, port P72, and port P77, in the conventional case, the operation is performed such that the third bit data becomes the seventh bit data. It is necessary to write the data to the port P7 at the time of
All you have to do is write to 7.

Example 2. FIG. 3 shows an embodiment of the invention of claim 2, in which 1A is a switch, 2 is a latch / direction register as input / output port means, 3 is a pad, and 4 is a pad.
a is a data signal, 6a and 6b are decode signal lines connected to the switch 1, 7 is a switch signal line of the switch, and 14 is a decode signal line of the latch / direction register 2.

In this embodiment, when a switch signal is input to the switch 1 through the switch signal line 7, the switch 1A causes the decode signal line 14 of the latch / direction register 2 to be connected to the decode signal line 6a or the decode signal line 6b. One of the two decode signals is selected by switching and connecting one of the two.

Further, in this embodiment, for example, the port P6 and the port P assigned to two consecutive addresses are assigned.
7, data signal DB0 to data signal DB3 of one port P6, data signal D of the other port P7
When B4 to signal DB7 are required, port P6 and port P7 can be combined and used as a bit port.

As a result, when outputting 8-bit data, it is necessary to separately output the data to the port P6 and the port P7 in the conventional case, but according to this embodiment, the 8-bit data can be output at a time. There is an effect that can be output.

The above is a description of a certain condition. Since an arbitrary data bus can be selected for each bit of the port, the port P6 outputs the data signal DB.
0, port P7 is data signal DB1 to data signal DB7
, The port P6 outputs the data signal DB0 and the data signal D.
Even if the port P7 is B2, data signal DB4, or data signal DB6 and the port P7 is data signal DB1, data signal DB3, data signal DB5, or data signal DB7, it can be arranged at an address having one 8-bit data. .

Generally, one address indicated by the address signal is assigned with a set of 8 bits of data.

Also, in this circuit, the one in which the decode signal is switched has been described, but even if the address signal input to the decode circuit (not shown) for creating the decode signal is switched, the same operation as that of the above-described embodiment is realized. it can.

Example 3. FIG. 4 shows claims 1 and 2.
Another embodiment of the present invention is shown, in which 1, 1A is a switch, 2 is a latch / direction register, 3 is a pad, 4a and 4b are data signal lines connected to the switch 1, and 5 is a latch from the switch 1A. A data signal line connected to the / direction register 2.

Further, 6a and 6b are decode signal lines connected to the switch 1A, 7 is a switch signal line of the switch 1 and switch 1A, and 14 is a decode signal line of the latch / direction register 2.

In this circuit, according to the switching signal input to the switching device 1 and the switching device 1A through the switching signal line 7, the switching device 1 is connected to the data signal line 5 connected to the latch / direction register 2 and the data signal line 4a. Alternatively, one of the data signal lines 4b is switched and connected.

Further, the switch 1A switches and connects either the decode signal line 6a or the decode signal line 6b to the decode signal line 14 of the latch / direction register 2.

In this embodiment, the switch 1 and the switch 1
Although the switching signals of A are the same, they may be different signals.

In the above embodiment, the 2-input switch 1,
Although the one using the switch 1A is shown, a switch having three or more inputs may be used, and the above embodiments may be combined.

Example 4. FIG. 5 shows an embodiment of the invention of claim 3, in which 1B is a switching device, 2 and 2A are latch / direction registers as input port means, 3 and 3A are pads, and 7 is a switching device 1B. A signal line, 15 is a dedicated input / output signal line, and 16 and 16A are respective dedicated input / output signal lines connected from the respective latch / direction registers 2 and 2A to the switch 1B.

In this circuit, the switching signal input to the switching unit 1B through the switching signal line 7 causes the switching unit 1B to output the dedicated input / output signal line 15 to the output-side dedicated input / output signal line 16 or the dedicated input / output signal line 16A. You can switch to either.

In this embodiment, for example, the port P6
Dedicated input / output signal lines for signals TM0 to TM7 are connected to 0 to port P67, respectively.
When the signals M1, signal TM2, signal TM5, and signal TM7 are absolutely necessary, the dedicated input / output signal line for each signal can be connected to an arbitrary bit of the port P6.

As a result, port P60 to port P67
When connecting 4 of the 8 ports of
Port P60, Port P61, Port P65, Port P
Although the dedicated input / output signal line which is absolutely necessary is connected in the state of 67, according to this embodiment, it is possible to leave the continuous ports P60 to P63.

Example 5. FIG. 6 shows an embodiment of a circuit for generating a switching signal according to the inventions of claims 1 to 3, in which a pad 23 connected to a switching signal line 7 is connected to a power supply 24 using a bonding wire 21. The voltage level of the switching signal can be set to "H '" and "L'", respectively, by connecting to the pad 23 that is connected to the pad 23 or connected to the pad 23 that is connected to the ground 25.

[0052]

As described above, according to the first aspect of the present invention, input / output or input / output of data with the outside is performed, and an input having a plurality of bits selected by one of the combinations of address signals is input. Since the input / output port means having the output port is provided and the bit combination of the data signal lines connected in a one-to-one correspondence with each bit of each of the input / output ports is configured to be arbitrarily switched by the switcher, It is possible to obtain the effect that the bit of the data signal line connected to the latch / direction register of the input / output port can be switched to change the bit of the data of the input / output port.

As a result, when developing products of semiconductor integrated circuits having different numbers of pins with the same chip, the address and data buses can be regularly reordered, which has the effect of facilitating programming.

Further, since the bonding pad for inputting / outputting a necessary signal can be set at an arbitrary position,
The bonding pad without wire bonding can be set at an arbitrary position, and can be set at an optimum position when performing assembly, and it is not necessary to fabricate a frame or a chip, which facilitates design. There is an effect that what can be obtained.

According to the second aspect of the present invention, input / output or input / output of data with the outside is performed, and an input / output port having a plurality of bits selected by one of the combinations of address signals is provided. Since the output port means is provided and the address assigned to the plurality of bit groups forming each of the input / output ports can be changed bit by bit by the switch for address selection, By switching the decode signal connected to multiple bits of the output port with the switch, the bit unit address of the input / output port can be changed, and the address and data bus can be regularly arranged and changed in the same chip. Besides, whether it is easy to set the position of the bonding pad used for signal input / output or not wire bonding. The effect of which can be optimized to obtain.

According to the invention of claim 3, an input / output port having a plurality of bits for inputting, outputting or inputting / outputting data to / from the outside and having a plurality of bits selected by one of the combination of address signals Since the means is provided and the connection between the dedicated input / output signal line for controlling signals such as timers and interrupts and any one of the above input / output port means is configured to be switched by the switch, the dedicated input signal is input / output. There is an effect that a terminal whose terminal can be easily changed can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of a switch in FIG.

FIG. 3 is a block diagram showing a semiconductor integrated circuit according to an embodiment of the invention of claim 2;

FIG. 4 is a block diagram showing a semiconductor integrated circuit according to another embodiment of the invention of claims 1 and 2;

FIG. 5 is a block diagram showing a semiconductor integrated circuit according to an embodiment of the invention of claim 3;

FIG. 6 is a switch input circuit diagram showing a circuit for generating a switching signal in the inventions of claims 1 to 3;

FIG. 7 is a block diagram showing a conventional semiconductor integrated circuit.

FIG. 8 is a block diagram showing a semiconductor integrated circuit having a plurality of port latches and direction registers around a conventional semiconductor integrated circuit.

FIG. 9 is an explanatory diagram showing external terminals and internal terminals of a conventional semiconductor integrated circuit product.

FIG. 10 is an explanatory diagram showing a connection between a chip and a frame of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1, 1A, 1B switching device 2, 2A latch / direction register (input / output port means) 4a, 4b data signal line

Claims (3)

[Claims] 1. An input / output port means for inputting / outputting / inputting / outputting data to / from the outside and having an input / output port having a plurality of bits selected by one of a combination of address signals; A semiconductor integrated circuit comprising: a switch for arbitrarily switching a combination of bits of a data signal line connected in a one-to-one correspondence with each bit of an input / output port. 2. Input / output port means for inputting / outputting / inputting / outputting data to / from the outside and having an input / output port having a plurality of bits selected by one of a combination of address signals; A semiconductor integrated circuit comprising an address selection switcher for changing an address assigned to a plurality of bit groups constituting an input / output port for each bit. 3. An input / output port means for inputting, outputting or inputting / outputting data to / from the outside and having an input / output port having a plurality of bits selected by one of a combination of address signals, a timer and A semiconductor integrated circuit comprising a switch for switching connection between a dedicated input / output signal line for control signals such as interrupts and any one of the above input / output ports.