JPH09181260A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To freely select a plurality of functional modules and to assign an arbitrary module to a prescribed connecting section. SOLUTION: Multiplexers 5-11 which select the connecting destinations of functional modules 2-4, such as a timer, interruption controller, etc., and pads P1-P3 which become signal inputting-output sections are provided between the modules 2-4 and pads P1-P3. The multiplexers 5-11 are provided in the data inputting-outputting sections and I/O switching sections of the modules 2-4, are controlled by terminal function selecting signals, and assign various functional modules to the pads P1-P3 by assigning an arbitrary module 2, 3, or 4 to an arbitrary pad P1, P2, or P3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to any one of a plurality of functional modules.
The present invention relates to a technology effectively applied to the allocation of terminal functions selected by one functional module.

[0002]

2. Description of the Related Art According to a study by the present inventor, for example, RISC (Reduced Instructive) is used.
In a semiconductor integrated circuit device such as an on set computer) processor, a timer or DM is connected to one external terminal.
A (Direct Memory Access) controller (A) A plurality of function modules, which are peripheral circuits such as a controller, are assigned and control registers for controlling the function modules are set.
It is selected by activating any one of the functional modules.

As an example in which a semiconductor integrated circuit device of this kind is described in detail, Press Journal Co., Ltd., issued April 26, 1993, 1993 special issue, Volume 12, No. 7, Shigeru Kiura (ed. ) "Monthly Semicon
ductor World special issue The LSI-LSI
Device Guidebooks "P57 to P61, and this document describes the configuration and characteristics of the RISC processor.

[0004]

However, the present inventor has found that the method of selecting a functional module as described above has the following problems.

That is, since a predetermined plurality of functional modules are only assigned in advance to a predetermined single external terminal, only products having the same semiconductor chip and the same package are compatible. .

As a result, when the product development of the semiconductor integrated circuit device is carried out, it is necessary to change the design for changing the allocation of the terminal function, which increases the design and development cost and prolongs the development days. There was a problem.

An object of the present invention is to provide a semiconductor integrated circuit device capable of freely selecting a plurality of function modules and assigning any function module to a predetermined connecting portion.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor integrated circuit device of the present invention is provided with a functional module selection means for selecting an arbitrary functional module from a plurality of functional modules and assigning it to a predetermined electrode portion.

Further, in the semiconductor integrated circuit device of the present invention, the functional module selection means selects one of the signals output from one of the plurality of connection destinations based on the control input signal. It consists of a multiplexer to select.

Further, according to the semiconductor integrated circuit device of the present invention,
The microcomputer comprises a functional module selection means between a plurality of functional modules and a predetermined electrode portion.

As described above, since the allocation of the predetermined external terminals and the plurality of functional modules can be freely changed, many kinds of functional modules can be formed in advance and necessary functional modules can be selected. In addition, it is not necessary to change the design associated with the product development of the semiconductor integrated circuit device, the design and development cost can be significantly reduced, and the development days can be shortened.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a structural explanatory view of a terminal function selection portion and its peripheral portion provided in a semiconductor integrated circuit device according to one embodiment of the present invention, and FIG. 2 is a semiconductor integrated circuit according to one embodiment of the present invention. 3A and 3B are circuit diagrams of a terminal function selection unit provided in the circuit device, and FIGS. 3A and 3B are explanatory views showing an example of wire bonding in the semiconductor integrated circuit device according to the embodiment of the present invention.

In the present embodiment, the semiconductor integrated circuit device 1 which is a one-chip microcomputer has, as a peripheral circuit, a functional module 2 including a timer and a serial I / O (Input / Output).
There is provided a functional module 3 composed of, a functional module 4 composed of an interrupt controller, and the like.

Further, these functional modules 2 to 4 include
An input unit for inputting data, an output unit for outputting data, and an I / O switching unit for switching input / output of data are provided.

Further, the semiconductor integrated circuit device 1 is provided with multiplexers (functional module selection means) 5 to 11 which are selection changeover switches for selecting and outputting one of the two input sections based on the control signal. ing.

Each of the multiplexers 5 to 11 is provided with a module function selection section for switching a function module selected by a predetermined control signal, and the module function selection section has a terminal function selection signal (control signal). The terminal function selection signal line Ts is connected so that the control input signal) is input.

Further, one input section of the multiplexer 5 is connected to the output section of the functional module 2, and the other input section is connected to the output section of the functional module 3.

Further, one input portion of the multiplexer 6 is connected to the I / O switching portion of the functional module 2,
The other input section is connected to the I / O switching section of the functional module 3.

Here, one input section of the multiplexer 6 is connected to an I / O switching section in another functional module (not shown) provided in the semiconductor integrated circuit device 1.

The output of the multiplexer 7 is connected to the input of the functional module 2, one input of the multiplexer 8 is connected to the output of the functional module 3, and the other input is connected to the other input. , Is connected to the output of the functional module 4.

Further, the I / O switching unit of the functional module 3 is connected to one input unit of the multiplexer 9, and the I / O switching unit of the functional module 4 is connected to the other input unit.

The output of the multiplexer 10 is connected to the input of the functional module 3, and the output of the multiplexer 11 is connected to the input of the functional module 4.

Next, the semiconductor integrated circuit device 1 is provided with buffers 12 to 14 for temporarily storing input / output data and the like and adjusting a time lag.

The buffer 12 includes an OR circuit 12a,
NAND circuit 12b, NOR circuit 12c, inverter 1
2d to 12g, a P-channel MOS transistor 12h and an N-channel MOS transistor 12i.

The buffer 12 has a NOR circuit 12
One input section of c is connected to the output section of the multiplexer 5 and the other input section of the NAND circuit 12b, and the other input section is connected to the output section of the inverter 12d.

The output portion of the NOR circuit 12c is connected to the input portion of the inverter 12e, and the inverter 12e
The output of e is connected to the gate of transistor 12i.

Further, the output portion of the OR circuit 12a is connected to the input portion of the inverter 12g, and the inverter 12g
The output part of g is connected to one input part of the multiplexer 7 and the other input part of the multiplexer 10, respectively.

The other input section of the multiplexer 7 is connected to the output section of the buffer (not shown) of the other functional module described above.

One input of the OR circuit 12a is connected to the input of the inverter 12d, one input of the NAND circuit 12b and the output of the multiplexer 6.

Next, the output part of the NAND circuit 12b is connected to the inverter 12f, and the output part of the inverter 12f is connected to the gate of the transistor 12h.

The output of the transistor 12h is connected to the ground potential, and the input of the transistor 12i is
Connected to power supply voltage.

Further, the input part of the transistor 12h is
It is connected to the output part of the transistor 12i, and the connection part of the transistors 12h and 12i and the other input part of the OR circuit 12a are connected to a pad (electrode part) P1 which is an electrode provided in the semiconductor integrated circuit device 1. .

The pad P1 is electrically connected to a lead, which is an external lead wire, by a bonding wire by wire bonding.

Then, also in the buffers 13 and 14,
OR circuits 13a and 14a, NAND circuits 13b and 14
b, NOR circuits 13c and 14c, inverters 13d to 1
3f, 14d to 14f, transistors 13h and 14h which are P channel MOS transistors, and transistors 13i and 14i which are N channel MOS transistors.
And the circuit configuration thereof is similar to that of the buffer 12 described above.

The output of the multiplexer 8 is connected to one input of the NOR circuit 13c and the other input of the NAND circuit 13b in the buffer 13, and the output of the multiplexer 9 is one input of the OR circuit 13a. Section and the input section of the inverter 13d are connected.

Further, one input part of the multiplexer 10 is connected to the output part of the inverter 13g, and the other input part of the multiplexer 10 is connected to the output part of the inverter 12g.

Further, the connection portion of the transistors 13h and 13i and the other input portion of the OR circuit 13a are connected to a pad (electrode portion) P2 which is an electrode also provided in the semiconductor integrated circuit device 1.

Similarly, the pad P2 is also electrically connected to a lead, which is an external lead wire, by a bonding wire by wire bonding.

Next, in the buffer 14, the output section of the functional module 4 is directly connected to one input section of the NOR circuit 14c and the other input section of the NAND circuit 14b.

Similarly, the I / O switching section of the functional module 4 is also connected to one input section of the OR circuit 14a and the input section of the inverter 14d.

Further, one input portion of the multiplexer 11 is connected to the output portion of the inverter 14g, and the other input portion of the multiplexer 11 is connected to the inverter 13g.
Is connected to the output of.

Further, the connection portion of the transistors 14h and 14i and the other input portion of the OR circuit 14a are connected to a pad (electrode portion) P3 which is an electrode also provided in the semiconductor integrated circuit device 1.

Further, as described above, the pad P2 is also electrically connected to the lead which is the external lead wire by the wire bonding and the bonding wire.

Next, the circuit configuration of the multiplexers 5-11 will be described.

For example, the multiplexer 5 includes inverters Iv1 and Iv2, an AND circuit Ak, as shown in FIG.
1, Ak2 and NOR circuit Nk.

The module function selection section to which the terminal function selection signals in the multiplexers 5 to 11 are input is connected to one input section of the AND circuit Ak1 and the input section of the inverter Iv1.

Further, the other input section of the AND circuit Ak1 is connected so that the signal inputted to one input section of the multiplexers 5 to 11 is inputted, and the output section of the AND circuit Ak1 is It is connected to one input portion of the NOR circuit Nk.

Furthermore, the output of the inverter Iv1 is A
It is connected to one input section of the ND circuit Ak2, and is connected to the other input section so that the signal input from the other input section of the multiplexer 5 is input.

The output of the AND circuit Ak2 is connected to the other input of the NOR circuit Nk, and the output of the NOR circuit Nk is connected to the input of the inverter Iv2.

The output of the inverter Iv2 serves as the output section of the multiplexers 5-11. Further, the circuit configurations of the multiplexers 6 to 11 are also the same as the circuit configuration of the multiplexer 5 shown in FIG.

Next, the operation of the present embodiment will be described.

For example, the Hi signal of the terminal function selection signal is input to the multiplexers 5 to 11 via the terminal function selection signal line Ts.

Here, the multiplexers 8 and 9 to which the Hi signal is input to the module function selection section have, as shown in FIG. 2 described above, one input section of the AND circuit Ak1 having the terminal function selection signal Hi. Signal is input, AND
The Lo signal inverted by the inverter Iv1 is input to one input portion of the circuit Ak2.

The output of the AND circuit Ak1 becomes a signal having the same logical value as the signal input to the other input section, that is, the signal output from the functional module 3, and AN
The output of the D circuit Ak2 has a Hi signal, Lo
The Lo signal is output regardless of which logical value of the signal is input.

Next, since the Lo signal is input to the other input section of the NOR circuit Nk, the output is the AND circuit A
The inverted signal is output as a logical value by being input to the other input portion of k1, and the logical value is inverted and output again by the inverter Iv2 connected to the subsequent stage of the NOR circuit Nk.

Therefore, the output of the multiplexer 8 outputs the signal of the logical value output from the functional module 3, and the functional module 3 is selected.

Next, in the multiplexer 9, when a signal is output from the output section of the functional module 3,
Since the Hi signal is also output from the I / O switching unit of the functional module 3, the Hi signal is also output from the output unit of the multiplexer 9.

While the signal is output from the output section of the functional module 3, the Hi signal is output from the I / O switching section, and the Hi signal is output from the output section of the multiplexer 9. Therefore, the OR in the buffer 13 is performed. The Hi signal is input to one input portion of the circuit 13a, one input portion of the NAND circuit 13b, and the input portion of the inverter 13d.

The Lo signal inverted by the inverter 13d is input to the other input section of the NOR circuit 13c, and one input section of the NOR circuit 13c and NA.
The multiplexer 8 is provided at the other input section of the ND circuit 13b.
The signal output from, that is, the signal output from the output unit of the functional module 3 is input.

Since the other input portion of the NOR circuit 13c is fixed to the Lo signal which is the output signal from the inverter 13d, the output portion of the NOR circuit 13c outputs the signal output from the multiplexer 8. An inverted signal is output.

At the same time, one input portion of the NAND circuit 13b is fixed to the Hi signal, and the NAND circuit 13b is also fixed.
The inversion signal of the signal output from the multiplexer 8 is also output from the output section of.

Then, these NAND circuits 13b, NO
The output signals of the R circuit 13c are output from the inverter 13 respectively.
Inverted by e and 13f.

For example, when a Hi signal is output from the output section of the functional module 3, the transistors 13h and 13 are
Since the Hi signal is input to the gate of i, the transistor 13i which is a P-channel transistor is in the non-conduction state,
That is, it is turned off, and the transistor 13h, which is an N-channel transistor, is turned on, which is a conductive state,
The Lo signal is output to the pad P2.

From the output of the functional module 3, Lo
When a signal is output, the outputs of the NAND circuit 13b and the NOR circuit 13c become a Hi signal, which is inverted by the inverters 13e and 13f provided in the subsequent stage.

Therefore, the Lo signal is input to the gates of the transistors 13h and 13i, and the transistor 13i becomes O.
Since it becomes N and the transistor 13h is turned off, the Hi signal is output to the pad P2.

When the signal of this functional module 3 is output, OR
Since one input portion of the circuit 13a is fixed to the Hi signal output from the multiplexer 9, the OR circuit 13a
Even if either the Hi signal or the Lo signal is input to the other input portion of a, the output of the OR circuit 13a is fixed to the Hi signal, and the fixed Hi signal is output by the inverter 13g provided in the subsequent stage. Inverted, multiplexer 1
It is input to one input section of 0 and the other input section of the multiplexer 11.

Next, when a signal is input from the pad P2 through the external lead wire, the Lo signal is output from the I / O switching section of the functional module 3.

Since the Lo signal is also output from the multiplexer 9, one input portion of the NAND circuit 13b is fixed to the Lo signal, and the other input portion of the NOR circuit 13c has the Hi signal inverted by the inverter 13d. Fixed to.

Then, the output of the NAND circuit 13b is fixed to the Hi signal even if the logical value of one input portion changes,
The Lo signal inverted by the inverter 13f is input to the gate of the transistor 13h.

The output of the NOR circuit 13c is fixed to the Lo signal even if the logic value of the other input section changes, and the Hi signal inverted by the inverter 13e is input to the gate of the transistor 13i.

Therefore, the transistors 13h and 13i are turned off, and no signal is output to the pad P2.

The signal input from the pad P2 is
It is input to the other input section of the OR circuit 13a. here,
The multiplexer 9 is provided at one input portion of the OR circuit 13a.
Since the fixed signal of the Lo signal output from is input, the signal input from the pad P2 is output to the output section of the OR circuit 13a, and the signal is inverted by the inverter 13g provided in the subsequent stage to function. It will be input to the input section of the module 3.

Next, the case where the Lo signal of the terminal function selection signal is input to the multiplexers 5 to 11 via the terminal function selection signal line Ts will be described.

Here, each of the multiplexers 8 and 9 to which the Lo signal is input to the module function selection section has the Lo of the terminal function selection signal input to one input section of the AND circuit Ak1 as shown in FIG. Signal is input, AND
The Hi signal inverted by the inverter Iv1 is input to one input portion of the circuit Ak2.

The output of the AND circuit Ak1 becomes a Lo signal regardless of the logical value of the other input portion because the Lo signal is input to one input portion, and the output of the AND circuit Ak2 becomes one. Since the Hi signal is input to the input section of, the signal has the same logical value as the signal output from the functional module 4.

Next, since the Lo signal is input to one of the input sections of the NOR circuit Nk, the output is the AND circuit A
The inverted signal is output to the logical value by being input to the other input portion of k2, and the logical value is inverted and output again by the inverter Iv2 connected to the subsequent stage of the NOR circuit Nk.

Therefore, the signal of the logical value output from the functional module 4 is output from the output section of the multiplexer 8, and the functional module 4 is selected.

Next, in the multiplexer 9, when a signal is output from the output section of the functional module 4,
Since the Hi signal is also output from the I / O switching unit of the functional module 4, the Hi signal is also output from the output unit of the multiplexer 9.

The signal input from the pad P2 via the external lead wire is the OR circuit 13a and the inverter 13g.
Is output to the multiplexers 10 and 11 via the above. However, since the other input portion of the multiplexers 10 and 11 is selected by the Lo signal of the terminal function selection signal described above, the signal output from the inverter 13g is It is input to the input section of the functional module 4.

Therefore, by setting the terminal function selection signal to the Lo signal, the input / output signal of the functional module 4 is input / output via the pad P2. Similarly, the input / output signals of the functional module 3 are input / output via the pad P1.

Next, a generation example of the terminal function selection signal on the terminal function selection signal line Ts will be described with reference to FIGS. 3 (a) and 3 (b).

First, in order to generate the terminal function selection signal on the terminal function selection signal line Ts, as shown in FIG. 3A, a dedicated bonding pad PT is previously formed at the end of the terminal function selection signal line Ts. Then, at the time of bonding with the bonding wire W, it is selected whether the terminal function selection signal on the terminal function selection signal line Ts is the Hi signal or the Lo signal.

For example, when the terminal function selection signal is the Hi signal, since the Hi signal must be supplied to the pad PT as well, it is bonded to the pad Pv for the internal power supply line connected to the wiring Hv for the power supply voltage. By wire-bonding the above-mentioned pad PT to the lead Lv, which is a terminal for supplying a power supply voltage electrically connected by the wire W, also by the bonding wire W,
H for the terminal function selection signal on the terminal function selection signal line Ts
Generate the i signal.

When the terminal function selection signal is the Lo signal, wire bonding between the lead Lv and the pad PT is not performed at the time of bonding.

Next, as shown in FIG. 3B, the generation of the terminal function selection signal in the terminal function selection signal line Ts is performed by wiring normally connected to another lead L, pad Pn and pad Pn. Similar to Hn, a dedicated bonding pad PT is provided in advance on the end of the terminal function selection signal line Ts.
And a dedicated lead Lt is formed, and a Hi signal or L which is a terminal function selection signal is externally supplied via this lead Lt.
The o signal may be supplied.

In this case, the user can arbitrarily select whether the terminal function selection signal supplied to the lead Lt is the Hi signal or the Lo signal.

Therefore, according to the present embodiment, the functional modules 2 to 11 which require the multiplexers 5 to 11 based on the terminal function selection signal on the terminal function selection signal line Ts.
4 can be selected, the design change accompanying the product development of the semiconductor integrated circuit device 1 becomes unnecessary, and the design and development cost can be reduced.

Further, in the present embodiment, the terminal function selection signal on the terminal function selection signal line Ts is supplied to the lead Lv which is a terminal for supplying the power supply voltage and the pad Pv for the internal power supply line.
It is generated whether or not is connected by a bonding wire W or by externally supplying a terminal function selection signal via a lead Lt. However, for example, selection for generating a predetermined terminal function selection signal by setting a program. The terminal function selection signal may be generated by setting a signal generator (not shown) or a control register (not shown).

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above embodiment, the number of the terminal function selection signal lines is one, and the multiplexer is controlled by the 2-bit terminal function selection signal of the Hi signal and the Lo signal. It is possible to select an arbitrary functional module from a larger number of functional modules and allocate it to a predetermined pad by increasing the number of lines and controlling the multiplexer.

[0094]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the function module selecting means can freely change the allocation of a predetermined electrode portion and a plurality of function modules.

(2) Further, in the present invention, by the above (1), the design change accompanying the product development of the semiconductor integrated circuit device becomes unnecessary, the design development cost can be greatly reduced, and the development days can be shortened. be able to.

[Brief description of the drawings]

FIG. 1 is a configuration explanatory diagram of a terminal function selection unit and its peripheral portion provided in a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a terminal function selection unit provided in the semiconductor integrated circuit device according to the embodiment of the present invention.

3A and 3B are explanatory views showing an example of wire bonding in a semiconductor integrated circuit device according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 semiconductor integrated circuit device 2 functional module 3 functional module 4 functional module 5-11 multiplexer (functional module selection means) 12 buffer 12a OR circuit 12b NAND circuit 12c NOR circuit 12d-12g inverter 12h transistor 12i transistor 13 buffer 13a OR circuit 13b NAND Circuit 13c NOR circuit 13d to 13g Inverter 13h Transistor 13i Transistor 14 Buffer 14a OR circuit 14b NAND circuit 14c NOR circuit 14d to 14g Inverter 14h Transistor 14i Transistor P1 to P3 Pad (electrode part) PT Pad Pv Pad Pn Inverter Iv1 Inverter Iv1 AND circuit Ak2 AND circuit Nk NOR circuit W Bonde Nguwaiya Ts terminal function selection signal line Lv lead Lt lead L lead

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sonei Nagasaki 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division

Claims (3)

[Claims] 1. A semiconductor integrated circuit device comprising: a functional module selecting means for selecting an arbitrary functional module from a plurality of functional modules and allocating it to a predetermined electrode portion. 2. The semiconductor integrated circuit device according to claim 1, wherein the functional module selection means outputs from one connection destination among signals output from a plurality of connection destinations based on a control input signal. A semiconductor integrated circuit device comprising a multiplexer for selecting a signal. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the function module selecting means is provided between the plurality of function modules and the predetermined electrode section. Semiconductor integrated circuit device.