JPH01125017A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a switching means, and also, to apply a normal signal to an internal circuit by inserting a buffer means between each of plural external signal use bonding pads and the switching means. CONSTITUTION:Between a bonding pad 1a and a transistor 3, inverters 14, 15 are connected in series. Also, between a bonding pad 1c and a transistor 6, inverters 18, 19 are connected in series. Moreover, between a bonding pad 1b and a node D placed between transistors 4, 5, inverters 16, 17 are connected. In such a way, even if the input signal of the bonding pad is TTL level, and even in case of a negative voltage, said signal is inputted in a MOS level to an internal circuit by the inverters 14-18. Accordingly, even in case of any external signal, such a failure as the transistor which is to be in an OFF state goes to on state as a conventional example is not generated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a plurality of bonding pads for one internal circuit, and using the bonding pads by switching as necessary. The present invention relates to a semiconductor device.

[Prior Art] FIG. 2 is a diagram showing a part of a pad switching circuit using conventional bonding. In FIG. 2, the bonding pad 1a is a zigzag in-line (hereinafter referred to as ZIL)
The bonding pad 1b is the A7 signal pad of the package, and the bonding pad 1b is the A7 signal pad of the dual in-line (hereinafter referred to as DIP) package, and the ZI
L A8 signal pad, bonding pad 1c
is a DIP A8 signal pad. An n-channel MO3) transistor 3 is connected between pad 1a and pad 1b.
．． 4 are connected in series, and n-channel MO transistors 5 and 6 are connected in series between pad 1b and pad IC. Further, pad la and pad IC are each grounded via an n-channel MOS transistor 2.7. Further, node A between transistors 3 and 4 is connected to an internal A7 buffer circuit-8a, and node B between transistors 5 and 6 is connected to an internal A8 buffer circuit 8b. A switching signal PC is input to the gates of the n-channel MOS transistors 3, 5, and 7.
A complementary switching signal is input to the gates of n-channel MOS transistors 2, 4, and 6.

FIG. 3 is a diagram showing a switching signal (PC, PC) generation circuit. In FIG. 3, the switching signal generating circuit includes switch switching bonding pads 9. to which wires 13 for wire bonding are bonded. Inverter 10.11 and n-channel MO8) transistor 12
, the output of the inverter 10 is under the complementary switching signal, and the output of the inverter 11 is under the switching signal P.
Becomes C.

Next, the operation of the conventional semiconductor device will be explained.

First, a case will be described in which a semiconductor chip is mounted in a DIP package, that is, a case in which the power supply terminal on the package and the switch switching bonding pad 9 are not connected. At this time, the node C shown in FIG. 3 becomes "L" level because the n-channel MO8) transistor 12 is always in a conductive state. Therefore, the auxiliary switching signal PC goes to the "H" level, while the switching signal PC goes to the 'L' level. Therefore, in FIG. 2, transistors 2.4 and 6 are in the ON state,
Transistors 3.5 and 7 are turned off. As a result, bonding pad 1b is connected to internal A7 buffer circuit 8a, bonding pad IC is connected to internal A8 buffer circuit 8b, and bonding pad 1a is isolated from the internal buffer circuit.

Next, the case of mounting on a zIL package, that is, the case of connecting the power supply terminal on the package and the switch switching bonding pad 9 using the bonding wire 13 will be described. At this time, since the power supply voltage is supplied to the bonding pad 9, the switching signal P
C becomes “H” level, and the auxiliary switching signal PC becomes “H” level.
becomes L” level. Therefore, bonding pad 1a
is connected to internal A7 buffer circuit 8a, bonding pad 1b is connected to internal A8 buffer circuit 8b, and bonding pad 1c is isolated from the internal buffer circuit.

As described above, depending on whether or not the power supply terminal on the package is bonded to the switch switching bonding pad 9, one bat of the A7 signal bonding pads la, 1b(7) 5 for ZIL and DIP is internally connected. A
7 buffer circuit 8a. The same applies to the A8 signal bonding pads lb and lc.

As a result, even though two bonding pads for external signals are provided on the semiconductor chip, the input capacitance seen from the external signal input bin is based on only one bonding pad for external input signals on the chip. It is almost equal to the input capacitance when it is provided. Also, bonding pad 1
Focusing on point b, it is possible to share the DIP A7 signal bonding pad and the ZILJ11A8 signal bonding pad, and the number of bonding pads can be reduced. Thereby, the area of the chip can be used effectively.

rThe problem to be solved by the invention: Since the conventional pad switching circuit using bonding is configured as described above, when it is used as a DIP package, that is, when the auxiliary switching signal is at "H" level, the next There were problems such as TT
When the "H2 level" of the input signal of the bonding pad 1b for L person level 7 DIP is set to 2.4V, if the "L" level of the input signal of the bonding pad 1c for AgDIP becomes 12V, , OFF
The source-gate voltage of the transistor 5 in the current state becomes higher than the threshold voltage V, and the transistor 5 becomes ON, and the "H" level of the human input signal of the internal A7 buffer circuit 8a decreases, so that the internal A7 buffer circuit 8a causes malfunction.

Therefore, this invention was made to solve the above-mentioned problems, and it is possible to prevent the internal circuit from malfunctioning even when the L2 level of the input signal of the signal bonding pad becomes a negative voltage. An object of the present invention is to provide a semiconductor device having a pad switching circuit as described above.

[Means for Solving the Problems] A semiconductor device according to the present invention includes a semiconductor chip, an internal circuit provided on the semiconductor chip, and a plurality of external circuits provided on the semiconductor chip and connected to the internal circuit. A semiconductor device including a signal bonding pad and a switching means provided in each connection path between each external signal bonding pad and an internal circuit to selectively connect one of the external signal bonding pads to the internal circuit. , a buffer means is provided between each external signal bonding pad and the switching means.

[Function] In the semiconductor device according to the present invention, the buffer means inserted between each of the plurality of external signal bonding pads and the switching means keeps the potential of the external signal at a potential level at which the switching means operates accurately. , and converts it to a potential level used in internal circuits.

[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the invention. 1, the difference from the conventional semiconductor device shown in FIG. 2 is that inverters 14 and 15 are connected in series between bonding pad 1a and transistor 3, and bonding pad IC and transistor 6 are connected in series. Inverters 18, 19 are connected in series between the bonding pad 1b and the node D between the transistor 4.5, and the inverter 16, 17 is connected between the bonding pad 1b and the node D between the transistor 4.5. Since the configuration is similar to that shown in FIG. 2, the same parts are given the same reference numerals and the explanation thereof will be omitted.

Next, the operation will be explained. Similar to the conventional example, DIP
When mounting a semiconductor chip in a package for use with a semiconductor device, the switching signal PC becomes 'L' level and the auxiliary switching signal PC becomes 'H' level. Therefore,
n-channel MO8) transistors 2, 4 and 6 are ON
state, and n-channel MOS transistors 3.5 and 7 are turned off. Therefore, A7(ZIL
) bonding pad 1a is separated from the internal buffer circuit.

Now, let's consider the input at the TTL level. When the input signal A7 (DIP) of bonding pad 1b is set to 2.4V at "H" level, bonding pad I
Even when the human input signal A8 (DIP) of C becomes a "L" level negative voltage, the node D is connected to the inverters 16 and 17.
Therefore, the MOS level becomes 5V. Further, the node E between the transistor 6 and the inverter 19 is also connected to the inverter 1.
8 and 19 result in Ov. Therefore, node D
The potential of the node E is applied to the internal A7 buffer circuit 8a via the n-channel MOS transistor 4, and the potential of the node E is applied to the internal A8 buffer circuit 8b via the n-channel MO3 transistor. That is, even if the input signals to the bonding pads (1b and lc in this case) are at TTL level or negative voltage, the internal circuits are supplied with MOS level (H" level -5v, "L0" level) by inverters 14 to 18. It is input at level -0V).

Therefore, no matter what kind of external signal there is, there will be no problem such as in the conventional example where a transistor that is supposed to be in an OFF state remains ON.

Note that when PC is at the "H" level and T is at the "L" level, the A8 (DIP) bonding pad IC is disconnected from the internal buffer circuit and applied to the A7 (Z I L) bonding pad 1a. The external signal is applied to the internal A7 buffer circuit 8a, and the external signal applied to the A8 (ZIL) bonding pad 1b is applied to the internal A8 buffer circuit 8b. Also in this case, each inverter performs the same function as described above.

In addition, in the above-mentioned embodiment, the DIP package and the ZIL
Although the description has been made regarding the package for the above, it goes without saying that it can be used for other packages as well.

Furthermore, the present invention can be applied to devices in which the mode of the same chip is changed by bonding switching, such as changing the word structure from IM.times.1 to 256K.times.4 in a dynamic RAM.

[Effects of the Invention] As described above, according to the present invention, between each of the plurality of external signal bonding pads and the switching means,
By inserting the buffer means, the external signal is converted to a potential level that allows the switching means to operate accurately and is also used in the internal circuit, so that it is possible to prevent malfunction of the switching means, and also to prevent the internal circuit from malfunctioning. can give a normal signal.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a diagram showing part of a pad switching circuit using conventional bonding. FIG. 3 shows a switching signal generating circuit applied to an embodiment of the present invention and used in a conventional semiconductor device. In the figure, 1a is the A7 signal bonding pad for ZIL, 1b is the A7 signal for DIP and A8 for ZIL.
Bonding pad shared with signal, IC is A8 signal bonding pad for DIP, 2 to 7 are n-channel MO3) transistors, 8a is internal A7 buffer circuit, 8
b indicates an internal A8 buffer circuit, and 14 to 19 indicate inverters. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] (1) a semiconductor chip; an internal circuit provided on the semiconductor chip; a plurality of external signal bonding pads provided on the semiconductor chip and connected to the internal circuit; and a plurality of external signal bonding pads provided on the semiconductor chip and connected to the internal circuit. A semiconductor device including a switching means provided in each connection path between each of the plurality of external signal bonding pads and the internal circuit, and selectively connects one of the plurality of external signal bonding pads to the internal circuit. A semiconductor device comprising a buffer means between each of the external signal bonding pads and the switching means. (2) The semiconductor device according to claim 1, wherein the buffer means comprises logic circuit means. (3) The semiconductor device according to claim 2, wherein the buffer means includes a plurality of inverters. (4) The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor chip includes a switch switching bonding pad into which a signal for determining the selection state of the switching means is input. .