JPH0430396A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To supply a general article for normal and a special article for low voltage action by the same chip by constituting so as to select and to switch either a first sense amplifier or a second one. CONSTITUTION:When a selecting signal 24 becomes an 'H' level, a normal sense amplifier 14 becomes inable when a signal, the inverse of ce 1 is an 'L' level. Then, the information of a selected memory cell appears on a drain line 4, is discriminated to be '1' or '0' by the amplifier 14 and an NAND circuit 22 and is outputted to an output 2. The amplifier 14 is selected by wire-bonding the signal 24 with a power source Vcc in this way. Next, when the signal 24 becomes the 'L' level, a sense amplifier for low power source voltage action 23 becomes inable when the signal 1 is the 'L' level. Then, the information of the selected memory cell appears on the line 4, is discriminated to be '1' or '0' by the amplifier 23 and the circuit 22 and is outputted to the output 2. The amplifier 23 is selected by wire-bonding the signal 24 with GND.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device whose operating power supply voltage range can be switched by a wire bonding process.

[Conventional technology]

FIG. 4 is a circuit diagram of a conventional semiconductor memory device. In the figure, (1) is a chip enable signal (hereinafter referred to as a), (
2) is the sense amplifier output, (3) is the memory cell array,
(4) is the drain line of the memory cell, and (5) is the drain line of the memory cell.

0υ, a is a P-channel MO3) transistor, (6) ~
αQ.

03 is an N-channel MO3) transistor, and MOS1-transistors (5) to a3 constitute a sense amplifier 04). When the address is fixed by external address input, one memory cell in the memory cell array (3) is determined, the information is applied to the drain line (4) of the memory cell, and is set to "1" by the sense amplifier 04). “0”
is determined and output to the sense amplifier output (2).

Next, the operation will be explained. The sense amplifier 04) is enabled when the e signal (1) is at the "L" level, and is in a standby state when the (2) signal is at the "H" level. When the sense amplifier 04) is enabled and the drain line (4) of the memory cell is at the "L" level, the sense amplifier output (2) outputs the "H" level, and the drain line 0a of the memory cell is at the "H" level. At this time, the sense amplifier output (2) outputs "L" level.

The sense amplifier 04 is a normal sense amplifier whose operating power supply voltage range is optimized around the standard value of the power supply voltage within the product specifications, and low power supply voltage operation is generally guaranteed outside the product specifications. However, with the spread of IC carts in recent years, the demand for products that operate at low power supply voltages has increased.

[Problem to be solved by the invention]

Conventional normal sense amplifiers are configured as described above, so it is difficult to guarantee low power supply voltage operation while satisfying product standards when used. Since power supply voltage operation cannot be guaranteed, stable supply is difficult. Therefore, in order to stably supply low power supply voltage operation products, it is necessary to change from a normal sense amplifier to a sense amplifier for low power supply voltage operation that is optimized for low power supply voltage operation. There was a problem that it was necessary to change the pattern.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a semiconductor memory device that can supply power supply voltage operating products and low power supply voltage operating products within product specifications without changing the pattern. do.

[Means to solve the problem]

A semiconductor memory device according to the present invention includes a normal sense amplifier and a sense amplifier for low power supply voltage operation, and is capable of switching the operating power supply voltage range by selecting one of the sense amplifiers through a wire bonding process. .

[For production]

Since the sense amplifier according to the present invention is configured to select and switch between the first and second sense amplifiers, it is possible to supply a general product for normal use and a special product for low voltage operation using the same chip. can.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, decoding (1) to (141) are the same as the conventional one, so the explanation thereof will be omitted. In the figure, (15).

(21) is a P-channel MOS transistor, (16) -
(20) is an N-channel MOS transistor, and the MOS transistors (15) to (21) constitute a sense amplifier (23) for low power supply voltage operation. (22) is a NAND that combines the final inverter circuit of the normal sense amplifier (+4) and the sense amplifier for low power supply voltage operation (23).
In the circuit, (24) is a select signal determined by wire bonding, (25), (28), and (29) are inverter circuits, and (26) and (27) are NOR circuits.

Figure 2 is an explanatory diagram showing the relationship between the wire bond and the select signal (24). In the figure, there is an empty pad inside the chip next to the Vcc power supply pad and the GND pad connected by AI wiring. . In the figure, the level of the select signal (24) is set to the "H" level by wire-bonding the empty pad on the Vee power supply side to the VEC power supply. Figure 3 shows that the level of the 5elect signal (24) is set to “L” by wire-bonding the empty pad on the GND side to GND.
``It's on a level.

Next, the operation will be explained. The sense amplifier 0 is a sense amplifier that is optimized to satisfy the operating power supply voltage range within the product specifications, and the sense amplifier (23) is a sense amplifier for low power supply voltage operation that is optimized for low power supply voltage operation. It is. First, the operation when a normal sense amplifier is selected will be described. As shown in FIG. 2, the wire bonding at this time is to wire-bond the V-power source to the empty bat next to the V-e power source pad. Then, the select signal (24) becomes "H" level. Here, when the select signal (24) in FIG. 1 becomes "H" level, the select signal (24)
The output of the NOR circuit (27) powered by 4) is at the "L" level regardless of the input of the signal (1), and the "H" level signal inverted by the inverter circuit (29) is sent to the sense amplifier (23). ) is input. Then, the sense amplifier (23) for low power supply voltage operation becomes disabled, and the "H" level is always input to the NAND circuit (22). On the other hand, "L" level is input to the NOR circuit (26) to which the inverted signal of the select signal (24) is input. Normal sense amplifier 04) is high signal (1
) is enabled when the signal is at "L" level, and disabled when it is at "H" level. Normal sense amplifier 04
) is enabled, the information of the selected memory cell is applied to the drain line (4) and the normal sense amplifier (
“l” or “0” by 14+ and NAND circuit (22)
is determined and output to the sense amplifier output (2). By wire-bonding the select signal (24) to the V te power supply in this way, the normal sense amplifier is selected.

Next, the operation when the sense amplifier for low power supply voltage operation is selected will be described. At this time, as shown in FIG. 3, wire bonding is performed between the empty pad next to GND and GND.

Then, the select signal (24) becomes "L2 level. Here, the select signal (24) in FIG. 1 becomes "L2 level.
" level, an "H" level signal, which is an inverted signal of the select signal (24), is input to the NOR circuit (26), and the output of the NOR circuit (26) becomes ", regardless of the input of the a signal (1). The inverter circuit (28
) is input to the sense amplifier (14). Then, the normal sense amplifier (14) becomes disabled and the NAND
The "H" level is always input to the circuit (22). On the other hand, the NOR circuit (27) inputs the select signal (24).
) is input with the "L" level. The sense amplifier (23) for low power supply voltage operation is enabled when the e signal (1) is at "L" level, and disabled when it is at "H" level.

When the sense amplifier (23) for low power supply voltage operation is enabled, the information of the selected memory cell is transferred to the drain line (4).
, the sense amplifier for low power supply voltage operation (23) and the NAND circuit (22) determine whether it is "L" or "0" and output to the sense amplifier output (2). By wire-bonding the select signal (24) to GND in this manner, a sense amplifier for low power supply voltage operation is selected.

Table 1 shows a mode table showing the relationship between wire bonds, select signals (24), and sense amplifiers.

Table 1 [Effects of the Invention] As described above, according to the present invention, by changing the wire bond, the normal sense amplifier and the sense amplifier for low power supply voltage operation can be switched. This has the advantage that it is possible to provide a semiconductor memory device having both a sense amplifier and one for low power supply voltage operation.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a sense amplifier circuit according to an embodiment of the present invention, FIGS. 2 and 3 are explanatory diagrams showing a wire bond switching method according to an embodiment of the present invention, and FIG. 4 is a circuit diagram of a conventional sense amplifier circuit. FIG. 3 is a circuit diagram of a sense amplifier circuit. In the figure, (3) is a memory cell array, +5),
(l I) (12), (15) (21) are P-channel MO3) transistors, (6) to (10), (+3)
, (16) to (20) are N-channel MOS transistors, (14) is a normal sense amplifier, and (22) is an NA
ND circuit, (23) is a sense amplifier for low power supply voltage operation,
(25) (28) (29) are inverter circuits, (2
6) (27) shows a NOR circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A first sense amplifier whose drain line of a memory cell having an array structure formed on a semiconductor substrate has an optimized operating range at a first potential; and a first sense amplifier whose operating range is optimized at a potential lower than the first potential. A semiconductor memory device characterized in that the semiconductor memory device is connected to a second sense amplifier which is connected to a second sense amplifier, and selects either the first sense amplifier or the second sense amplifier in a wire bonding process.