JP3255662B2 - Output circuit and data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit and a data transfer device used for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a conventional output circuit, a three-state type output circuit (tri-state type output circuit) and an open drain type output circuit are used separately. In the parallel processing system we are currently developing, one-to-one transfer in which data is transferred from a data transfer circuit to one of a plurality of data reception circuits, and a plurality of data reception circuits are used from a data transfer circuit. Broadcast transfer is required to transfer data to all. At the time of data transfer, the data receiving circuit indicates to the data transfer circuit whether or not data can be received by a flag signal (hereinafter, a flag signal) indicating an internal state.
When the output circuit of this flag signal is constituted by a three-state output circuit, the flag signal is connected to the data transfer circuit from each data receiving circuit, and at the time of broadcast transfer, the data transfer circuit takes the logical product of all the flag signals. Determine whether data transfer is possible. On the other hand, in the case of using an open drain type output circuit, the flag signal from each data receiving circuit is wired and used, but a pull-up resistor for raising the signal to a high level and holding the high level is required.

[0003]

As described above, in a conventional data transfer device using a three-state output circuit, the number of flag signals increases as the number of data receiving circuits increases, and the logical product of the flag signals is calculated. The circuit to be taken becomes complicated, and the circuit area becomes very large. In addition, the number of data receiving circuits tends to increase in the future, and the number of signal lines increases, and the problem of an increase in circuit area becomes serious. On the other hand, in a data transfer device using an open drain type output circuit, a pull-up resistor that raises a signal in which a flag signal is wired-connected to a high level and holds the signal at a high level is used. At this time, in order to increase the operating speed, it is desired to reduce the pull-up resistance.However, in terms of power consumption, there is a conflicting demand to increase the pull-up resistance. Has become.

The present invention provides an output circuit that can realize a three-state output circuit and an open drain output circuit with a single circuit. The present invention also provides a data transfer device that can operate at high speed with a reduced number of wires by using this output circuit.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention has first and second control inputs, a data input and a data output, and the first control input normally outputs a data output. Control or open drain output,
The second control input is an output circuit for controlling whether the data output for normal output is to be activated or deactivated.

Further, the present invention provides a data transfer circuit having an input circuit having a pull-up circuit for setting an input signal line to a pull-up state by an output control line, and a plurality of data receiving circuits each having the above-described output circuit. A data line output from the data transfer circuit and the output control line are commonly connected to the plurality of data reception circuits, and an address line output from the data transfer circuit is connected to the plurality of data reception circuits, respectively. Connecting the output of the output circuit to the input signal line of the data transfer circuit in common, and controlling whether the output of the output circuit is a normal output or an open drain type output by the output control line, A data transfer device characterized by controlling whether an output of the output circuit is activated or deactivated by an address line.

[0007]

According to the output circuit of the present invention, a three-state output circuit and an open drain output circuit can be realized by a single circuit.

[0010] As a result, the data transfer device of the present invention can greatly reduce the number of flag signal wirings compared to a data transfer device using a three-state output circuit by the above configuration, and can reduce the logical product of the flag signals. No circuit is required, and high integration of the circuit can be achieved. In addition, since the operation speed can be changed to a three-state output circuit at the time of one-to-one transfer, which occupies most of the data transfer, the operation speed is increased as compared with a data transfer device using an open drain output circuit. Can be achieved. Further, since the pull-up circuit is turned off at the time of one-to-one transfer, lower power consumption can be achieved as compared with a data transfer device using an open drain type output circuit.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an output circuit according to Embodiment 1 of the present invention.

In FIG. 1, 1 is a P-type MOS transistor as a first switching element, 2 is an N-type MOS transistor as a second switching element, 3 to 5 are 2-input NOR circuits, 6 is an inverter circuit, 7 Is a 2-input NA
ND circuit, 8 to 11 are terminals, 19 is a first control circuit, 2
0 is a second control circuit, 21 is a third control circuit, 9
, A control signal OD serving as a first control input, and a second control signal OD.
Control signals EN and 11 which are control inputs of
in is input.

The P-type MOS transistor 1 is connected between the power supply VDD and the terminal 8, and the N-type MOS transistor 2 is connected between the ground terminal VSS and the terminal 8. The gate of the P-type MOS transistor 1 is connected to the output of the NAND circuit 7, and the input of the NAND circuit 7 is connected to the output of the NOR circuit 4 and the node 12, respectively. A node 14 and a signal obtained by inverting the control signal EN by the inverter circuit 6 are input to the inputs of the NOR circuit 4. The gate of the N-type MOS transistor 2 is connected to the output of the NOR circuit 3, and the input of the NOR circuit 3 is connected to the node 12 and the output of the NOR circuit 5, respectively. The inputs of the NOR circuit 5 are connected to nodes 13 and 14, respectively. The nodes 14, 13, and 12 are connected to a terminal 9 (control signal OD), a terminal 10 (control signal EN), and a terminal 11 (data signal Din), respectively.

Next, the operation of this circuit will be described with reference to an operation diagram. FIG. 2 is an operation diagram of the output circuit of FIG.

When the control signal OD is at a high level (hereinafter "H"), the output 15 of the NOR circuit 4 is always at a low level (hereinafter "L"), so that the output 17 of the NAND circuit 7 is always at "H". The P-type MOS transistor 1 is turned off. At this time, the output 16 of the NOR circuit 5 is always "L".
Therefore, "L" is always input to one of the inputs of the NOR circuit 3. Therefore, when the data signal Din is "H", NO
The output 18 of the R circuit 3 becomes "L", the N-type MOS transistor 2 is turned off, and when the data signal Din is "L", N
The output 18 of the OR circuit 3 becomes "H", and the N-type MOS transistor 2 is turned on.

The control signal OD is "L" and the control signal EN
Is "L" , the output 15 of the NOR circuit 4 becomes "L", the output 17 of the NAND circuit 7 becomes "H", and the P-type MOS transistor 1 is turned off. At this time,
Since the output 16 of the NOR circuit 5 becomes “H”, “H” is always input to one of the inputs of the NOR circuit 3. Therefore N
The output 18 of the OR circuit 3 is always "L", and the N-type MOS transistor 2 is turned off.

The control signal OD is "L" and the control signal EN
Is "H" , the output 15 of the NOR circuit 4 becomes "H", so that "H" is always input to one of the inputs of the NAND circuit 7. Therefore, when data signal Din is "H", NA
The output 17 of the ND circuit 7 becomes "L", the P-type MOS transistor 1 is turned on, and when the data signal Din is "L", N
The output 17 of the AND circuit 7 becomes "H", and the P-type MOS transistor 1 is turned off. Also, at this time, the output 16 of the NOR circuit 5 becomes “L”, so that “L” is always input to one of the inputs of the NOR circuit 3. Therefore, the data signal D
When in is "H", the output 18 of the NOR circuit 3 becomes "L" and the N-type MOS transistor 2 is turned off. When the data signal Din is "L", the output 18 of the NOR circuit 3 becomes "H" and N The type MOS transistor 2 is turned on.

As described above, according to the output circuit of the embodiment of the present invention, when the control signal OD input to the terminal 9 is "H", the output circuit is an open drain type output circuit, and when the control signal OD is "L", the three-state type output circuit is used. Becomes In addition, P in the last stage of this embodiment
Since the type and N-type MOS transistors 1 and 2 can be used with high driving capability, they are particularly effective as output pad circuits.

FIG. 3 is a circuit diagram of an output circuit according to a second embodiment of the present invention. In FIG. 3, reference numeral 30 denotes a P-type MOS transistor serving as a first switching element, 31 denotes a P-type MOS transistor, 32 denotes an N-type MOS transistor, 33 denotes an N-type MOS transistor to serve as a second switching element, and 34 and 35 2-input NOR circuit, 36-3
8, 45 are inverter circuits, 50 is a control circuit, 51 is a logic circuit, 41 to 44 are terminals, 41 is a control signal OD serving as a first control input, and 42 is a control signal serving as a second control input. Data signals Din are input to the signals EN and 43, respectively.

The P-type MOS transistors 30 and 31 are connected in series between the power supply VDD and the terminal 44, and the N-type MOS transistors 32 and 33 are connected in series between the ground terminal VSS and the terminal 44. The gate of the P-type MOS transistor 30 is connected to a signal obtained by inverting the output of the NOR circuit 34 by an inverter circuit 38. The inputs of the NOR circuit 34 are connected to a node 40 and a signal obtained by inverting the control signal EN by an inverter circuit 37, respectively. The gate of the N-type MOS transistor 33 is connected to a signal obtained by inverting the output of the NOR circuit 35 by the inverter circuit 36. The input of the NOR circuit 35 is connected to nodes 39 and 40, respectively. P
MOS transistor 31, N-type MOS transistor 3
The two gates are commonly connected to the output of the inverter circuit 45, and the input of the inverter circuit 45 is connected to the terminal 43. Nodes 40 and 39 are connected to terminal 41 (control signal O
D), and terminal 42 (control signal EN).

Next, the operation of this circuit will be described with reference to an operation diagram. FIG. 4 is an operation diagram of this embodiment. P-type MO
The S transistor 31 is turned on when the data signal Din is "H" and turned off when the data signal Din is "L" regardless of the control signal EN and the control signal OD. The N-type MOS transistor 32 is turned off when the data signal Din is "H" and turned on when the data signal Din is "L" regardless of the control signal EN and the control signal OD.

When the control signal OD is "H", the output of the NOR circuit 34 is always "L" and the output 46 of the inverter circuit 38 is always "H", so that the P-type MOS transistor 30 is turned off. At this time, the output of the NOR circuit 35 is always “L”, and the output 47 of the inverter circuit 36 is output.
Is always "H", so that the N-type MOS transistor 33
N.

The control signal OD is "L" and the control signal EN
Is "L" , the output of the NOR circuit 34 is "L" and the output 46 of the inverter circuit 38 is always "H", so that the P-type MOS transistor 30 is turned off. At this time, the output of the NOR circuit 35 becomes "H" and the output 47 of the inverter circuit 36 always becomes "L".
The transistor 33 is turned off.

The control signal OD is "L" and the control signal EN
Is "H" , the output of the NOR circuit 34 is "H" and the output 46 of the inverter circuit 38 is always "L", so that the P-type MOS transistor 30 is turned on. At this time, the output of the NOR circuit 35 becomes "L" and the output 47 of the inverter circuit 36 always becomes "H", so that the N-type MOS transistor 33 is turned on.

As described above, according to the output circuit of the embodiment of the present invention, when the control signal OD input to the terminal 41 is "H", the output circuit is an open drain type output circuit, and when the control signal OD is "L", the three-state type output circuit is obtained. Becomes Therefore, with the output circuit of this embodiment, a three-state output circuit and an open drain output circuit can be realized with a small number of transistors, and the circuit area can be reduced.

FIG. 5 is a configuration diagram of a parallel processing system using the data transfer device of the present invention. Four processor elements (PE) 60-1 to 60-4 are connected by a 4 × 4 crossbar switch network 61-1a to 61-4d. The data transfer device 70 includes the PE 60-1 and the crossbar switch 6
1-1a to 61-1d.

FIG. 6 is a block diagram of the data transfer device of the present invention. The PE 60-1 serving as a data transfer circuit is a CPU 7
1, memory unit 73, control unit 72, and pull-up circuit 74
, And the crossbar switches 61-1a to 61-1d serving as data receiving circuits include a flag signal output circuit 75, a memory unit 76, and a control unit 76.

PE 60-1 and crossbar switch 61-1
a to 61-1d are commonly connected by a data bus 62, an output control line 63 for transmitting a broadcast signal, and an input signal line 64 for transmitting a flag signal.
Are the crossbar switches 61-1a to 61-1 from the PE 60-1.
-1d. The output control line 63 is connected to a pull-up circuit 74 composed of an N-type MOS transistor, and the input signal line 64 is connected to a control unit 72.
75 is an output circuit of the present invention, and the output control line 63 is
, And the address bus 65 is connected to the second control input. The output control line 63 controls whether the output of the flag signal output circuit 75 is a normal output or an open drain type output, and the address bus 65 activates or deactivates the output of the flag signal output circuit 75. Control what to do.

Next, the operation of the data transfer device will be described. When the broadcast signal 63 is “L”,
That is, when performing one-to-one transfer, the pull-up N-type MOS transistor 74 of the PE 60-1 is turned off, the flag signal output circuit 75 is a three-state output circuit, and the crossbar switch 61- Only the flag signal output circuit 75 of 1a is activated, and the flag signal output circuit 75 outputs a signal 66-1 output from the control unit 76 according to the internal state, indicating whether data can be received, as the flag signal 64 to the PE 60-1. . In response to the flag signal 64, the control unit 72 of the PE 60-1
3 issues a data output request. According to this request, the memory unit 7
3 outputs data to the data bus 62, and the crossbar switch 61-1a receives data from the data bus 62.
FIG. 7 shows an operation diagram when the crossbar switch 61-1a is designated.

When the broadcast signal 63 is "H", that is, when the broadcast transfer is performed, P
E60-1 pull-up N-type MOS transistor 74
Is ON, and all crossbar switches 61-1a
The flag signal output circuits 75 to 61-1d are open drain type output circuits. Each crossbar switch 6
In 1-1a to 61-1d, signals 66-1 to 66 output from the control unit 76 in accordance with the internal state and indicating whether or not data can be received.
In response to -4, the flag signal output circuit 75 outputs a high impedance state. All crossbar switches 61-
When the signals 1a to 61-1d are ready to receive data, that is, when the crossbar switches 61-1a to 61-1d have the outputs of the flag signal output circuits 75 of all the data receiving circuits in the high impedance state, the flag signal 64 is output. Is PE6
It is pulled up to “H” by the pull-up N-type MOS transistor 74 of 0-1. In response to this signal, PE60-
The first control unit 72 issues a data output request to the memory unit 73. In response to this request, the memory unit 73 outputs data to the data bus 62, and outputs data to all the crossbar switches 61-1a to 61-1a-6.
1-1d receives data from the data bus 62. FIG.
The operation diagram in this case is shown in FIG.

As described above, according to the data transfer apparatus of the embodiment of the present invention, the flag signals output from the N data receiving circuits connected to the data transfer circuit are wired-connected, so that the three-state output circuit is used. The number of wirings is 1 / N as compared with the conventional data transfer device, and a circuit for obtaining the logical product of the flag signals is not required, so that the circuit can be highly integrated. In addition, the operation speed is three-state output circuit at the time of one-to-one transfer, which occupies most of data transfer. Therefore, the operation speed is higher than that of a data transfer device using an open-drain output circuit in consideration of power consumption. Can be achieved. Since the pull-up circuit is turned off except during the broadcast transfer,
Power consumption can be reduced as compared with a data transfer device using an open drain type output circuit.

[0030]

As is clear from the above embodiments, according to the output circuit of the present invention, when a signal supplied to a specific control input terminal is not possible, a three-state output circuit is obtained, and when the signal is supplied, an open drain type output circuit is obtained. Since it is an output circuit, a three-state output circuit and an open-drain output circuit can be realized by a single circuit. Further, according to the data transfer device of the present invention, the number of flag signal wires of the flag signal can be reduced to 1 / N as compared with a data transfer device using a three-state output circuit.
There is no need for a circuit that takes the logical product of the flag signals, and the circuit can be highly integrated. In addition, the operation speed can be increased and the power consumption can be reduced as compared with the data transfer device using the open drain type output circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an output circuit according to a first embodiment of the present invention.

FIG. 2 is an operation diagram of the output circuit of FIG. 1;

FIG. 3 is a circuit diagram of an output circuit according to a second embodiment of the present invention.

FIG. 4 is an operation diagram of the output circuit of FIG. 3;

FIG. 5 is a configuration diagram of a parallel processing system using the data transfer device of the present invention.

FIG. 6 is a circuit diagram of a data transfer device of the present invention.

FIG. 7 is an operation diagram of the data transfer device of FIG. 6;

8 is an operation diagram of the data transfer device of FIG.

[Description of Signs] 1,30,31 P-type MOS transistor 2,32,33 N-type MOS transistor 8-11,41-44 Terminal 19 First control circuit 20 Second control circuit 21 Third control circuit 50 Control circuit 51 Logic circuit 60-1 to 60-4 PE (processor element) 61-1a to 61-4d Crossbar switch 62 Data bus 63 Output control line 64 Input signal line 65 Address bus 71 CPU 73, 77 Memory unit 72, 76 control unit 74 pull-up circuit 78 input circuit

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-105115 (JP, A) JP-A-2-214220 (JP, A) JP-A-61-274511 (JP, A)

Claims (1)

(57) [Claims] A plurality of output circuits, wherein a data output of each output circuit is commonly connected to a pull-up circuit ;
The pull-up circuit is turned off and one-to-one transfer is performed.
A data transfer device for performing one-to-many transfer by turning on a flip-flop circuit , wherein each output circuit includes: a P-channel transistor having one end connected to a first power supply; the other end of the P-channel transistor; Are connected to form an output, the other terminal of which is connected to a second power supply lower than the first power supply, a first terminal to which an open drain control signal is input, and an enable control signal. A control circuit for controlling the P-channel transistor and the N-channel transistor, the control circuit having a second terminal and a third terminal to which a data signal is input; An output circuit, wherein when the control circuit performs an open-drain output, the P-channel transistor is output only by the open-drain control signal. The register O
When the normal output is performed, even if the FF is used, the P-channel transistor and the N-channel transistor are turned off irrespective of the data signal by switching the enable control signal.
And the open drain control signal pulls up the data output to a high level when the P-channel transistor is turned off in response to the data signal. External pull-up circuit
N. A data transfer device configured to be used as a control signal to perform N.