JP3022695B2 - Bus driver circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus driver circuit, and more particularly to a bus driver circuit comprising a logic integrated circuit.

[0002]

2. Description of the Related Art An example of a conventional bus driver circuit is shown in FIG.
As shown in the figure, different transmission signals D7, D8, D9
And the enable signals EN7, EN8, EN9 are connected to each other, and the outputs of the tristate buffers 52, 53, 54 are connected to form an output OUT3. Two or more of these tristate buffers are configured as an output OUT3. The timing of switching the enable signal is controlled externally (not shown) so as to prevent the bus from being short-circuited so that the outputs of the buses are not simultaneously enabled .

In another conventional example, as shown in FIG. 4, a NOR (NO) having enable signals EN10 and EN11 as inputs is provided.
R) element 58 and enable signals EN10, EN11,
Each of the NOR element 58 receiving the EN12, the NOR element 60 receiving the enable signals EN11 and EN12, the NOR element 61 receiving the enable signals EN10 and EN12, the NOR element 58 and the NOR element 59, respectively. OR (OR) that receives the output and the enable signal EN11 as inputs
The element 62, the NOR element 59, the NOR element 60, the OR element 63 to which each output of the NOR element 61 and the enable signal EN12 are input, and the transmission signal D10 to be input and are controlled by the enable signal EN10. A tri-state buffer 55, a transmission signal D11, an output of the OR element 62 as an enable signal, and an output connected to an output of the tri-state buffer 55, and a transmission signal D12. And a tri-state buffer 57 whose output is used as an enable signal and whose output is connected to the output OUT4 of the tri-state buffer 55.

In this embodiment, when two or more tri-state buffers are simultaneously enabled, the output of the NOR element which receives all of the enable signals corresponding to the enabled tri-state buffers goes high. , OR elements 62, 6 connected to the NOR element
Since the output of 3 is at a high level, only one tri-state buffer is forcibly enabled.
The bus short circuit was prevented.

[0005]

In the conventional bus driver circuit shown in FIG. 3, it is necessary to switch enable signals so that two or more tri-state buffers are not simultaneously enabled, so that there are many buses. When the number of bits is increased, the control of the enable signal becomes complicated, and the design of the enable control circuit requires a great deal of man-hour. Also, when verifying by simulation, it is difficult to set all the practical states, and the bus may be short-circuited due to missing verification.

Therefore, in the conventional bus driver circuit of FIG. 4, the problem of the bus driver circuit of FIG. 3 has been improved by providing the above-described short prevention circuit for all combinations of enable signals that cause a bus short. When the bus becomes multi-bit, the number of combinations of enable signals causing the bus to be short-circuited increases remarkably, and there is a problem that the short-circuit prevention circuit becomes complicated and large-scale.

More specifically, when the bus has two bits, one short prevention circuit is provided for two tristate buffers. However, when the bus has 10 bits, the short prevention circuit is provided for ten tristate buffers. With about 1,000, the role of the short circuit prevention circuit in the bus driver circuit increases.

[0008] An object of the present invention is to solve the above problems,
Even with a large number of bits, the short-circuit prevention circuit does not increase significantly,
Another object of the present invention is to provide a bus driver circuit that reliably eliminates a bus short circuit accident.

The bus driver circuit according to the present invention comprises a source electrode
Is a p-channel MOS field effect connected to the power supply voltage terminal
The transistor and the source electrode are connected to the reference potential terminal.
Connected in series with an n-channel MOS field effect transistor
The output stage with the series connection node as the output terminal
Transmission signal to be output to the controller and externally applied enable
The inverted signal of the signal is input and the output signal is the p-channel.
NA as gate input of MOS field effect transistor
An ND gate circuit, the transmission signal and the enable signal;
And at least an output signal from the n-channel type M
NOR gate as gate input of OS field effect transistor
And the output signal of the NAND gate circuit is inverted.
And a tri-state buffer
A plurality of said NORs of each tri-state buffer
The gate circuit is connected to the above-mentioned inverter of another tri-state buffer.
Data output signals, and the plurality of
The output terminals of the Lystate buffers are commonly connected . Also, the source electrode is connected to the power supply voltage terminal
P-channel type with drain electrode connected to output terminal
The MOS field effect transistor and the drain electrode
First n-channel MOS field effect connected to the input terminal
A transistor and a drain electrode connected to the first n-channel
Connected to the source electrode of a MOS field-effect transistor
A second n-channel in which the source electrode is connected to the reference potential terminal
An output stage comprising a MOS-type MOS field-effect transistor;
Transmission signal to be output to outside and enable given from outside
Input signal and the inverted signal of the
Used as the gate input of a flannel MOS field effect transistor
NAND gate circuit, transmission signal and enable signal
And outputs an output signal to the second n-channel type M
NOR gate as gate input of OS field effect transistor
And the output point is connected to the first n-channel type MOS power supply.
Multiple inputs connected to the gate electrode of a field effect transistor
Tri-state buffer composed of AND gate circuits
And the AN of each tri-state buffer
The above-mentioned NA of another tri-state buffer is added to the D gate circuit.
The output signal of the ND gate circuit is configured to be input.
Connect the output terminals of multiple tri-state buffers in common.
It is characterized by having continued .

[0010]

FIG. 1 is a circuit diagram showing a bus driver circuit according to a first embodiment of the present invention.

In FIG. 1, a bus driver circuit according to this embodiment includes transmission signals D1, D2, D3, and an enable signal EN.
1, EN2, and EN3 are input, and tristate buffers 19, 20, and 21 are provided for obtaining only one output OUT1.

That is, in the present embodiment, an inverter 1 receiving the first enable signal EN1 as an input, a NAND (NAND) element 2 receiving this output and the first transmission signal D1 as inputs, and the NAND element 2 And an P-channel transistor 5 having its output connected to a gate electrode and its source electrode connected to a power supply; One enable signal EN1 and the first transmission signal D1
(NOR) element 3 which receives the input of the second short prevention signal 23 and the third short prevention signal 24, the output of the NOR element 3 is connected to the gate electrode, the source electrode is grounded, and the drain electrode is Is provided with an N-channel transistor 6 having the transmission signal output OUT1 and a second and third tristate buffer 19 having the same configuration as the first tristate buffer 19. Buffers 20 and 21 are provided.

The second tri-state buffer 20
Outputs a short-circuit prevention signal 23 of the first and third tri-state buffers 19 and 21, and outputs a second enable signal EN2, a second transmission signal D2, and the first and third tri-state buffers 19 and 21. Short prevention signal output 2
2, 24 are input, and the output of the transmission signal is connected to the output OUT1 of the transmission signal of the first tri-state buffer 19.

The third tri-state buffer 21 receives a third enable signal EN3, a third transmission signal D3, and short-circuit prevention signal outputs 22, 23 of the first and second tri-state buffers 19, 20. The output of the transmission signal is connected to the output OU1 of the transmission signal of the first tri-state buffer 19, and the short-circuit prevention signal 24 is output.

Next, the operation of the bus driver circuit of this embodiment will be described. When the transmission signal D1 goes high and the enable signal EN1 goes low, the NAND element 2
Is at a low level, the output of the inverter 4 is at a high level, the P-channel transistor 5 is turned on, and the output OU1 of the tri-state buffer 19 is at a high level. At this time, if the NAND element 8 is at a low level, the P-channel transistor 11 is turned on and the output of the tri-state buffer 20 is at a high level, so that the bus does not enter a short-circuit state. If the NAND element 8 is at a high level, the P-channel transistor 11
Is turned off, the NOR element 9 becomes low level, and N
Since the channel transistor 12 is turned off, the output of the tri-state buffer 20 becomes high impedance, and the bus does not become short-circuited.

Similarly, when the NAND element 14 is at a low level, the output of the tristate buffer 21 is at a high level, and when the NAND element 14 is at a high level, the output of the tristate buffer 21 is at a high impedance. The bus does not go into a short state.

With this operation, when the output of an arbitrary tri-state buffer is at a high level, the output of another tri-state buffer is at a high level or a high impedance, so that a short circuit of the bus can be prevented. Further, a bus driver circuit can be constituted by only the number of tri-state buffers corresponding to the number of bits of the bus.

FIG. 2 is a circuit diagram showing a bus driver circuit according to a second embodiment of the present invention.

In FIG. 2, the bus driver circuit of this embodiment has an N-channel transistor 30 connected in series between the N-channel transistor 31 and the P-channel transistor 29 at the output stage of the tri-state buffer 46 for short-circuit prevention control. The N-channel transistor 30 is controlled by the output of the AND element 28 which receives the short prevention signals 50 and 51 of the second and third tri-state buffers 47 and 48 directly.

The first tri-state buffer 46 has an inverter 25 receiving the enable signal EN4 as an input, and a NA receiving the transmission signal D4 and the output of the inverter 25 as inputs.
It has an ND element 26, an AND element 28, a P-channel transistor 29, and N-channel transistors 30 and 31. A short prevention signal 49 is obtained from the output of the NAND element 26. Second and third tri-state buffers 4
7 and 48 have the same configuration as the first tri-state buffer 46. With the configuration of this embodiment, the same effects as those of the first embodiment can be obtained.

[0021]

As described above, according to the present invention, the bus is not short-circuited even when two or more tri-state buffers are simultaneously enabled, so that the enable control circuit can be easily designed and verified. This has the effect that the short circuit of the bus due to leakage can be completely prevented.

In addition, the present invention eliminates the need to provide a separate short-circuit prevention circuit, particularly when the tri-state buffer has a short-circuit prevention function, so that the bus driver circuit can be constituted by only a tri-state buffer corresponding to the number of bits of the bus. Since the configuration is possible, there is an effect that the circuit scale for one bit does not increase even if the bus has many bits.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a bus driver circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of the related art.

FIG. 4 is a circuit diagram showing another example of the related art.

[Explanation of symbols]

1,4,7,10,13,16,25,32,39
Inverter 2,8,14,26,33,40 NAND (NAN
D) Element 3, 9, 15, 27, 34, 41, 58, 59, 60,
61 NOR element (NOR) element 5, 11, 17, 29, 36, 43 P-channel transistor 6, 12, 18, 30, 31, 37, 38, 44, 45
N-channel transistors 19, 20, 21, 46, 47, 48, 52, 53, 5
4, 55, 56, 57 Tristate buffer 22, 23, 24, 49, 50, 51 Short prevention signal 28, 35, 42 AND (AND) element 62, 63 OR (OR) element

Claims (2)

(57) [Claims] 1. A source electrode is connected to a power supply voltage terminal.
P-channel type MOS field effect transistor and source electrode
Is connected to the reference potential terminal, the n-channel MOS field effect
Connected in series with the output transistor and outputs a connection node in series
The output stage as a terminal, the transmission signal to be output to the outside, and the external
And the inverted signal of the enable signal given from
An output signal is supplied to the p-channel MOS field effect transistor.
A NAND gate circuit as a gate input of the
At least a signal and the enable signal
A signal of the n-channel MOS field-effect transistor
A NOR gate circuit serving as a gate input;
And an inverter that inverts the output signal of the gate circuit.
A plurality of tri-state buffers, the NOR gate circuit of each tri-state buffer
The output of the inverter of another tri-state buffer
A plurality of tri-states.
A bus driver circuit , wherein output terminals of a buffer are commonly connected . A source electrode connected to the power supply voltage terminal;
P-channel MOS with rain electrode connected to output terminal
A field effect transistor and a drain electrode connected to the output terminal
N-channel MOS field-effect transistor connected to
A transistor and a drain electrode are formed of the first n-channel type MO.
Source connected to source electrode of S field effect transistor
The second n-channel type M whose electrode is connected to the reference potential terminal
Output stage consisting of OS field effect transistor and external
Transmission signal to be output and enable signal given externally
And the output signal is the p-channel type
NAN as gate input of MOS field effect transistor
D gate circuit, the transmission signal and the enable signal
And outputs the output signal to the second n-channel MOS
NOR gate times as gate inputs of field effect transistors
And the output point is the first n-channel MOS field effect.
Multiple input AN connected to the gate electrode of the transistor
Multiple tri-state buffers consisting of D gate circuits
And the AND gate circuit of each tri-state buffer
The NAND gate circuit of another tri-state buffer.
A plurality of traffic signals.
A bus driver circuit , wherein output terminals of an state buffer are commonly connected .