JPH04305960A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to optimize the functions of LSIs in conformity with their uses more elaborately and more easily without damaging the advantages of LSI development and manufacturing costs. CONSTITUTION:These are included a cell which serves as a core and a redundant number of macro cells from 9 to 11 which fail to operate simultaneously in one LSI 1. These macro cells 9 to 11 with the core cell 2 are connected with a common bus signal line 3 in the LSI. Furthermore, there are provided circuit means (6-1 to 6-5) which select and connect a desired cell alone with the common bus signal line 3 in conformity with the use of the LSI out of the macro cells and cut off other macro cells which are unnecessary from the common bus signal line 3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the construction of semiconductor integrated circuits, and more particularly to a semiconductor device for realizing a design method and a manufacturing method for an LSI including a plurality of macro cells.

0002

2. Description of the Related Art An example of a conventional system LSI system is shown in FIG. 4 and will be described. This figure 4 is published in Japanese Patent Application Laid-Open No. 62-24136.
This is a system LSI system shown in Publication No. 5, in which 1 is an LSI, 21, 22, 23 are independent first, second, and third circuits, 31, 32, and 32 are selector circuits, T0, T1 and TN are the first, second and third respectively.
The LSI input/output terminals TS0 and TS1 connected to the circuits 21, 22 and 23 are selector circuits 31 and 32, respectively.
, 33 circuit selection terminals.

[0003] Next, the operation will be explained. First, when the circuit selection terminals TS0 and TS1 are set to "00",
The input/output terminals T0, T1, and TN are connected to the first circuit 21, and the LSI 1 is an LS that has the function of the first circuit 21.
Becomes I. Next, the circuit selection terminals TS0 and TS1 are set to “
01”, input/output terminals T0, T1, T
N is connected to the second circuit 22, and the LSI 1
This is an LSI having the functions of the circuit 22. Further, when the circuit connection terminals TS0, TS1 are set to "10", the input/output terminals T0, T1, TN are connected to the third circuit 2.
3, and the LSI 1 becomes an LSI having the function of this third circuit 23. In this way, multiple independent circuits are built into one LSI, a selector circuit is provided between this circuit and the input/output pin of the LSI, and this selector circuit connects the input/output pin to one of the multiple built-in circuits. As a result, one type of LSI can be used as an LSI with multiple circuit functions, so the number of LSIs produced of the same type can be increased while reducing the number of types of LSIs.

0004

[Problem to be Solved by the Invention] In the conventional system LSI system described above, although one LSI has a plurality of independent circuits, only one of them can be used depending on the purpose. The problem was that it was structurally impossible to use these circuits in combination. Although increasing the production quantity of the same type of LSI is advantageous in terms of development and manufacturing costs, there is also a demand for finely optimizing the functions of the LSI for each use. exist. The above selection method has a problem in that it has not been able to satisfactorily solve the latter requirement. Furthermore, since the above method is configured to select the desired circuit from outside the LSI, it requires a selector circuit, a circuit selection terminal, etc., and is disadvantageous in terms of cost such as chip area and mounting package. There was an issue.

[0005] The present invention was made to solve this problem, and it is possible to more precisely and easily optimize functions according to the application without sacrificing the advantages of LSI development and manufacturing costs. The purpose is to obtain a semiconductor device that can perform

[0006]

[Means for Solving the Problems] A semiconductor device according to the present invention includes one or more circuits that are incorporated into an LSI and must operate, a circuit group consisting of a plurality of circuits that cannot operate simultaneously, the one or more circuits and the above circuits. A device that is provided between a signal line commonly connected to the circuit group and a signal line common to each of the circuit groups, and selectively disables the operation of each circuit forming the circuit group. According to the selection of the circuit means, appropriate circuit groups are connected to a common signal line, and the LSI is configured to perform different operations.

[0007]

[Operation] In the present invention, there is only one LSI as the base, and development and manufacturing only need to be performed for this LSI. On the other hand, since it includes a plurality of macro cells as options, by selecting only desired macro cells from these macro cells, it is possible to finely and easily optimize the functions according to the application of the LSI.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing an embodiment of a semiconductor device according to the present invention. In this Figure 1, 1 is an LSI
, 2 is a core cell, 3 is a bus signal line connected to this core cell 2, 4 and 5 are macro cell groups, 6-1, 6-2, 6-
3, 6-4, and 6-5 are macrocell selection circuits connected to the bus signal line 3, 7 and 8 are macrocells built into the macrocell group 4, and 9, 10, and 11 are macrocells built into the macrocell group 6. be. And macro cells 7 and 8 are LS
Macro cells 9 to 11 constitute one or more circuits that are incorporated into I1 and must operate, and macro cells 9 to 11 constitute a circuit group from a plurality of circuits that cannot operate at the same time. Bus signal line 3 is the above 1
The macrocell selection circuits 6-1 to 6-5 are signal lines to which at least one circuit and the circuit group are commonly connected, and the macrocell selection circuits 6-1 to 6-5 are provided between each of the circuit groups and the common signal line to the circuit group. A circuit means is configured to selectively disable the operation of each circuit forming the circuit. According to the selection of this circuit means, appropriate circuit groups are connected to the common signal line, and the LSI 1 is configured to perform different operations.

FIGS. 2 and 3 are block diagrams showing specific examples of macro cell selection circuits 6-1 to 6-5 shown in FIG. 1. 2 and 3, the same reference numerals as in FIG. 1 indicate corresponding parts, 12-1, 12-2, 12-3, 12
-4, 12-5 are flip-flops forming a register, 13 are each of these flip-flops 12-1 to 12-5
clock signals for driving 14-1, 14-2,
14-3, 14-4, 14-5 are N-channel transistor elements, 15-1, 15-2, 15-3, 15-4, 1
5-5 is a fuse element, 16-1, 16-2, 16-3
, 16-4, 16-5 are high resistance elements, and these high resistance elements 16-1 to 16-5 are fuse elements 15-1 to 15-5.
are connected in series with each other, and this fuse element 15-1
~15-5 and the high resistance elements 16-1 to 16-5 are connected to N-channel transistor elements 14-1 to 14, respectively.
-5 are connected to each gate.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIGS. 2 and 3. First, the core cell 2 corresponds to, for example, an MPU, and is a cell that implements the parts that are basically required for the functions of the entire semiconductor device according to the present invention. On the other hand, the macro cell groups 4 and 5 realize functions that assist the core cell 2, and can assume a DMA function, an interface function, and many other functions. It is assumed that these macrocell groups 4 and 5 are connected to the core cell 2 by a bus signal line 3 and operate while communicating with each other. By the way, the functions of the macro cell that should assist the functions of the core cell 2 are considered to vary depending on the use of this LSI. Therefore, the macro cells 7 and 8 included in the macro cell group 4 have different functions, and are configured so that one can be selected depending on the desired LSI function. Similarly, it is assumed that one of the macro cells 9, 10, and 11 included in the macro cell group 5 can be selected. Any macro cell in the macro cell group 4 and any macro cell in the macro cell group 5 can operate on the core cell 2 at the same time.

Now, it is assumed that a desired LSI function can be realized by a combination of core cell 2, macro cell 7, and macro cell 10. Therefore, macrocells 8, 9, 1
Since the function No. 1 is no longer necessary, the macro cell selection circuit 6 is used to disconnect these from the bus signal line 3. The specific configuration and operation of this macro cell selection circuit 6 will be described later. According to the above description, the functional configuration of the LSI 1 is such that the core cell 2, the macro cell 7, and the macro cell 10 are connected by the bus signal line 3. Although other macro cells exist on the LSI, they do not contribute to the functions.

Next, in the case of FIG. 2, as shown in FIG.
2 constitutes a register, and the output signal of each bit of this register is connected to the gate terminal of the N-channel transistor element 14. As described above, in order to obtain an LSI with a configuration in which the core cell 2 and macro cells 7 and 10 are interconnected by the bus signal line 3, the clock signal 13 is used to control the five flip-flops forming the register. Pu 12-1, 12-2, 12-3, 12-4, 12-
Write "1, 0, 0, 1, 0" in 5 from the left in order. Here, the output signals of the respective flip-flops 12-1 to 12-5 are transmitted to five N-channel transistors 14-1 and 14-1.
This N-channel transistor 14 is connected to the gate terminals of 4-2, 14-3, 14-4, and 14-5.
-1, 14-2, 14-3, 14-4, and 14-5 are in the [ON, OFF, OFF, ON, OFF] state in order from the left side. Therefore, core cell 2 is connected to bus signal line 3.
and macro cells 7, 10 are connected, and macro cells 8, 9,
This means that an LSI with 10 parts separated is constructed.

Note that the elements constituting the register need not be limited to flip-flops, and the same operation can of course be obtained even if they are replaced with nonvolatile memory elements. In any case, there may be various combinations of core cells and macro cells to obtain the desired LSI configuration, but the combination is set based on the LSI described above.
This is a simple task on the part of the SI user, and L
There is only one manufacturing process for SI.

On the other hand, in the case of FIG. 3, fuse elements 15-1 and 15-2 connected to the power supply as shown in FIG.
, 15-3, 15-4, 15-5 and high resistance elements 16-1, 16-2, 16-3, 16-4 connected to the ground.
, 16-5, and these fuse elements 15-1 to 15
-5 The other ends of the crossing resistance elements 16-1 to 16-5 are commonly connected to N.
Channel transistor elements 14-1, 14-2, 14-
3, 14-4, and 14-5, respectively. As described above, in order to obtain an LSI having a structure in which the core cell 2 and the macro cells 7 and 10 are interconnected by the bus signal line 3, the fuse element 15 is cut using thermal melting by laser beam irradiation or the like in the manufacturing process. -1,15-
2, 15-3, 15-4, 15-5 from the left side
, 0, 0, 1, 0''. (here "0"
represents the blown state of the fuse element, and "1" represents the unbroken state), and each fuse element 1
5 and the high resistance element 16 are connected to the gate terminals of the five N channel transistors 14-1 to 14-5.
14-2, 14-3, 14-4, and 14-5 are in the [ON, OFF, OFF, ON, OFF] state in order from the left side. Therefore, an LSI is constructed in which the core cell 2 and macro cells 7, 10 are connected to the bus signal line 3, and the macro cells 8, 9, 11 are separated.

[0015] In the above embodiment, the case where a fuse element is provided has been explained as an example, but in particular, the fuse element 1 is
It goes without saying that even if 5 is not provided, the same operation can be obtained by connecting directly to the power supply using only the wiring material and disconnecting or not disconnecting the wiring material. In any case, in this case, the combination of core cells and macrocells to obtain the desired LSI configuration depends on whether or not each fuse element or wiring material is cut, so the LSI manufacturing side It will be necessary to separate the two. However, most of the LSI manufacturing processes can be standardized, and only the thermal blowing of fuses using laser light or the like in the final process is required for each LSI, so the increase in manufacturing costs is kept to a minimum. It can be suppressed.

[0016]

[Effects of the Invention] As explained above, in the semiconductor device of the present invention, a core cell aiming at a basic function and a redundant number of macrocell groups with different supporting functions are prepared in one LSI. There is. These macro cells are connected to the core cell via a common bus signal line within the LSI, and only desired macro cells from among the macro cells can be selectively connected to the bus signal line according to the application of the LSI. ,
It is equipped with a means for disconnecting unnecessary items from the common signal line, and includes macro cells as selection branches, so by selectively operating only desired ones from these macro cells, it can be adjusted according to the application. This has the advantage that the functions of the LSI can be finely and easily optimized. On the other hand, there is only one LSI as the base, and development and manufacturing only need to be done for this LSI. From the above, this invention has advantages in terms of costs such as development, manufacturing, equipment, and production management by mass producing a single LSI, and flexibly optimizes the functions of the LSI according to the application. It has the effect of being able to do things and having advantages.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a configuration diagram showing a specific example of the macro cell selection circuit shown in FIG. 1;

FIG. 3 is a configuration diagram showing another specific example of the macro cell selection circuit shown in FIG. 1;

FIG. 4 is a configuration diagram showing an example of a conventional system LSI system.

[Explanation of symbols]

1 LSI 2 Core cell 3 Bus signal line 4, 5 Macro cell group 6 Macro cell selection circuit 7-11 Macro cell

Claims (1)

[Claims] 1. A circuit group consisting of one or more circuits that are incorporated into an LSI and must operate, a plurality of circuits that cannot operate simultaneously, and a signal line to which the one or more circuits and the circuit group are commonly connected. and a circuit means provided between each of the circuit groups and a common signal line to selectively disable the operation of each circuit forming the circuit group,
A semiconductor device characterized in that a suitable circuit group is connected to a common signal line according to the selection of the circuit means, and the LSI is configured to perform different operations.