JPH071492B2 - Memory device malfunction detection method - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a malfunction detection method for a storage device in an information processing apparatus, and more particularly to a malfunction detection method for accessing a plurality of storage devices.

[Prior art]

Conventionally, when accessing a storage device of this type, as a method of detecting a malfunction of the storage device, there is a method of recognizing the malfunction of the storage device by receiving an error response signal from the storage device. Generally adopted. However, with this method, when a malfunction is detected in the storage device, the malfunction of the storage device can be recognized, but no malfunction is detected in the storage device and no response signal is returned from the storage device. Or, if a response signal is returned illegally, it will be detected as a malfunction of the device on the accessing side. Therefore, there is a maintenance defect that it takes a lot of time until it is determined that the storage device is malfunctioning.

[Object of the Invention]

An object of the present invention is to set a storage device access time as a fixed time, generate a check bit of a Hamming code from an access request signal sent to the storage device, and hold the check bit until a response signal is returned from the storage device. Then, by checking the presence or absence of an illegal response signal by collating the held bit with the response signal, it is possible to determine which memory device the response signal is from when the illegal response signal is present. Another object of the present invention is to provide a malfunction detection method for a storage device.

[Structure of Invention]

A malfunction detection method for a storage device according to the present invention is such that access information is sent to a plurality of storage devices accessed at the same preset access time and each of the plurality of storage devices, and after the access time elapses. An arithmetic processing unit that receives response information corresponding to the access information from each of the plurality of storage devices, a unit that supplies an access time of the storage unit, and the processing unit sends the access time to the plurality of storage devices. Means for degenerating the request signal included in the access information into an inspection code, means for retaining the degenerated inspection code for a period determined by the access time, and transmission from the retaining means after the access time elapses. It corresponds to the access information output from each of the plurality of storage devices based on the inspection code obtained. And a error detection means for checking the response signal included in the response information.

Example of Invention

Next, a malfunction detection method according to the present invention will be described in detail with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, the arithmetic processing unit 1 sends access information to the storage units 2-1 to 2-16 via the access paths 101-1 to 101-16. The access information includes a request signal, operation instruction signal, address, and write data. The storage devices 2-1 to 2-16
All complete their operations in the same access time. Therefore, when these storage devices receive an access request, they send response information to the arithmetic processing unit 1 via the access paths 102-1 to 102-16 after the access time. The response information includes a response signal, an operation signal, and read data. The ECG circuit 3 has access paths 101-1 to 101-16.
When a request signal is supplied to each of the request signals via, the check bits of the Hamming code for the request signal are generated. The generated check bit is supplied to the memory circuit 4 via the connection 103. The memory circuit 4 is a circuit for storing the check bit supplied by the connection 103, and its write address is supplied by the connection 107 and its read address is supplied by the connection 109. The read data is supplied to the error detection circuit 5 via the connection 104.

The error detection circuit 5 includes access paths 102-1 to 102.
The response signal in -16 and the check bit stored in the memory circuit 4 are supplied by the connection 104. Here, an incorrect response signal is detected, and an error signal corresponding to the storage device that has sent the incorrect response signal is output to the flip-flops 11-1 to 11-16 by the connections 110-1 to 110-16.
Is supplied to. Flip-flops 11-1 to 11-16
Serves as an error flag which holds the error signal provided by connections 110-1 through 110-16.

The register 6 is a register for holding the access time of the storage devices 2-1 to 2-16, the value of which is set only by a shift path (not shown) and is supplied to the conversion circuit 7 by the connection 105. The conversion circuit 7 is realized by adding "1" in the present embodiment, and is supplied to the subtraction circuit 10 through the connection 106. The address register 8 is a register that holds the write address of the memory circuit 4, and the output of the adder circuit 9 is supplied by the connection 108, and the adder circuit 9, by the connection 107.
The output is supplied to the subtraction circuit 10 and the storage circuit 4. The adder circuit 9 is a circuit for adding the write address “1” of the memory circuit 44 supplied from the address register 8 via the connection 107, and is supplied to the address register 8 via the connection 108.
The subtraction circuit 10 is a circuit that generates the read address of the storage circuit 4 by subtracting the access time information supplied by the connection line 106 from the write address of the storage circuit 4 supplied by the connection line 107, and the output thereof is stored by the connection line 109. It is supplied to the circuit 4. As the access time information in this embodiment, the value obtained by adding "1" to the access time held in the register 6 by the conversion circuit 7 is supplied. “1” in time
It can also be realized by holding the value to which is added. In that case, the conversion circuit 7 can be omitted.

The operation of the embodiment thus configured will be described below with reference to the time chart of FIG. In this example, the access time of the storage devices 2-1 to 2-16 is 20 clock cycles. Therefore, register 6 has a value
20 is held, 1 is added by the conversion circuit 7, and the value 21 is supplied to the subtraction circuit 10 by the connection 106. A value is set in the register 6 by the shift path, and the set value is held thereafter.
Is always supplied with the value 21. Address register 8
Access timing A from the arithmetic processing unit 1 to the storage units 2-1, 2-2 and 2-3 at the timing a when the value of 0 is 0.
If there is, access paths 101-1 to 101-16
Request signals are 1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0 in order. The 16-bit request signal is input, and the ECG circuit 3 generates a check bit of the Hamming code. The generating method is, as shown in FIG. 3, generated by the exclusive OR circuits 21-1 to 21-6 by the combination of request signals input from the request signal lines 201-1 to 201-16. Request signal lines 201-1 to 201-16 are 101- in FIG.
1 to 101-16. As shown in the above example, when 1 is input to 201-1 to 201-3 of this request signal, 103-1 to 1,103-2 to 103-6 to 0 are input.
Is output as a check bit. The output check bit is stored in the address of the memory circuit 4 indicated by the value held in the address register 8, that is, the address 0.

The response corresponding to the access request A is stored in the storage device 2-
After 1 to 2-16 receive this access request A, 20
After the clock cycle, that is, at the timing b after 21 clock cycles from the timing a, the storage device 2-
It is sent to the arithmetic processing unit 1 from 1 to 2-16. Since the generation of the timing b is 21 clock cycles after the timing a, the value of the address register 8 is 21 by adding 1 every clock. Therefore, the read address of the storage circuit 4 is converted from the value 21 held in the address register 8 by the subtraction circuit 10 into the conversion circuit 7.
The output value of 21 is reduced to 0, and the content stored at address 0, that is, the check bit of the request signal of the access request A is read and supplied to the error detection circuit 5.
On the other hand, the response signal sent from the storage devices 2-1 to 2-16 at the timing b is also supplied to the error detection circuit 5.
The error detection circuit 5 is configured as shown in FIG. 4, and the response signal in the access paths 102-1 to 102-16 is 16 bits from the storage circuit 4 by the signal lines 301-1 to 301-16. 6 check bits are provided by connections 104-1 to 104-6. The exclusive OR (31-1 to 31-6) is taken by the combination of the response signal and the check bit, and 6 bits are generated in the syndromes 303-1 to 303-6. By decoding the generated syndrome with the decoding circuit 32 as shown in FIG.
110-1 to 110-16 can be detected.

Now, suppose that at the above timing b, 301-
3 is “0”, that is, 301-1 to 301-16 are 1,1,0,0,0,
If there is a response such as 0,0,0,0,0,0,0,0,0,0,0, syndromes 303-1 to 303-6 are 1,0,1,1,0,0
Becomes Therefore, it can be seen from FIG. 5 that 301-3 is invalid, and as a result, the output 110-
3 becomes "1", and the error flag 11-3 is set to "1". Also, for example, at timing b, 30 of the response signals
It is assumed that 1-4 becomes "1" and there is a response. That is, 30
1-1 to 301-16 is 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,
If it is 0, the above syndromes 303-1 to 30-30
3-6 becomes 1,0,1,0,1,0, and 301-
4 is illegal, 110-4 becomes "1" and "1" is set in the error flag 11-4.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, the check bit of the Hamming code generated from the request signal to the storage device is held until the timing at which the response signal is returned from the storage device, and the holding information and the response signal By configuring so that an unauthorized response signal can be detected from, the malfunction of the storage device can be detected promptly with a small amount of hardware, and the effect obtained to improve the reliability of the information setting system is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention,
FIG. 2 is a time chart for explaining the operation of the embodiment of FIG. 1, FIG. 3 is a circuit diagram showing a concrete configuration example of the ECG circuit in the embodiment of FIG. 1, and FIG. FIG. 5 is a circuit diagram showing a concrete configuration example of the error detection circuit in the embodiment of FIG. 1, and FIG. 5 is a diagram showing a state of an illegal response signal which is interrupted in the error detection circuit of FIG. In the figure, 1 is an arithmetic processing unit, 2-1 to 2-16 and 4 are storage devices, 3 is an ECG circuit, 5 is an error detection circuit, 6 is a register, 7 is a conversion circuit, 8 is an address register, and 9 is an addition. Circuit, 10 is a subtraction circuit, 11-1 to 11-16 are error flags, 21-1 to 21-6, 31-
Reference numerals 1 to 31-6 are exclusive OR circuits, and 32 is a decoding circuit.

Claims (1)

[Claims] 1. A plurality of storage devices accessed at the same preset access time, and access information is sent to each of the plurality of storage devices, and after the access time elapses, the plurality of storage devices are accessed. An arithmetic processing unit that receives response information corresponding to the access information from each, a unit that supplies the access time of the storage unit, and a unit that is included in the access information sent from the arithmetic processing unit to the plurality of storage units. Means for degenerating the request signal to the inspection code, means for holding the degenerated inspection code for a period determined by the access time, and the inspection code sent from the holding means after the access time elapses. Is included in the response information corresponding to the access information output from each of the plurality of storage devices based on Malfunction detection method of a storage device characterized by comprising an error detecting means for checking the answer signal.