JPS61163450A - System for detecting malfunction of storage device - Google Patents

Abstract

PURPOSE:To detect malfunction of a storage device with less hardware quantity by storing a check bit of a humming code generated from a request signal to a storage device and using the storage information and a response signal to detect an incorrect response signal. CONSTITUTION:When an access request signal is fed to an ECG circuit 3, the circuit 3 generates a check bit of the humming code to the request signal, the result is fed to a storage circuit 4 through a connection 103 and a write address is fed and stored through a connection 107 and a read address is through a connection 109. The read data is fed to an error detection circuit 5 through the connection 104. A response signal in access paths 102-1-102-16 and the check bit from the connection 104 are fed to the circuit 5 and the incorrect response signal is detected. An error signal corresponding to the storage device transmitting the incorrect response signal is fed to FFs 11-1-11-16 through connections 110-1-110-16 and used as an error flag storing the error signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a malfunction detection method for a storage device in an information processing apparatus, and particularly to a malfunction detection method when accessing a plurality of storage devices.

[Prior art]

Conventionally, when accessing this type of storage device, the method for detecting malfunction of the storage device is as follows.

A commonly used method is to recognize a malfunction of a storage device by receiving an error response signal from the storage device. But with this method.

If a malfunction is detected within the storage device, the malfunction of the storage device can be recognized, but if the malfunction is not detected within the storage device and no response signal is returned from the storage device, or if the storage device has not returned a response signal, If a response signal is returned, it will be detected as a malfunction of the accessed device. As a result, there was a maintenance defect in that it took a long time to determine that the storage device was malfunctioning.

[Purpose of the invention]

An object of the present invention is to set the access time of a storage device to a fixed time, and to generate a check bit of a code from an access request signal sent to the storage device.

The check bit is held until a response signal is returned from the storage device, and the presence or absence of a false response signal is checked by comparing the held bit with the response signal. Another object of the present invention is to provide a storage device malfunction detection method that can determine which storage device the response signal is from.

[Structure of the invention]

The storage device malfunction detection method according to the present invention includes a plurality of storage devices that are accessed at a constant and the same access time;
In a storage device applied to an information processing system consisting of a device that accesses the storage device,
means for supplying the access time of the storage device; means for degenerating the access device into a sound code; means for holding the degenerated test code for a period determined by the access time; The present invention is characterized by comprising a response information inspection means for checking response information sent from each of the storage devices to the access device using a held inspection code.

[Embodiments of the invention]

Next, two malfunction detection methods according to the present invention will be described in detail with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, an arithmetic processing device 1 sends access information to storage devices 2-1 to 2-16 via access paths 101-1 to 101-16. Request signal for access information.

Contains operation instruction signals, addresses, and write data. All of the storage devices 2-1 to 2-16 complete their operations in the same access time. therefore.

When these storage devices receive an access request.

Access paths 102-1 to 102-1 after the access time
2-16, the response information is sent to the arithmetic processing device 1. Response information includes response signals and operation signals.

Contains read data. When the ECG circuit 3 is supplied with a request signal via the access paths 101-1 to 101-16, it generates a Hamming code check bit for the request signal. The generated test bits are supplied to the storage circuit 4 via a connection 103. The memory circuit 4 is a circuit that stores the test bits supplied through the connection 103, and its write address is determined through the connection 107.
A read address is also provided by connection 109. The read data is sent to the error detection circuit 5 through the connection 104.
supplied to

The error detection circuit 5 is supplied with the respective response signals in the access paths 102-1 to 102-16 and the check bits stored in the storage circuit 4 via a connection 104. Here, an invalid response signal is detected, and an error signal corresponding to the storage device that sent the invalid response signal is sent to connection 1.
10-1 to 110-16 to flip a tube 1
1-1 to 1t-tj. Flip-flops 11-1 to 11-16 serve as error flags that hold error signals supplied by connections 110-1 to 110-16.

The register 6 is a register that holds the access time of the storage devices 2-1 to 2-16, and its value is set only by a shift (not shown).

It is supplied to the conversion circuit 7 via connection 105. Conversion circuit 7
is realized by adding ``1'' in this embodiment, and is supplied to the subtraction circuit 10 through a connection 106.The address register 8 is a register that holds the write address of the memory circuit 4, and is supplied to the subtraction circuit 10 through a connection 108. The output is supplied to the adder circuit 9, the subtracter circuit 10, and the memory circuit 4 through a connection 107.The adder circuit 9 receives the write address "1" of the memory circuit 4, which is supplied from the address register 8 through a connection 107. This is a circuit that adds

The address register 8 is supplied through a connection 108. The subtraction circuit 10 is connected to the storage circuit 4 supplied by the connection 107.
This circuit generates the read address of the memory circuit 4 by subtracting the access time information supplied by the connection 106 from the write address of the memory circuit 4, and its output is supplied to the memory circuit 4 by the connection 109. Note that the access time information in this embodiment is as follows.

The conversion circuit 7 converts the access time held in the register 6 into
However, the value added by '1' is supplied.

This access time information can also be supplied by holding a value obtained by adding 1'' to the access time in a register. In that case, the conversion circuit 7 can be omitted.

Regarding the operation of the embodiment configured in this way.

This will be explained below with reference to the time chart of FIG. In this example, the access time for the storage devices 2-1 to 2-16 is 20 clock cycles.

Therefore, the value 20 is held in register 6.

1 is added by the conversion circuit 7 and the value 21 is supplied to the subtraction circuit 10 via a connection 106. Shift /J? in register 6? A value is set by the subtractor circuit 10 from connection 106 in order to hold the set value thereafter.
is always supplied with the value 21. Assuming that there is an access request A from the arithmetic processing unit 1 to the storage devices 2-1, 2-2 and 2-3 at timing a when the value of the address register 8 is O, access time blocks 101-1 to 101- The 16 request signals are 1.1, 1, 0, 0,
0,0.0,0,0°o, o, o, o, o, o.

With this 16-bit request signal as input, ECG circuit 3
The check bits of the Noming code are generated at . The generation method is as shown in FIG.
-1 to 201-16 are generated by the exclusive OR circuits 21-1 to 21-6. Note that the request signal lines 201-1 to 201-16
is a part of 101-1 to 101-16 in FIG. As shown in the example above, two of these request signals
When 1 is input to 01-1 to 201-3.

103-1 to 1.103-2 to 103-6 to 0
is output as a check bit. The output check bit is stored at the address of the storage circuit 4 indicated by the value held in the address register 8, that is, at address 0.

The response corresponding to the above access requester is the storage device 2-
After 1 to 2-16 receive this access request A,
After 20 clock cycles, i.e. 2 from timing a
At timing b one clock cycle later, the data is sent from the storage devices 2-1 to 2-16 to the arithmetic processing unit 1. The occurrence of this timing b is 2 of timing a.
Since it is one clock cycle later, address register 8
The value of 1 is added to each tarok, making it 21.

Therefore, the read address 21 of the memory circuit 4 is subtracted to 0, and the content stored at address 0, that is, the check bit of the request signal of the access requester is read out and supplied to the error detection circuit 5. On the other hand, response signals sent from the storage devices 2-1 to 2-16 at timing b are also supplied to the error detection circuit 5. The error detection circuit 5 is configured as shown in FIG.
The response signal from 02-1 to 102-16 is sent to signal line 3.
16 bits are connected by 01-1 to 301-16, and the check bits from memory circuit 4 are connected to connections 104-1 to 104-.
Robit is supplied by 6. Exclusive OR (31-1 to 3l-
6) is taken and syndromes 303-1 to 303-
6 generates 6 bits. By decoding the generated syndrome by the decoding circuit 32 as shown in FIG. 5, false response signals 110-1 to 110-16 can be detected.

Now, suppose that 301 of the response signals at timing b above
-3 is 0#, i.e. 301-1 to 301-16
is 1,1,0,0,0,0,0,0,0,0,0,0,
If there is a response like 0°0.0.0, syndromes 303-1 to 303-6 will be 1,0,1,1,
It becomes 0.0. Therefore, it can be seen from FIG.
'1' is set to '1'. Also, for example, at timing b
Suppose that 301-4 of the response signals becomes '1'' and there is no response. That is, 301-1 to 301-16
is 1.1,1,1,0,0,0,0,0,0,0゜o,
If o, o, o, o, then the above syndrome 3
03-1 to 303-6 become 1.0, 1, 0, 1.0, and according to FIG.
1-4 is set to 11".

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the test pits of the Hamming code generated from the request signal to the storage device are held until the timing when the response signal is returned from the storage device, and this held information and the response signal are combined. By configuring the system so that an incorrect response signal can be detected from the system, a malfunction of the storage device can be quickly detected with a small amount of hardware, and this has a great effect on improving the reliability of the information processing system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention;
2 is a time chart for explaining the operation of the embodiment of FIG. 1, and FIG. 3 is an ECG diagram of the embodiment of FIG.
4 is a circuit diagram showing a specific example of the configuration of the error detection circuit in the embodiment shown in FIG. 1. FIG. 5 is a circuit diagram showing a specific example of the error detection circuit in the embodiment shown in FIG. FIG. 3 is a diagram showing the state of an unauthorized response signal that is decoded in FIG. In the figure, 1 is an arithmetic processing unit, 2-1 to 2-16°4
is a storage device, 3 is an ECG circuit, 5 is an error detection circuit, 6
is a register, 7 is a conversion circuit, 8 is an address register, 9
is an addition circuit, 10 is a subtraction circuit, 11-1 to 11-16 are error flags, 21-1 to 21-6° 31-1 to 31-
6 is an exclusive OR circuit, and 32 is a decoding circuit. Figure 3

Claims (1)

[Claims] 1. In a storage device applied to an information processing system consisting of a plurality of storage devices that are accessed at a constant and the same access time and devices that access these storage devices, access of the storage device means for supplying time; means for degenerating the access information sent from the access device to each of the storage devices into a 1-bit or multiple-bit test code for the access information; and a means for degenerating the degenerate test code. comprising means for holding for a period determined by the access time, and response information checking means for checking response information sent from each storage device to the access device using a check code held in the holding means. A storage device malfunction detection method characterized by: