JPH01205251A - Memory data checker - Google Patents

Abstract

PURPOSE:To execute a data check to be always correct by detecting an error contained in data by means of the complete comparison of two data read from a memory. CONSTITUTION:The title checker is equipped with a memory 11 to store the same data of 8 bits in two storing positions to be mutually different, a latch circuit 12 to temporarily hold one side of the data stored in the memory 11, a comparing circuit 13 to compare the data of one side held in the latch circuit 12 and the data of the other side stored in the memory 11, an AND gate circuit 14 for controlling the output of the comparing circuit 13, and a control circuit 15 to control the latch circuit 12 and AND gate circuit 14 based on the reading timing of the data stored in the memory 11. By completely comparing two data read from the memory 11, the error contained in the data can be detected. Thus, the data check to be always correct can be executed.

Description

[Detailed Description of the Invention] "Industrial Application Field" The present invention provides a method for reading data stored in a memory.
The present invention relates to a memory data checking device for checking whether or not this data is proper.

``Prior Art'' As a conventional memory data check device, one based on a parity check method is known.

FIG. 3 shows an example of a circuit employing this method. This circuit performs a parity check on data transmitted through the path of driver 1, memory 2, and receiver 3, and includes a parity generator 4, parity checker
5. It is equipped with a memory 6.

First, the transmission data supplied to the driver 1 is supplied to the parity generator 4 byte by byte.
A parity bit is generated according to the combination of "and o". This parity bit is stored at a predetermined location in the memory 6, and is read out from the memory 6 when the corresponding transmission data is read out from the memory 2. This parity bit is then supplied to the parity checker 5 together with the transmission data, and the suitability of the transmission data is determined based on the combination of these bits.

FIGS. 4A-4C explain the principle of such a parity check. In this example, even parity is generated in the parity generator 4, and the transmission data D1 and the parity bit b are "1".
The parity bit b is determined so that the sum of the numbers becomes an even number (FIG. 4A).

Therefore, as shown in 4N8, if the sum of "1"' on the parity checker 5 side is an even number, the transmitted data is determined to be proper, and as shown in FIG. For example, the transmitted data is determined to be invalid.

"Problem to be solved by the invention" However, in this parity check method,
Since the suitability of data is judged based on even numbers and odd numbers, there is a problem in that if the transmitted data contains two invalid bits, the false transmitted data may be mistakenly determined to be valid.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a memory data check device that can always perform accurate data checks.

[Means for Solving the Problems] The memory data check device of the present invention has the following configuration requirements A to D in order to achieve the above-mentioned objects.

(Δ) A memory that stores the same data in two different storage locations. This memory is one in which data can be freely written, and for example, a dynamic RAM (random access memory) is employed.

(B) A reading means for sequentially reading two pieces of data stored in this memory. This is composed of a dynamic RAM control circuit and the like.

(C) A latch means for latching one of the two data read out from the memory first. For example, it is constituted by a flip-flop circuit or the like.

(D) Comparison means for comparing one data latched by the latch means and the other data read later from the memory. This is to perform a complete comparison of data by determining whether each digit of both data matches.

In such a memory data checking device, accurate data checking can be performed by completely comparing two pieces of data read from the memory.

"Example" The present invention will be described in detail with reference to Examples below.

As shown in FIG.
a memory 11 for storing data in two storage locations;
a latch circuit 12 that temporarily holds one of the data stored in the memory IJ 11; a comparison circuit 13 that compares one data held in the latch circuit 12 with the other data stored in the memo IJ 11; An AND gate circuit 14 for controlling the output of the comparison circuit 13 and a latch circuit 12 that sequentially reads data stored in the memory 11 in nibble mode and based on this read timing.
and a control circuit 15 that controls the AND gate circuit 14.

The memory 11 is configured by combining eight bit-node dynamic RAMs, for example, 256, and one row address signal (row address 5 trobe).
After loading, two column address signals (column
By sequentially taking in the data (address 5trobe), two pieces of 1-foot data are sequentially written or read within one memory cycle.

The latch circuit 12 is configured to store a 1-byte data, and is designed to store 1-byte data read out from the memo I311 in accordance with the first column address signal. Note that the data latched by the latch circuit 12 is output to a processing circuit (not shown) as data to be actually used.

The comparison circuit 13 compares the 1-byte data read from the memory 1 by the second column address signal and the 1-byte data already latched in the latch circuit 12,
If the two do not match, an error signal is supplied to one input terminal of the AND gate circuit 14.

The control circuit 15 performs address designation of the memory 11, data write/read control, and controls such as latching and unlatching of the latch circuit 12. The control circuit 15 also supplies a strobe signal for error detection to the other input terminal of the AND gate circuit 14, and the above-mentioned error signal is output from the AND gate circuit 14 at the timing of this strobe signal. Output.

FIG. 2 is a timing diagram illustrating the operation when reading data in the memory data checking device as described above.

First, the control circuit 15 outputs a row address signal (a in the figure), and when the first column address signal is output (b in the figure), data is read from the memory 11 (a in the figure). C) is latched by the latch circuit 12 (d in the figure). As the latch circuit 12 latches, the data taken into the latch circuit 12 is output as data to be used (e in the figure). Furthermore, when the second column address signal is output (b in the figure), data is read from the memory 11 (c in the figure).
, is supplied to the comparison circuit 13, and the latch circuit 12
The data latched in is taken into the comparator circuit 13, and the two are compared. The output of this comparison circuit 13 (f in the figure) is supplied to one input terminal of the AND gate circuit 14, and if the comparison result does not match, a strobe signal (g in the figure) is sent from the control circuit 15. An error signal is output from the AND gate circuit 14 (h in the figure) and supplied to the processing circuit side. In this way, errors contained within the data can be detected. Note that the processing circuit executes a predetermined error correction process by receiving the error signal.

As described above, in this embodiment, two pieces of data are sequentially read in the nibble mode and a data check is performed, so this processing can be performed within one memory cycle, and the overall processing time can be shortened. effective.

In addition, by reading two pieces of data in sequence, the number of memory chips can be reduced to half compared to reading two pieces of data in parallel within one memory cycle.
This has the effect of reducing mounting space.

"Effects of the Invention" As explained above, according to the present invention, errors contained in the data are detected by a complete comparison of two pieces of data read from the memory, making it possible to perform an accurate data check. effective.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing a memory data check device according to an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining the operation when reading data in the memory data check device of the same embodiment. 3 is a block diagram showing a memory data check device using a parity check method as a conventional technique, and FIGS. 4A to 4C are explanatory diagrams explaining the principle of parity check in the memory data check device shown in FIG. be. 11... Memory, 12... Latch circuit, 13... Comparison circuit, 14... AND gate circuit, 15... Control circuit. Applicant Fuji Xerox Co., Ltd. Agent
Patent Attorney Umeo Yamauchi Figure 1 Figure 2 (hl Error f words Figure 3 Figure 4

Claims (1)

[Scope of Claims] A memory that stores the same data in two different storage locations; a reading device that sequentially reads out the two data stored in the memory; and a device that reads out the two data from the memory first. A memory characterized by comprising: latch means for latching one of the data latched by the latch means, and comparison means for comparing one data latched by the latch means and the other data read later from the memory. Data checking device.